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CONTENTS REVISION HISTORY
SCHEMATIC Name SHEET Date Author Ver Comments
D 01.Contents & History 1 2012/08/27 Jeff/Jerry 1.00 For SR stage. D
2012/09/14 Jeff/Jerry 1.01 For SR2 stage.
02.TV System Power Budget 2
2012/10/20 Jeff/Jerry 1.02 For ER stage.
03.MB Block Diagram 3 2012/11/07 Jeff/Jerry 1.03 For ER2 stage.
2012/11/21 Jeff/Jerry 1.03a For PR stage.
04.DC to DC 4
05.MSD8841-3A3D&USB&AUDIO 5
06.MSD8841-DDR&LVDS&GPIO 6
07.MSD8841_POWER 7
08.MSD8841-CI&TFE&TS&NAND 8
C 09.MEMORY DDR3 9 C
10.PCMCIA CONN 10
11.HDMI and MHL 11
12.VGA 12
13.COMPONENT and AV 13
14.SCART 14
15.SPEAKER&EARPHONE AMP 15
16.TUNER 16
B 17.LVDS 17 B
18.SPDIF 18
19.USB 19
20.NAND FLASH 20
21.Ethernet CONN 21
22.MSB1230 22
23.IR_ALS 23
A A
Title : Contents&History
MAIN BOARD Engineer: Jeff Y Hsiao/Jerry Lo
Size Project Name Rev
B L2300 1.03a
Date: Thursday, December 20, 2012 Sheet 1 of 23
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TV System Power Budget Block Diagram
AC 220~240
+5V_Standby 1307mA +5V_Normal
U2 +3.3V_Normal DEMOD U24
3947mA DC/DC MSB1230-LF
1047mA
NORMAL_PWR_CTL 1047mA AVDD_SAR_T2(Pin33)
PSU Unit TPS5432DDAR Enable_Control
U21 55mA AVDD33_ADC_T2(Pin36)
Enable_Control
32"/39"/50" GPIO_12V_EN LDO AVDD_MPLL_T2(Pin43)
80mA RT9043-GB AVDD_APLL_TS/SDR_T2(Pin47)
GPIO_OCP_OUTPUT_PWM 240mA U17 TUNER_3.3V TU1 VDD33_T2(Pin7,18,28,31,50,53,60)
D +5V_Standby LDO TUNER Power on Max. current= 55mA D
GPIO_BL_EN APE1117AK-HF 240mA SUT_RE221
25mA U23 SPI_Flash
ACDetect
10mA EN25F20-100GCP
SCANNING_BL_EN SPDIF_OUT CIRCUIT Power on Max. current= 25mA
+12V_Normal 10mA
SC_CVBS_OUT CIRCUIT 445mA
DT2_2.5V U24
U21 443mA 43mA MSB1230-LF
Enable_Control LDO AVDD25_ADC_T2(pin42)
LIPS U7 +5V_Normal RT9025_25PSP Power on Max. current= 43mA
MSD8841BX_BGA20x20
AVDD_ALIVE(ball=N7)= 17.31mA U24
AVDD_DVI(ball=L7,K7)= 18.64mA MSB1230-LF
32WX/32FHD/39FHD/50FHD AVDD_DMPLL(ball=P6)= 6.01mA DT2_2.5V VDDC1(Pin9)
LED Driver 330mA U1 +3.3V_Standby 400mA
56mA AVDD_MPLL(ball=M8)= 13.24mA VDDC2(Pin20)
LDO Power on Max. current= 55.2mA U22 DT2_1.2V VDDC3(Pin30)
+5V_Standby RT9043-GB 330mA LDO
Standby Max. current= 2.912mA Enable_Control VDDC4(Pin51)
Enable_Control RT9025_25PSP 400mA
+5V_Normal VDDC5(Pin59)
U8 Reset IC Power on Max. current= 400mA
20mA
G690H293T73UF
Power on Max. current= 20mA
PANEL_VCC Standby Max. current= U7 U7
+12V_Normal 0.7A Panel _Tcon
MSD8841BX_BGA20x20 MSD8841BX_BGA20x20
45mA U11 SPI Flash VDDP(ball=R19,T19)= 8.59mA AVDD_ADC(ball=V8,W7,W8)= 36.2mA
32WX/32FHD 50mA
GPIO_Panel_VCC_ON W25Q64FVSSIG AVDD_AU(ball=T7)= 17.32mA 105.24mA AVDD25_PGA(ball=W11)= 0.01mA
C
Power on Max. current= 45mA C
AVDD_EAR(ball=R7)= 5.08mA AVDD_REF(ball=W9)= 0.43mA
Standby Max. current= 0.05mA
1.3A AVDD_LPLL(ball=W17,W18)=18.19mA AVDD_LAN(ball=W14)= 15.3mA
AMP(7W+7W) Power on Max. current= 49.18mA AVDD_MOD(ball=V16,W16)= 53.3mA
96mA U27 MHL to HDMI
MSG1200 Power on Max. current= 105.24mA
Amp efficiency:85% , Devition 5% 110mA U5
Power on Max. current= 95.12mA +2.5V_Normal
Standby Max. current= 1.12mA LDO
U19 TS21C_HF
RT9043-GB 105.24mA
PANEL_VCC Enable_Control
U3 +1.2V_Standby_MHL U27 MHL to HDMI
+12V_Normal 0.7A Panel _Tcon 85mA LDO MSG1200 200mA
85mA Power on Max. current= 85mA U4 U7
39FHD RT9043-GB +1.5V_Normal
GPIO_Panel_VCC_ON Standby Max. current= 0.58mA DC/DC MSD8841BX_BGA20x20
RT8059GJ5 AVDD_DDR0(ball=J17,K15,K16,L15)= 57.5mA
530mA
AVDD_DDR1(ball=K17,L17,M17,L16)= 52.5mA
Enable_Control
1.3A 15mA IR_ALS Board Power on Max. current= 110mA
AMP(7W+7W) ((530mA/1000)*1.5)/(0.8)/5= 0.198
Power on Max. current= 15mA
Amp efficiency:85% , Devition 5% Standby Max. current= U12 DDR3 Memory
U18 NAND Flash
H5TQ2G63DFR-PBC
30mA H27U2G8F2C VDD1..9(ball=N1,R1,B2,K2,G7,K8,D9,N9,R9)
U27 MHL to HDMI VCC1(Pin12)
PANEL_VCC 0.046mA LED_Board VCC2(Pin37) VDDQ1..9(ball=A1,C1,F1,D2,H2,A8,C9,E9,H9)
MSG1200 10mA
+12V_Normal 0.7A Panel _Tcon Power on Max. current= 30mA Power on Max. current= 210mA
Power on Max. current= 0.046mA Power on Max. current= 10mA
50FHD Standby Max. current= 0.046mA Standby Max. current= 20mA U13 DDR3 Memory
GPIO_Panel_VCC_ON pull high Resistor
Power on Max. current= 20mA H5TQ1G63DFR-PBC
U6 U7 VDD1..9(ball=N1,R1,B2,K2,G7,K8,D9,N9,R9)
410mA +1.2V_Normal
1.3A DC/DC MSD8841BX_BGA20x20 Headphone VDDQ1..9(ball=A1,C1,F1,D2,H2,A8,C9,E9,H9)
AMP(7W+7W) +3.3V_Normal VDDC (ball=G9,H9,K10,K11,L10,M12,M13, 4mA Amplifier Power on Max. current= 210mA
TPS5432DDAR 1339mA N12,P14,P15,R10,R14,R15,T10)= 1266.25mA
Enable_Control
B
Amp efficiency:85% , Devition 5% B
Power on Max. current= 4mA
((1340mA/1000)*1.2)/(0.8)/5= 0.402 DVDDC(ball=M14)(DVDD_DDR)= 55.5mA
AVDDLV_USB(ball=K12)= 1.08mA U16 Audio
AVDDL_MOD(ball=R16)= 7.8mA 83mA TAS5707L Power
AVDD11_ETH(ball=L11)= 0.67mA TAS5707L= 83mA Amplifier
AVDD1P1(ball=P10)= 7.7mA Power on Max. current= 83mA
Power on Max. current= 1339mA
U14 Line Driver
25mA DRV632PWR
USB_5V VDD(Pin 9)
1900mA 500mA(Min). USB Power on Max. current= 25mA
GPIO_USB1_PWR_SW VCC-PCMCIA
500mA(Min).
PCMCIA
GPIO_PCM_5V_CTL +5V_HDMIC
900mA(Max).
MHL
PS_CTRL#
A A
Title : TV System Power Budget
MAIN BOARD Engineer: Jeff Y Hsiao/Jerry Lo
Size Project Name Rev
D L2300 1.03a
Date: Thursday, December 20, 2012 Sheet 2 of 23
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DDR BUS 2G DDR3 Vender:
TS0 DDR3 2GBit
DVB-T/T2/C PCMCIA SLOT 1st: Hynix H5TQ2G63DFR-PBC
TS1 DDR3-1600 11-11-11/ 64MB*16
DIF
Silcon DDR BUS 2nd: Samsung K4B2G1646E-BCK0000
D
TS DDR3 1GBit DDR3-1600 11-11-11/ 64MB*16 D
Tuner SPI Flash MSB-1230 Tuner I2C BUS
2Mbit Demod 1G DDR3 Vender:
1st: Hynix H5TQ1G63DFR-PBC
DDR3-1600 11-11-11/ 64MB*16
SPI FLASH BUS
Tuner I2C BUS 2nd: Samsung K4B1G1646G-BGK0
DDR3-1600 11-11-11/ 64MB*16
RGB-In/H/V/DDC
VGA
SPI FLASH BUS SPI Flash 1st: Windbond W25Q64FVSSIG
L/R-In
VGA Phone Jack 64MBit 2nd:
HDMI ---ARC
CEC CEC
NAND FLASH BUS NAND Flash 1st: Hynix H27U2G8F2C
C HDMI 1 TDMS-A In/DDC C
2GBit 2nd: Toshiba TC58NVG1S3ETA00
CEC
TDMS/CBUS MHL TDMS-B In/DDC
HDMI 2
HDMI 3
CEC
MSG1200
TDMS-C In/DDC
MSD8841BX
2 CH LVDS
CEC Panel Unit
HDMI 4 TDMS-D In/DDC
Ethernet-Tx/Rx
L/R-Out AMP TS21C_HF RJ-45
AV Out DVR632
B
SCART(Full) RGB In/AV In B
L/R OUT
L/R-In TPA6132 Earphone
YPbPr In
I2S BUS
Component L/R-In
I2C BUS TAS5707L SPEAKER
AV In
Composite
Input+L/R L/R-In SAR I/F
Power KEY "+" KEY "-" KEY P/V/AV KEY
DP0/DM0 IR In
USB 0
I2C BUS IR/ALS Board
DP1/DM1
A A
USB 1(SIDE)
LED I/F
LED Board
SPDIF_Out Title : Block Diagram
SPDIF out Engineer: Jeff Y Hsiao/Jerry Lo
MAIN BOARD
Size Project Name Rev
B L2300 1.03a
Date: Thursday, December 20, 2012 Sheet 3 of 23
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+12V_Normal
CN1
14 FB1 1 2 120Ohm NC G3
13 FB2 1 2 120Ohm C429 C8 C9 +5V_Standby +3.3V_Standby G1
1
1
1
12 C3 C5 C6 U1 RT9043-GB 1 9 1 9
NP_NC GND8 NP_NC GND8
1
1
1
11 1 5 2 8 2 8
+5V_Standby VIN VOUT GND1 GND7 GND1 GND7
4.7UF/25V
0.1UF/16V
0.1UF/16V
10 2 3 7 3 7
2
2
2
GND GND2 GND6 GND2 GND6
1
1
1
1
10UF/10V
1000PF/50V
0.1UF/16V
9 3 4 C15 C16 4 6 4 6
2
2
2
EN FB GND3 GND5 GND3 GND5
1
1
8 FB3 1 2 120Ohm C13 C14 R12 R13 5 5
GND4 GND4
12KOhm
1UF/16V
0.1UF/16V
7 FB4 1 2 120Ohm 180KOHM
2
2
1UF/16V
0.1UF/16V
6 C315D157N C315D130N
2
2
D 5 R144 1 2 0 Ohm D
SCANNING_BL_EN 6