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PCB STACK UP
LAYER 1 : TOP
CT8 BLOCK DIAGRAM
LAYER 2 : GND
DDR CPU THERMAL CLAW HAMMER / RS480 / SB400
LAYER 3 : IN1 DDR-SODIMM1 266,333,400MHz SENSOR
GMT-781
A
LAYER 4 : IN2 CPU CLAW HAMMER 14.318MHz A

SYSTEM POWER MAX1845
LAYER 5 : VCC CPUCLK, (1.2V/NB_CORE/1.25V)
DDR-SODIMM2 754 Pins (uPGA) CPUCLK#
LAYER 6 : BOT CLOCK GEN
CY28RS480/ ICS951412 CPU CORE MAX1544
SBLINKCLK, SBLINKCLK#
POWER 1.2V
HyperThansport I/O BUS NBSRCCLK, NBSRCCLK#
Link 16x16 HTREFCLK
CABLE DOCK
SYSTEM MAX1999
POWER(3/5V)
R.G,B OSC14M
Daughter Board CRT port
TV, USB, BLUE TOOTH NORTH BRIDGE SYSTEM POWER MAX1845
LVDS X1 RS480M (2.5VSUS/1.8VSUS)
LCD Panel
705 BGA
Power Board INTEGRADED VGA FUNCTION
B TV-OUT Based on Redeon 9600 B
S-VIDEO BATT CHARGER
MAX1722
A-LINK
32.768KHz 2X
PCI-E DISCHARGE
NBSRCCLK, NBSRCCLK#
USB PORT 0, 1, 2 USB 2.0
33MHZ, 3.3V PCI
PCLK_7411
PCLK_MINI
1st IDE - HDD ATA 66/100/133 SB400 24.576MHz 48MHz
PCLK_LAN
564 BGA AC97
2nd IDE - CDROM
ATA 66/100/133
PWRCLKP AC97 LAN MINI-PCI CARDBUS / IEEE 1394
PWRCLKN CX20468-31 Realtek CONTROLLER/CF
C DIB_DATAN C
DIB_DATAP MBAMC20493-010 8100CL TI 7411

PCI DEVICES IRQ ROUTING 32.768KHz PCLK_591
24.576MHz 25MHz
3.3V LPC, 33MHz
DEVICE IDSEL # REQ/GNT # PCI_INT
GBIT ETHERNET AD16 2 C
MINIPCI SLOT AD18 1 E,F SMARTDAA AMP 5 IN 1 CARDBUS 1394
CardBus/1394 AD25 4 B,D,G MODEM, CARD SLOT X1 CONN
PC97551 TPA0312 READER
SD/MMC,
TQFP 176 SM, MS,
XD
WIRE


RJ11 JACK RJ45
D FAN Touchpad Keyboard FLASH HEADPHONE, D
JACK JACK
2ND HEADPHONE,
MIC
PROJECT : CT8
Quanta Computer Inc.
Size Document Number Rev
Custom BLOCK DIAGRAM 1A

Date: Thursday, April 14, 2005 Sheet 1 of 42
1 2 3 4 5 6 7 8
5 4 3 2 1




CLK +3V CLK_VDD 20 Mils
NBSRCCLK
NBSRCCLK#

SBSRCCLK
NBSRCCLK 7
NBSRCCLK# 7

SBSRCCLK 12
L39 40 Mils +3V SBSRCCLK#
SBSRCCLK# 12
TI201209G121
CLK_VDDA L42 SBLINKCLK
SBLINKCLK 7
C478 C485 C497 C496 C488 C480 C483 C491 C498 TI201209G121 SBLINKCLK#
22U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 0.1U SBLINKCLK# 7
C492 C494

0.1U 22U
D D




CLK_VDD
U23

43 VDDCPU VDDA 39
14 VDDSRC3 GNDA 38
21 VDDSRC2
EMI 32 45 CPUCLK8T0 R288 15/F
+3V VDDSRC1 CPUCLK8T0 CPUCLK 3
REV.C 35 44 CPUCLK8C0 R291 15/F
VDD_SRC0 CPUCLK8C0 CPUCLK# 3
51 VDD_PCI CPUCLK8T1 41 T128
3 VDD48 CPUCLK8C1 40 T297
SBK160808T-301Y-S 48
L40 VDDHTT SRCCLKT7 R286 33 SBSRCCLK R285 49.9/F
56 VDDREF SRCCLKT7 12
C482 13 SRCCLKC7 R290 33 SBSRCCLK# R289 49.9/F
C749 C750 SRCCLKC7 SRCCLKT6 R296 33 NBSRCCLK R295 49.9/F
5 GND1 SRCCLKT6 16
0.1U 2.2U 0.1U 55 17 SRCCLKC6 R298 33 NBSRCCLK# R297 49.9/F
GND2 SRCCLKC6 SRCCLKT5 R301 33 SBLINKCLK R300 49.9/F
36 GNDSRC0 SRCCLKT5 18
SRCCLKC5 R303 33 SBLINKCLK# R302 49.9/F
REV.B 31
26
GNDSRC1
GNDSRC2
SRCCLKC5
SRCCLKT4
19
22 T131
20 GNDSRC3 SRCCLKC4 23 T299
C320 27P 15 24
GNDSRC4 SRCCLKT3 T301
49 GNDPCI SRCCLKC3 25 T306




1
Parallel Resonance Crystal Y2 R83
46
42
GNDHTT SRCCLKT2 27
28
T305
T302
GNDCPU SRCCLKC2
Tolerance: 35ppm (max) *1M
1
SRCCLKT1 30
29
T304
X1 SRCCLKC1 T303
C
Load: 20pf 14.318MHZ C




2
SRCCLKT0 34 T298
C479 27P 2 33
X2 SRCCLKC0 T300
REV.B CLK_VDD
6 50 R283 *4.7K CLK_VDD
T296 NC SEL75#/100/PCICLK0
1.Remove R84.

7 R274 R277 R276
9,10,13 SCLK SCLK
8 10K 10K 10K
9,10,13 SDATA SDATA R273 *22 CLK FREQ
SB_OSC_INT 7,13
R281 33 SELECT
7 OSC14M 52 REF2
54 R275 *10K
FS0/REF0 R280 *10K
37 IREF FS1/REF1 53
9 R279 *10K
Ioh = 5 * Iref R304 FS2
(2.32mA)
475/F 4 R278 33
USB_48MHz USBCLK_EXT 13
Voh = 0.71V @ 60 ohm 47 R284 33
HTTCLK0 HTREFCLK 7
11 CLKREQB#
10 R287
CLKREQA#
51.1
ICS951412

R292 R282
*10K *10K

B
Operating Current: 400mA B




Layout Note:
1- PLACE ALL THE SERIES TERMINATION RESISTORS AS CLOSE AS
CKG. AS POSSIBLE
EXT CLK FREQUENCY SELECT TABLE(MHZ)
2- ROUTE ALL CPUCLK/#, NBSRCCLK/#, SBSRCCLK/#, SBLINKCLK/# AS
DIFFERENT PAIR RULE FS2 FS1 FS0 CPU SRCCLK HTT PCI USB COMMENT
[2:1]
3- PUT DECOUPLING CAPS CLOSE TO CKG. POWER PIN
0 0 0 Hi-Z 100.00 Hi-Z Hi-Z 48.00 Reserved
0 0 1 X 100.00 X/3 X/6 48.00 Reserved
0 1 0 180.00 100.00 60.00 30.00 48.00 Reserved
0 1 1 220.00 100.00 36.56 73.12 48.00 Reserved
1 0 0 100.00 100.00 66.66 33.33 48.00 Reserved
1 0 1 133.33 100.00 66.66 33.33 48.00 Reserved

A
1 1 1 200.00 100.00 66.66 33.33 48.00 Normal HAMMER operation A




PROJECT : CT8
Quanta Computer Inc.
Size Document Number Rev
Custom EXT CLOCK GENERATOR 3A

Date: Thursday, April 14, 2005 Sheet 2 of 42
5 4 3 2 1
5 4 3 2 1




CPU VDDA_1V2 U22A
AMD K8
LDT
VDDA_1V2
20 Mils width to pin
100 Mils width to capacitor
250 Mils width to PWM T124 U22C
AMD K8
CTL & DBG
R76

169/F
Near Socket754

CPU_CLK C295 3900P
CPUCLK 2
B27 AF25 CPU_CLK# C296 3900P
V_HT0_A0 V_HT0_B0 CPUCLK# 2
B29 AE28 LDT_RST# AF20 A20 THERMTRIP#
V_HT0_A1 V_HT0_B1 12 LDT_RST# RESET# THERMTRIP#
C26 AF29 CPUPWRGD AE18 FBCLKOUT# R78 80.6/F FBCLKOUT
V_HT0_A2 V_HT0_B2 LDTSTOP# PWROK THERMDA
C28 V_HT0_A3 V_HT0_B3 AG26 7,12 LDTSTOP# AJ27 HT_STOP# THERMDA A26
D25 AG28 A27 THERMDC
V_HT0_A4 V_HT0_B4 L0_REF1 THERMDC
D27 V_HT0_A5 V_HT0_B5 AH27 AF27 L0_REF1
CADIP[0..15] D29 AH29 CADOP[0..15] L0_REF0 AE26 AJ28
5 CADIP[0..15] V_HT0_A6 V_HT0_B6 CADOP[0..15] 5 L0_REF0 KEY0 T294
D KEY1 A28 T97 D
CADIP15 T25 N26 CADOP15 COREFB A23
HT_RXD15 HT_TXD15 40 COREFB COREFB
CADIP14 U27 L25 CADOP14 COREFB# A24
HT_RXD14 HT_TXD14 40 COREFB# COREFB#
CADIP13 V25 L26 CADOP13 B23
HT_RXD13 HT_TXD13 T96 CORE_SENSE
CADIP12 W27 J25 CADOP12 AG18
HT_RXD12 HT_TXD12 NC_BP3 T118
CADIP11 AA27 G25 CADOP11 AE12 AH18
HT_RXD11 HT_TXD11 T121 VDDIOFB NC_BP2 T295
CADIP10 AB25 G26 CADOP10 AF12 AG17 NC_AG17
HT_RXD10 HT_TXD10 T120 VDDIOFB# NC_BP1
CADIP9 AC27 E25 CADOP9 VDDIO_SENSE AE11 AJ18 NC_AJ18
CADIP8 HT_RXD9 HT_TXD9 CADOP8 VDDIO_SENSE NC_BP0
AD25 HT_RXD8 HT_TXD8 E26
CADIP7 T27 N29 CADOP7 CPU_CLK AJ21 AJ23 NC_AJ23
CADIP6 HT_RXD7 HT_TXD7 CADOP6 CPU_CLK# CLKIN NC_BPSCLK NC_AH23 680-8P4R
V29 HT_RXD6 HT_TXD6 M28 AH21 CLKIN# NC_BPSCLK# AH23 RN1
CADIP5 V27 L29 CADOP5 1 2 NC_D20 VCC_CORE
CADIP4 HT_RXD5 HT_TXD5 CADOP4 FBCLKOUT NC_C19
Y29 HT_RXD4 HT_TXD4 K28 AH19 FBCLKOUT NC_PLLCHZ AE24 T122 3 4
CADIP3 AB29 H28 CADOP3 FBCLKOUT# AJ19 AF24 5 6 NC_B19 R42 51 COREFB
HT_RXD3 HT_TXD3 FBCLKOUT# NC_PLLCHZ# T123
CADIP2 AB27 G29 CADOP2 7 8 NC_C21
CADIP1 HT_RXD2 HT_TXD2 CADOP1 NC_D20 R41 51 COREFB#
AD29 HT_RXD1 HT_TXD1 F28 VDDA_2.5V AH25 VDDA1 NC_SCANCLK1 D20
CADIN[0..15] CADIP0 AD27 E29 CADOP0 CADON[0..15] AJ25 C21 NC_C21 R34 680 NC_D18
5 CADIN[0..15] HT_RXD0 HT_TXD0 CADON[0..15] 5 VDDA2 NC_SCANCLK2
D18 NC_D18 R265 680 NC_AG17
CADIN15 CADON15 NC_SCANEN NC_C19 R256 680 NC_AJ18
R25 HT_RXD#15 HT_TXD#15 N27 NC_SCANSHENB C19
CADIN14 U26 M25 CADON14 VID0 AE15 B19 NC_B19 VDDA_1V2
HT_RXD#14 HT_TXD#14 40 VID0 VID0 NC_SCANSHENA
CADIN13 U25 L27 CADON13 VID1 AF15
HT_RXD#13 HT_TXD#13 40 VID1 VID1
CADIN12 W26 K25 CADON12 VID2 AG14 D22 R262 44.2/F L0_REF1
HT_RXD#12 HT_TXD#12 40 VID2 VID2 NC_RSVD_SCL T93
CADIN11 AA26 H25 CADON11 VID3 AF14 C22
HT_RXD#11 HT_TXD#11 40 VID3 VID3 NC_RSVD_SDA T82
CADIN10 AA25 G27 CADON10 VID4 AG13 STUFF WHEN CONFIGURED AS 16-BIT LINK R261 44.2/F L0_REF0
HT_RXD#10 HT_TXD#10 40 VID4 VID4
CADIN9 AC26 F25 CADON9 A19 NC_A19
CADIN8 HT_RXD#9 HT_TXD#9 CADON8 NC_BRN# VDDA_1V2 C762 C763
AC25 HT_RXD#8 HT_TXD#8 E27 REV.D
CADIN7 T28 P29 CADON7 C15
HT_RXD#7 HT_TXD#7 NC_DCLKTWO T68 +2.5V
CADIN6 U29 M27 CADON6 DBRDY AH17 R56 49.9/F CTLIP1 ESD
HT_RXD#6 HT_TXD#6 JTAG6 DBRDY
CADIN5 V28 M29 CADON5 DBREQ# AE19 C18 NC_C18 *330p *330p
HT_RXD#5 HT_TXD#5 JTAG7 DBREQ# NC_SINCHN
CADIN4 W29 K27 CADON4 R57 49.9/F CTLIN1 R268 680 LDT_RST#
CADIN3 HT_RXD#4 HT_TXD#4 CADON3 TMS
AA29 HT_RXD#3 HT_TXD#3 H27 JTAG5 E20 TMS
CADIN2 AB28 H29 CADON2 TCK E17 AF21 R260 680 LDTSTOP#
C HT_RXD#2 HT_TXD#2 JTAG1 TCK NC_ANALOG0 C
CADIN1 AC29 F27 CADON1 TRST# B21 AF22