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HBL50 Schematics Document
Intel Yonah Processor with 945GM/945PM + DDRII + ICH7M
(With nVIDIA G73M/72MV)
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2005-11-08 3
REV: 0.3
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 1 of 59
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Compal Confidential
Thermal Sensor Clock Generator
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Model Name : HBL50 Fan Control
page 47
Yonah
F75383M ICS9LPRS325
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File Name : LA-2921 uPGA-478 Package
page 4,5
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PSB
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H_A#(3..31) 533/667MHz H_D#(0..63)
DVI-D Conn. LCD Conn. CRT & TV-out
page 25 page 23 page 24
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DVI LVDS Memory BUS(DDRII) 200pin DDRII-SO-DIMM X2
Intel 945PM/GM Dual Channel page 12,13
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CH7307C SDVO BANK 0, 1, 2, 3
page 25 1.8V DDRII 400/533
DVI LVDS uFCBGA-1466
w nVidia G73M/(72M)/72MV
with 64/128/256MB VRAM
page 15,16,17,18,19,20,21,22
PCI-Express page 6,7,8,9,10,11
DMI New Card
Socket page 37
LAN(GbE)
BCM5789
page 34
MINI CARD x2
page 36
USB conn x4
page 37
Bluetooth
Conn page 42
PCI Express USB port 3, 7 USB port 0, 2 USB port5
PCI BUS USB port 1
2
3.3V 33 MHz Intel ICH7-M 3.3V 48MHz 2
IDSEL:AD16 IDSEL:AD18 IDSEL:AD17 IDSEL:AD20 3.3V 24.576MHz/48Mhz HD Audio
(PIRQE#, (PIRQG/H#, (PIRQF#, (PIRQA#, BGA-652
GNT#2, GNT#3, GNT#3, GNT#2, 3.3V ATA-100
REQ#2) REQ#3) REQ#3) REQ#2) IDE
S-ATA
page 26,27,28,29
IEEE 1394 Mini PCI LAN (10/100) CardBus
VT6311S socket BCM4401E ENE CB714 CDROM MDC 1.5 HDA Codec
page 38 (WLAN) page 34 page 32 port 0 port 0 Conn. 31 Conn 42 ALC883
page page page 44
(TV-Tuner)
page 36
1394 Conn. RJ45 6 in 1 S-ATA HDD SATA-to-IDE HDD
Slot 0 socket SPIF3811-HV096
page 38 page 35
page 33 page 33
Conn.page 30 page 30
Conn.
page 30
Audio AMP Subwoofer
LPC BUS page 45 page 46
3 3
RTC CKT. Super I/O TPM1.2 Phone Jack x3
page 43
ENE KB910Q page 45
SMsC LPC47N207 SLB9635 TT 1.2
page 40 page 39 page 39
Power On/Off CKT. Switch/B Conn.
USB port4, 6
page 43
page 42
Touch Pad Int.KBD
page 43 page 41 FIR
TFDU6102-TR3
page 39
DC/DC Interface CKT. CD-PLAY/B Conn. EC I/O Buffer BIOS
page 42
page 48 page 41 page 41
Power Circuit DC/DC MEDIA/B Conn.
page 42
page 49,50,51,52 CIR
53,54,55,56 page 42
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Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 2 of 59
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SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Voltage Rails
Full ON HIGH HIGH HIGH HIGH ON ON ON ON
Power Plane
VIN
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Adapter power supply (19V)
S1
N/A
S3
N/A
S5
N/A
S1(Power On Suspend)
S3 (Suspend to RAM)
LOW
LOW
HIGH
LOW
HIGH
HIGH
HIGH
HIGH
ON
ON
ON
ON
ON
OFF
LOW
OFF
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B+ AC or battery power rail for power circuit. N/A N/A N/A
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S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1
+CPU_CORE Core voltage for CPU ON OFF OFF
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+0.9VS 0.9V switched power rail for DDR terminator ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.05VS 1.05V switched power rail ON OFF OFF
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+1.5VS 1.5V switched power rail ON OFF OFF
+1.8V 1.8V power rail for DDR ON ON OFF Board ID / SKU ID Table for AD channel
+1.8VS 1.8V switched power rail ON OFF OFF Vcc 3.3V +/- 5%
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+2.5VS 2.5V switched power rail ON OFF OFF Ra/Rc/Re 100K +/- 5%
+3VALW 3.3V always on power rail ON ON ON* Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+3VS 3.3V switched power rail ON OFF OFF 0 0 0 V 0 V 0 V
w+5VALW
+5VS
+VSB
+RTCVCC
5V always on power rail
5V switched power rail
VSB always on power rail
RTC power
ON
ON
ON
ON
ON
OFF
ON
ON
ON*
O
ON
FF
ON*
1
2
3
4
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
0.216 V
0.436 V
0.712 V
1.036 V
0.250 V
0.503 V
0.819 V
1.185 V
0.289 V
0.538 V
0.875 V
1.264 V
5 100K +/- 5% 1.453 V 1.650 V 1.759 V
6 200K +/- 5% 1.935 V 2.200 V 2.341 V
7 NC 2.500 V 3.300 V 3.300 V
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BOARD ID Table BTO Option Table
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
External PCI Devices Board ID PCB Revision BTO Item BOM Structure
Device IDSEL# REQ#/GNT# Interrupts
0 0.1 VGA PM@ + VGA@
CardBus(SD) AD20 2 PIRQA/PIRQB
1 UMA GM@
13 94 AD16 0 PIRQE
2 UMA's DVI 7307@
LAN(10/100) AD17 3 PIRQF
3 LAN(10/100) 4401@
Mini-PCI(WLAN/TV-Tuner) AD18 1 PIRQG/PORQH
4 LAN(GIGA) 5789@
5 MINI CARD1 MINI1@
6 MINI CARD2 MINI2@
7 SATA-to-IDE 3811@
PATA PATA@
SKU ID Table GRAPEVINE GRA@
EC SM Bus1 address EC SM Bus2 address G72MV Only G72@
3
Device Address Device Address
SKU ID SKU G73 Only G73@ 3
Smart Battery 0001 011X b Fintek F75383M 1001 100X b
0 PM VRAM X76@
EEPROM(24C16/02) 1010 000X b
1 GM VRAM 64M 64@
GMT G781-1 1001 101X b
2 VRAM 128M 64@+128@
3 VRAM 256M 64@+128@+256@
4 MEDIA/B MEDIA@
5 CIR CIR@
6 FIR FIR@
ICH7M SM Bus address 7 GENEVA GEN@
Device Address
LCM LCM@
Sub-woofer SUB@
Clock Generator 1101 001Xb 5789&5787 8789@
(ICS9LPRS325AKLFT_MLF72)
DDR DIMM0 1001 000Xb
4401&5789 0189@
DDR DIMM2 1001 010Xb
VP1020 VP1020@
INTERNAL MIC INTMIC@
1394 1394@
4 SATA HDD SATA@ 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.3
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HBL50 LA-2921P
Date: Friday, November 11, 2005 Sheet 3 of 59
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JP18A H_D#[0..63]
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H_D#[0..63] 6
H_A#[3..31] H_A#3 J4 E22 H_D#0
6 H_A#[3..31]
H_A#4
H_A#5
L4
A3#
A4#
YONAH D0#
D1# F24 H_D#1
H_D#2 +3VS
M3 E26
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H_A#6 A5# D2# H_D#3 C624
K5 A6# D3# H22
H_A#7 M1 F23 H_D#4 0.1U_0402_16V4Z
D H_A#8 A7# D4# H_D#5 D
N2 A8# D5# G25 1 2
H_A#9 J1 E25 H_D#6
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H_A#10 A9# D6# H_D#7
N3 A10# D7# E23
H_A#11 P5 K24 H_D#8
H_A#12 A11# D8# H_D#9
P2 A12# D9# G24
H_A#13 L1 J24 H_D#10 1 U37
A13# D10#
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H_A#14 P4 J23 H_D#11 C625 1 8
A14# D11# VDD SCLK EC_SMB_CK2 40
H_A#15 P1 H26 H_D#12
H_A#16 A15# D12# H_D#13 2200P_0402_50V7K THERMDA
R1 A16# D13# F26 2 D+ SDATA 7 EC_SMB_DA2 40
H_A#17 H_D#14 2
Y2 A17# D14# K22
H_A#18 U5 H25 H_D#15 THERMDC 3 6
H_A#19 A18# D15# H_D#16 D- ALERT#
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R3 A19# D16# N22
H_A#20 W6 K25 H_D#17 4 5
H_A#21 A20# D17# H_D#18 THERM# GND
U4 A21# D18# P26
H_A#22 Y5 R23 H_D#19
H_A#23 A22# D19# H_D#20 ADM1032ARMZ-2REEL_MSOP8
U2 A23# D20# L25
H_A#24 H_D#21
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R4 A24# D21# L22
H_A#25 T5 ADDR GROUP DATA GROUP L23 H_D#22 F75383M_MSOP8
H_A#26 A25# D22# H_D#23
T3 A26# D23# M23
H_A#27 W3 P25 H_D#24
H_A#28 A27# D24# H_D#25
W5 A28# D25# P22
H_A#29 Y4 P23 H_D#26
H_A#30 A29# D26# H_D#27
W2 A30# D27# T24
H_A#31 Y1 R24 H_D#28
A31# D28# H_D#29
D29# L26
H_REQ#[0..4] H_REQ#0 K3 T25 H_D#30
6 H_REQ#[0..4] REQ0# D30#
H_REQ#1 H2 N24 H_D#31
H_REQ#2 REQ1# D31# H_D#32
K2 REQ2# D32# AA23
H_REQ#3 J3 AB24 H_D#33
H_REQ#4 REQ3# D33# H_D#34 +1.05VS
L5 REQ4# D34# V24
V26 H_D#35
D35# H_D#36
6 H_ADSTB#0 L2 ADSTB0# D36# W25
C H_D#37 C
6 H_ADSTB#1 V4 ADSTB1# D37# U23
U25 H_D#38
D38# H_D#39 ITP_TDI R15 56_0402_5%
D39# U22 2 1
AB25 H_D#40
D40# H_D#41 ITP_TDO R17 56_0402_5%
D41# W22 2 1
Y23 H_D#42
D42# H_D#43 ITP_TMS R16 56_0402_5%
14 CLK_CPU_BCLK A22 BCLK0 D43# AA26 2 1
A21 HOST CLK Y26 H_D#44
14 CLK_CPU_BCLK# BCLK1 D44#
Y22 H_D#45 H_PROCHOT# R500 2 1 75_0402_5%
D45# H_D#46
D46# AC26
AA24 H_D#47 ITP_BPM#5 R18 2 1 56_0402_5%
D47# H_D#48
6 H_ADS# H1 ADS# D48# AC22
E2 AC23 H_D#49 H_IERR# R501 2 1 56_0402_5%
6 H_BNR# BNR# D49#
G5 AB22 H_D#50
6 H_BPRI# BPRI# D50# H_D#51
6 H_BR0# F1 BR0# D51# AA21
H5 AB21 H_D#52
6 H_DEFER# DEFER# D52# H_D#53
6 H_DRDY# F21 DRDY# D53# AC25
G6 AD20 H_D#54
6 H_HIT# HIT# D54#
E4 CONTROL AE22 H_D#55
6 H_HITM# HITM# D55#
H_IERR# D20 AF23 H_D#56
IERR# D56# H_D#57
6 H_LOCK# H4 LOCK# D57# AD24
H_RESET# B1 AE21 H_D#58
6 H_RESET# RESET# D58# H_D#59
D59# AD21