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J 1
Boot Logic Datal Address Bus
r---------------------------------------------~--~Input
I
Data

Buffers
I
8284
SelectMainMem I
I Addres! Addr
SelectinterruDt
SelectENetCtI
Bus
Registe" Decode r SelectENetData

- LS313's
~~~ ---- Addr.
and
Output
Data
8086 Latches
1 K X 16 Load =.4ma
I SeiectLocaJRAM I I
I
I II I
RAM

I I
I I
I
I
ControlBus I Bus
Timine
I
I
'--
III Logic

I I I
I I

II
I

I I I Function ~ I
System
Ethernet

Logic
I---
Decoder
U Bus

Tol From
Transceiver

IntAck

I Loss of Carrier
Pa ritY'E r ro r Interrupt
Collision
VertSvnc Cont rolle r
Systlntrpt
8259A

XEROX Project Ethernet Processor
File Designer Rev Date Page 1

SPG NoteTaker Block Diagram ENETBLOCK.si Ron Freeman A 11/1/79 1 i
------
40 LUSFIVE
.:::g~~:.::g:""'--2~~~ROUND1i8086m n
~~~~r,ROUND2 #aib

_~esH;tReac,i
t:::NetW riteReady
ECMemReady

XtalConnect
1~