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Microcomputer Components
SAB 80C517/80C537 8-Bit CMOS Single-Chip Microcontroller

User's Manual 05.94

Edition 05.95 This edition was realized using the software system FrameMaker®. Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstraße 73, 81541 München © Siemens AG 1995. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.

Revision History

SAB 80C517/80C537 User's Manual Revision History: 04.95 Previous Releases: Page 119 133 141 167 188 360 06.91/10.92/08.93/04.94

Subjects (changes since last revision) Figure 7-33, writing error corrected Pin assignment Table 7-10 corrected Page number reference number corrected Software watchdog timer start: extended description Description of CTF flag modified ROM verification timing: text added

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Table of Contents

Page

1 2 3 3.1 3.2 4 4.1 4.2 4.3 4.4 5 5.1 5.2 5.3 5.4 5.5 6 6.1 6.1.1 6.1.2 6.2 7 7.1 7.1.1 7.1.2 7.1.3 7.1.4 7.1.4.1 7.1.4.2 7.1.4.3 7.2 7.2.1 7.2.1.1 7.2.1.2 7.2.1.3 7.2.1.4 7.2.2 7.2.2.1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Fundamental Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Central Processing Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 CPU Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 External Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Accessing External Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Eight Datapointers for Faster External Bus Access . . . . . . . . . . . . . . . . . . . .29 PSEN, Program Store Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 ALE, Address Latch Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Overlapping External Data and Program Memory Spaces . . . . . . . . . . . . . .33 System Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Hardware Reset and Power-Up Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Reset Function and Circuitries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Hardware Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Reset Output Pin (RO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 On-Chip Peripheral Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Parallel I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Port Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Port 0 and Port 2 used as Address/Data Bus . . . . . . . . . . . . . . . . . . . . . . . .45 Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Port Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Port Loading and Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Read-Modify-Write Feature of Ports 0 through 6 . . . . . . . . . . . . . . . . . . . . . .49 Serial Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Serial Interface 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Operating Modes of Serial Interface 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Multiprocessor Communication Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Baud Rates of Serial Channel 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 New Baud Rate Generator for Serial Channel 0 . . . . . . . . . . . . . . . . . . . . . .58 Serial Interface 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Operating Modes of Serial Interface 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

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Table of Contents

Page

7.2.2.2 7.2.2.3 7.2.2.4 7.2.3 7.2.3.1 7.2.3.2 7.2.3.3 7.2.3.4 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.4 7.4.1 7.4.1.1 7.4.1.2 7.4.2 7.4.3 7.5 7.5.1 7.5.2 7.5.3 7.5.4 7.5.4.1 7.5.4.2 7.5.5 7.5.5.1 7.5.5.2 7.5.6 7.6 7.6.1 7.6.2 7.6.3 7.6.4 7.6.5 7.7 7.7.1 7.7.2 7.7.3 7.8

Multiprocessor Communication Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Baud Rates of Serial Channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 New Baud Rate Generator for Serial Channel 1 . . . . . . . . . . . . . . . . . . . . . .64 Detailed Description of the Operating Modes . . . . . . . . . . . . . . . . . . . . . . . .66 Mode 0, Synchronous Mode (Serial Interface 0) . . . . . . . . . . . . . . . . . . . . . .66 Mode 1/Mode B, 8-Bit UART (Serial Interfaces 0 and 1) . . . . . . . . . . . . . . . .67 Mode 2, 9-Bit UART (Serial Interface 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Mode 3 / Mode A, 9-Bit UART (Serial Interfaces 0 and 1) . . . . . . . . . . . . . . .68 Timer 0 and Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 Function and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 lnitialization and Input Channel Selection . . . . . . . . . . . . . . . . . . . . . . . . . . .83 Start of Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 Reference Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 A/D Converter Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 The Compare/Capture Unit (CCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 Timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 The Compare Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 Compare Function in the CCU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 Compare Modes of the CCU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 Compare Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 Compare Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 Timer/Compare Register Configurations in the CCU . . . . . . . . . . . . . . . . . .107 Compare Function of Timer 2 with Registers CRC, CC1 to CC4 . . . . . . . . .108 Compare Function of Registers CM0 to CM7 . . . . . . . . . . . . . . . . . . . . . . .116 Capture Function in the CCU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 Arithmetic Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 Programming the MDU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 Multiplication/Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 Normalize and Shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 The Overflow Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 The Error Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136 Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139 Slow-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140 Fail Save Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141

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Table of Contents

Page

7.8.1 7.8.2 7.9 7.10 8 8.1 8.2 8.3 8.4 8.5 9 9.1 9.2 9.2.1 9.2.2 9.2.3 9.2.4 9.3

Programmable Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 Oscillator Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146 Oscillator and Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 System Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152 Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152 Priority Level Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162 How Interrupts are Handled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167 Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169 Introduction to the Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172 Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 Control Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 Instruction Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176

10 Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .256 10.1 Application Examples for the Compare Functions . . . . . . . . . . . . . . . . . . . .256 10.1.1 Generation of Two Different PWM Signals with "Additive Compare" using the "CCx Registers" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .256 10.1.2 Sine-Wave Generation with a CMx Registers/Compare Timer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258 10.2 Using an SAB 80C537 with External Program Memory and Additional External Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263 11 Device Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265

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Introduction

1

Introduction

The SAB 80C517/80C537 is a high-end microcontroller in the Siemens SAB 8051 8-bit microcontroller family. lt is based on the well-known industry standard 8051 architecture; a great number of enhancements and new peripheral features extend its capabilities to meet the extensive requirements of new applications. Nevertheless, the SAB 80C517 maintains compatibility within the Siemens SAB 8051 family; in fact, the SAB 80C517 is a superset of the Siemens SAB 80C515/ 80C535 microcontroller thus offering an easy upgrade path for SAB 80(C)515/80(C)535 users. In addition to all features of the SAB 80C515, there are several enhancements for higher performance. The SAB 80C517 has been expanded e.g. in its arithmetic characteristics, fail save mechanisms, analog signal processing facilities and timer capabilities. Listed below is a summary of the main features of the SAB 80C517/80C537:
q q q q q q q q q

q q

q q q q

8 Kbyte on-chip program memory (SAB 80C517 only) ROMIess version also available (SAB 80C537) Full compatibility with SAB 80C515/80C535 256 byte on-chip RAM 256 directly addressable bits 1 microsecond instruction cycle at 12-MHz oscillator frequency 64 of 111 instructions are executed in one instruction cycle External program and data memory expandable up to 64 Kbyte each 8-bit A/D converter 12 multiplexed inputs Programmable reference voltages External/internal start of conversion Two 16-bit timers/counters (8051 compatible) Powerful compare/capture unit (CCU) based on a 16-bit timer/counter and a high-speed 16-bit timer for fast compare functions One 16-bit reload/compare/capture register Four 16-bit compare/capture registers, one of which serves up to nine compare channels (concurrent compare) Eight fast 16-bit compare registers Arithmetic unit for division, multiplication, shift and normalize operations Eight datapointers instead of one for indirect addressing of program and external data memory Extended watchdog facilities 16-bit programmable watchdog timer Oscillator watchdog

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Introduction

q Nine ports

q q q

q q

Seven bidirectional 8-bit ports One 8-bit and one 4-bit input port for analog and digital input signals Two full-duplex serial interfaces with own baud rate generators Four priority level interrupt systems, 14 interrupt vectors Three power saving modes Slow-down mode Idle mode Power-down mode Siemens high-performance ACMOS technology P-LCC-84 package

The ROMIess version SAB 80C537 is identical with the SAB 80C517 except for the fact that it lacks the on-chip program memory; the SAB 80C537 is designed for applications with external program memory. In this manual, any reference made to the SAB 80C517 applies to both versions, the SAB 80C517 and the SAB 80C537, unless otherwise noted. Figure 1-1 shows the logic symbol of the SAB 80C517:

Figure 1-1 Logic Symbol Semiconductor Group 9

Fundamental Structure

2

Fundamental Structure

The SAB 80C517 is a totally 8051-compatible microcontroller while its peripheral performance has been increased significantly. lt includes the complete SAB 80(C)515, providing 100% upward compatibility. This means that all existing 80515 programs or user's program libraries can be used further on without restriction and may be easily extended to the new SAB 80C517. The SAB 80C517 is in the Siemens line of highly integrated microcontrollers for control applications. Some of the various on-chip peripherals have been added to support the 8-bit core in case of stringent real-time requirements. The 32-bit/16-bit arithmetic unit, the improved 4-level interrupt structure and the increased number of eight 16-bit datapointers are meant to give such a CPU support. But strict compatibility to the 8051 architecture is a principle of the SAB 80C517's design. Furthermore, the SAB 80C517 contains three additional 8-bit I/O ports and twelve general input lines. The additional serial channel is compatible to an 8051-UART and provided with an independent and freely programmable baud rate generator. An 8-bit resolution A/D-converter with software-adjustable reference voltages has been integrated to allow analog signal processing. As a counterpart to the A/D converter, the SAB 80C517 includes a powerful compare/capture unit with two 16-bit timers for all kinds of digital signal processing. The controller has been completed with well considered provisions for "fail-safe" reaction in critical applications and offers all CMOS features like low power consumption as well as an idle, power-down and slow-down mode. Figure 2-1 shows a block diagram of the SAB 80C517. Readers who are familiar with the SAB 8051 or SAB 80515 may concentrate on chapters 6 and 7 where the reset conditions and the new peripheral components are described. Chapter 8 (Interrupt System) has a special section for 80515 professionals where enhancements of the interrupt structure compared to the SAB 80515 are summarized. For readers, however, who are newcomers to the 8051 family of microcontrollers, the following section may give a general view of the basic characteristics of the SAB 80C517. The details of operation are described later in chapters 3 and 4.

Semiconductor Group

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Fundamental Structure

Figure 2-1 Functional Block Diagram Semiconductor Group 11

Fundamental Structure

Central Processing Unit The CPU is designed to operate on bits and bytes. The instructions, which consist of up to 3 bytes, are performed in one, two or four machine cycles. One machine cycle requires twelve oscillator cycles. The instruction set has extensive facilities for data transfer, logic and arithmetic instructions. The Boolean processor has its own full-featured and bit-based instructions within the instruction set. The SAB 80C517 uses five addressing modes: direct access, immediate, register, register indirect access, and for accessing the external data or program memory portions a base register plus indexregister indirect addressing. Memory Organization The SAB 80C517 has an internal ROM of 8 Kbyte. The program memory can externally be expanded up to 64 Kbyte (see Bus Expansion Control). The internal RAM consists of 256 bytes. Within this address space there are 128 bit-addressable locations and four register banks, each with 8 general purpose registers. In addition to the internal RAM there is a further 128-byte address space for the special function registers, which are described in sections to follow. Because of its Harvard architecture, the SAB 80C517 distinguishes between an external program memory portion (as mentioned above) and up to 64 Kbyte external data memory accessed by a set of special instructions. As an important improvement of the 8051 architecture, the SAB 80C517 contains eight datapointers (instead of one in the 8051) which speed up external data access. Bus Expansion Control The external bus interface of the SAB 80C517 consists of an 8-bit data bus (port 0), a 16-bit address bus (port 0 and port 2) and five control lines. The address latch enable signal (ALE) is used to demultiplex address and data of port 0. The program memory is accessed by the program store enable signal (PSEN) twice a machine cycle. A separate external access line (EA) is used to inform the controller while executing out of the lower 8 Kbyte of the program memory, whether to operate out of the internal or external program memory. The read or write strobe (RD, WR) is used for accessing the external data memory. Peripheral Control All on-chip peripheral components - I/O ports, serial interfaces, timers, compare/capture registers, the interrupt controller and the A/D converter - are handled and controlled by the so-called special function registers. These registers constitute the easy-to-handle interface with the peripherals. This peripheral control concept, as implemented in the SAB 8051, provides the high flexibility for further expansion as done in the SAB 80C517. Moreover some of the special function registers, like accumulator, Bregister, program status word (PSW), stack pointer (SP) and the data pointers (DPTR) are used by the CPU and maintain the machine status.

Semiconductor Group

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Central Processing Unit

3 3.1

Central Processing Unit General Description

The CPU (Central Processing Unit) of the SAB 80C517 consists of the instruction decoder, the arithmetic section and the program control section. Each program instruction is decoded by the instruction decoder. This unit generates the internal signals controlling the functions of the individual units within the CPU. They have an effect on the source and destination of data transfers, and control the ALU processing. The arithmetic section of the processor performs extensive data manipulation and is comprised of the arithmetic/logic unit (ALU), an A register, B register and PSW register. The ALU accepts 8-bit data words from one or two sources and generates an 8-bit result under the control of the instruction decoder. The ALU performs the arithmetic operations add, subtract, multiply, divide, increment, decrement, BCD-decimal-add-adjust and compare, and the logic operations AND, OR, Exclusive OR, complement and rotate (right, left or swap nibble (left four)). Also included is a Boolean processor performing the bit operations of set, clear, complement, jump-if-not-set, jump-if-set-andclear and move to/from carry. Between any addressable bit (or its complement) and the carry flag, it can perform the bit operations of logical AND or logical OR with the result returned to the carry flag. The A, B and PSW registers are described in section 4.4. The program control section controls the sequence in which the instructions stored in program memory are executed. The 16-bit program counter (PC) holds the address of the next instruction to be executed. The PC is manipulated by the control transfer instructions listed in the chapter "Instruction Set". The conditional branch logic enables internal and external events to the processor to cause a change in the program execution sequence.

Semiconductor Group

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Central Processing Unit

3.2

CPU Timing

A machine cycle consists of 6 states (12 oscillator periods). Each state is divided into a phase 1 half, during which the phase 1 clock is active, and a phase 2 half, during which the phase 2 clock is active. Thus, a machine cycle consists of 12 oscillator periods, numbered S1P1 (state 1, phase 1) through S6P2 (state 6, phase 2). Each state lasts for two oscillator periods. Typically, arithmetic and logical operations take place during phase 1 and internal register-to-register transfers take place during phase 2. The diagrams in figure 3-1 show the fetch/execute timing related to the internal states and phases. Since these internal clock signals are not user-accessible, the XTAL2 oscillator signals and the ALE (address latch enable) signal are shown for external reference. ALE is normally activated twice during each machine cycle: once during S1P2 and S2P1, and again during S4P2 and S5P1. Execution of a one-cycle instruction begins at S1P2, when the op-code is latched into the instruction register. lf it is a two-byte instruction, the second is read during S4 of the same machine cycle. lf it is a one-byte instruction, there is still a fetch at S4, but the byte read (which would be the next opcode) is ignored, and the program counter is not incremented. In any case, execution is completed at the end of S6P2. Figures 3-1 a) and b) show the timing of a 1-byte, 1-cycle instruction and for a 2-byte, 1-cycle instruction. Most SAB 80C517 instructions are executed in one cycle. MUL (multiply) and DIV (divide) are the only instructions that take more than two cycles to complete; they take four cycles. Normally two code bytes are fetched from the program memory during every machine cycle. The only exception to this is when a MOVX instruction is executed. MOVX is a one-byte, 2-cycle instruction that accesses external data memory. During a MOVX, the two fetches in the second cycle are skipped while the external data memory is being addressed and strobed. Figures 3-1 c) and d) show the timing for a normal 1-byte, 2-cycle instruction and for a MOVX instruction.

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Central Processing Unit

Figure 3-1 Fetch/Execute Sequence Semiconductor Group 15

Memory Organization

4

Memory Organization

The SAB 80C517 CPU manipulates operands in the following four address spaces: 4.1 up to 64 Kbyte of program memory up to 64 Kbyte of external data memory 256 bytes of internal data memory a 128-byte special function register area Program Memory

The program memory of the SAB 80C517 consists of an internal and an external memory portion (see figure 4-1). 8 Kbytes of program memory may reside on-chip (SAB 80C517 only), while the SAB 80C537 has no internal ROM. The program memory can be externally expanded up to 64 Kbyte. lf the EA pin is held high, the SAB 80C517 executes out of the internal program memory unless the address exceeds 1 FFFH. Locations 2000H through 0FFFFH are then fetched from the external program memory. lf the EA pin is held low, the SAB 80C517 fetches all instructions from the external program memory. Since the SAB 80C537 has no internal program memory, pin EA must be tied low when using this device. In either case, the 16-bit program counter is the addressing mechanism. Locations 03H through 93H in the program memory are used by interrupt service routines. 4.2 Data Memory

The data memory address space consists of an internal and an external memory portion. Internal Data Memory The internal data memory address space is divided into three physically separate and distinct blocks: the lower 128 byte of RAM, the upper RAM area, and the 128-byte special function register (SFR) area (see figure 4-2). While the latter SFR area and the upper RAM area share the same address locations, they must be accessed through different addressing modes. The map in figure 4-2 and the following table show the addressing modes used for the different RAM/SFR spaces.

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Memory Organization

Address Space Lower 128 bytes of RAM Upper 128 bytes of RAM Special function registers

Locations 00H to 7FH 80H to 0FFH 80H to 0FFH

Addressing Mode direct/indirect indirect direct

For details about the addressing modes see chapter 9.1.

Figure 4-1 Program Memory Address Space The lower 128 bytes of the internal RAM are again grouped in three address spaces (see figure 4-3): 1) 2) A general purpose register area occupies locations 0 trough 1FH (see also section 4.3). The next 16 bytes, locations 20H through 2FH, contain 128 directly addressable bits. (Programming information: These bits can be referred to in two ways, both of which are acceptable for the ASM51. One way is to refer to their addresses, i.e. 0 to 7FH. The other way is with reference to bytes 20H to 2FH. Thus bits 0 to 7 can also be referred to as bits 20.0-20.7, and bits 8-0FH are the same as 21.0-21.7 and so on. Each of the 16 bytes in this segment may also be addressed as a byte.) Locations 30H to 7FH can be used as a scratch pad area.

3)

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17

Memory Organization

Using the stack pointer (SP) - a special function register described in section 4.4 - the stack can be located anywhere in the whole internal data memory address space. The stack depth is limited only by the internal RAM available (256 byte maximum). However, pay attention to the fact that the stack is not overwritten by other data, and vice versa. External Data Memory Figure 4-2 and 4-3 contain memory maps which illustrate the internal/external data memory. To address data memory external to the chip, the "MOVX" instructions in combination with a 16-bit datapointer or an 8-bit general purpose register are used. Refer to chapter 9 (Instruction Set) or 5 (External Bus Interface) for detailed descriptions of these operations. A maximum of 64 Kbytes of external data memory can be accessed by instructions using a 16-bit address. The datapointer structure in the SAB 80C517 deserves special attention, since it consists of eight 16-bit registers which can be alternatively selected as datapointers. See section 4.4 and chapter 5 for further details.

Figure 4-2 Data Memory / SFR Address Spaces

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18

Memory Organization

Figure 4-3 Mapping of the Lower Portion of the Internal Data Memory Semiconductor Group 19

Memory Organization

4.3

General Purpose Registers

The lower 32 locations of the internal RAM are assigned to four banks with eight general purpose registers (GPRs) each. Only one of these banks may be enabled at a time. Two bits in the program status word, PSW.3 and PSW.4, select the active register bank (see description of the PSW). This allows fast context switching, which is useful when entering subroutines or interrupt service routines. ASM51 and the device SAB 80C517 default to register bank 0. The 8 general purpose registers of the selected register bank may be accessed by register addressing. With register addressing the instruction of code indicates which register is to be used. For indirect addressing R0 and R1 are used as pointer or index register to address internal or external memory (e.g. MOV @R0). Reset initializes the stack pointer to location 07H and increments it once to start from location 08H which is also the first register (R0) of register bank 1. Thus, if one is going to use more than one register bank, the SP should be initialized to a different location of the RAM which is not used for data storage. 4.4 Special Function Registers

The special function register (SFR) area has two important functions. Firstly, all CPU registers except the program counter and the four register banks reside here. The CPU registers are the arithmetic registers like A, B, PSW and pointers like SP, DPHx and DPLx. Secondly, a number of registers constitute the interface between the CPU and all on-chip peripherals. That means, all control and data transfers from and to the peripherals use this register interface exclusively. The special function register area is located in the address space above the internal RAM from addresses 80H to FFH. All 81 special function registers of the SAB 80C517 reside here. Sixteen SFRs, that are located on addresses dividable by eight, are bit-addressable, thus allowing 128 bit-addressable locations within the SFR area. Since the SFR area is memory mapped, access to the special function registers is as easy as with the internal RAM, and they may be processed with most instructions. In addition, if the special functions are not used, some of them may be used as general scratch pad registers. Note, however, all SFRs can be accessed by direct addressing only. The special function registers are listed in the following tables where they are organized in functional groups which refer to the functional blocks of the SAB 80C517. Block names and symbols are listed in alphabetical order. Bit addressable special function registers are marked with a dot in the fifth column. Special function registers with bits belonging to more then one functional block are marked with an asterisk at the symbol name.

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Memory Organization

Special Function Registers of the SAB 80C517 Block CPU Symbol ACC B DPH DPL DPSEL PSW SP ADCON0 ADCON1 ADDAT DAPR IEN0 CTCON 2) IEN1 IEN2 IP0 IP1 IRCON TCON 2) T2CON 2) ARCON MD0 MD1 MD2 MD3 MD4 MD5 Name Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Data Pointer Select Register Program Status Word Register Stack Pointer A/D Converter Control Register 0 A/D Converter Control Register 1 A/D Converter Data Register D/A Converter Program Register Interrupt Enable Register 0 Com. Timer Control Register Interrupt Enable Register 1 Interrupt Enable Register 2 Interrupt Priority Register 0 Interrupt Priority Register 1 Interrupt Request Control Register Timer Control Register Timer 2 Control Register Arithmetic Control Register Multiplication/Division Register 0 Multiplication/Division Register 1 Multiplication/Division Register 2 Multiplication/Division Register 3 Multiplication/Division Register 4 Multiplication/Division Register 5 Address 0E0H 1) 0F0H 1) 83H 82H 92H 0D0H 1) 81H 0D8H 1) 0DCH 0D9H 0DAH 0A8H 1) 0E1H 0B8H 1) 9AH 0A9H 0B9H 0C0H 1) 88H 1) 0C8H 1) 0EFH 0E9H 0EAH 0EBH 0ECH 0EDH 0EEH Contents after Reset 00H 00H 00H 00H XXXX.X000B 3) 00H 07H 00H XXXX.0000B 3) 00H 00H 00H 0XXX.0000B 3) 00H XXXX.00X0B 3) 00H XX00.0000B 3) 00H 00H 00H 0XXX.XXXXB 3) XXH 3) XXH 3) XXH 3) XXH 3) XXH 3) XXH 3)

A/DConverter

Interrupt System

MUL/DIV Unit

1) Bit-addressable special function registers. 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) X means that the value is indeterminate.

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Memory Organization

Special Function Registers of the SAB 80C517 (cont'd) Block Compare/ Capture Unit (CCU) Symbol CCEN CC4EN CCH1 CCH2 CCH3 CCH4 CCL1 CCL2 CCL3 CCL4 CMEN CMH0 CMH1 CMH2 CMH3 CMH4 CMH5 CMH6 CMH7 CML0 CML1 CML2 CML3 CML4 CML5 CML6 CML7 CMSEL CRCH CRCL CTCON CTRELH CTRELL TH2 TL2 T2CON Name Compare/Capture Enable Register Compare/Capture 4 Enable Register Compare/Capture Register 1, High Byte Compare/Capture Register 2, High Byte Compare/Capture Register 3, High Byte Compare/Capture Register 4, High Byte Compare/Capture Register 1, Low Byte Compare/Capture Register 2, Low Byte Compare/Capture Register 3, Low Byte Compare/Capture Register 4, Low Byte Compare Enable Register Compare Register 0, High Byte Compare Register 1, High Byte Compare Register 2, High Byte Compare Register 3, High Byte Compare Register 4, High Byte Compare Register 5, High Byte Compare Register 6, High Byte Compare Register 7, High Byte Compare Register 0, Low Byte Compare Register 1, Low Byte Compare Register 2, Low Byte Compare Register 3, Low Byte Compare Register 4, Low Byte Compare Register 5, Low Byte Compare Register 6, Low Byte Compare Register 7, Low Byte Compare Input Select Com./Rel./Capt. Register, High Byte Com./Rel./Capt. Register, Low Byte Com. Timer Control Register Com. Timer Rel. Register, High Byte Com. Timer Rel. Register, Low Byte Timer 2, High Byte Timer 2, Low Byte Timer 2 Control Register Address 0C1H 0C9H 0C3H 0C5H 0C7H 0CFH 0C2H 0C4H 0C6H 0CEH 0F6H 0D3H 0D5H 0D7H 0E3H 0E5H 0E7H 0F3H 0F5H 0D2H 0D4H 0D6H 0E2H 0E4H 0E6H 0F2H 0F4H 0F7H 0CBH 0CAH 0E1H 0DFH 0DEH 0CDH 0CCH 0C8H 1) Contents after Reset 00H X000.0000B 3) 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 0XXX.0000B 3) 00H 00H 00H 00H 00H

1) Bit-addressable special function registers. 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) X means that the value is indeterminate.

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Memory Organization

Special Function Registers of the SAB 80C517 (cont'd) Block Ports Symbol P0 P1 P2 P3 P4 P5 P6 P7 P8 PCON ADCON0 2) PCON 2) S0BUF S0CON S0RELL4) S0RELH4) S1BUF S1CON S1REL S1RELH4) TCON TH0 TH1 TL0 TL1 TMOD IEN0 2) IEN1 2) IP0 2) IP1 2) WDTREL Name Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7, Analog/Digital Input Port 8, Analog/Digital Input, 4Bit Power Control Register A/D Converter Control Register Power Control Register Serial Channel 0, Buffer Register Serial Channel 0 Control Register Serial Channel 0, Reload Reg., low byte Serial Channel 0, Reload Reg., high byte Serial Channel 1, Buffer Register Serial Channel 1, Control Register Serial Channel 1, Reload Register Serial Channel 1, Reload Reg., high byte Timer Control Register Timer 0, High Byte Timer 1, High Byte Timer 0, Low Byte Timer 1, Low Byte Timer Mode Register Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Priority Register 0 Interrupt Priority Register 1 Watchdog Timer Reload Register Address 80H 1) 90H 1) 0A0H 1) 0B0H 1) 0E8H 1) 0F8H 1) 0FAH 0DBH 0DDH 87H 0D8H 1) 87H 99H 98H1) 0AAH 0BAH 9CH 9BH 9DH OBBH 88H 1) 8CH 8DH 8AH 8BH 89H 0A8H 1) 0B8H 1) 0A9H 0B9H 86H Contents after Reset FFH FFH FFH FFH FFH FFH FFH XXH 3) XXH 3) 00H 00H 00H XXH 3) 00H 0D9H XXXX.XX11B 3) XXH 3) 0X00.0000B 3) 00H XXXX.XX11B 00H 00H 00H 00H 00H 00H 00H 00H 00H XX00.0000B3) 00H
3)

Pow. Sav.M Serial Channels

Timer0/ Timer1

Watchdog

1) Bit-addressable special function registers. 2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks. 3) X means that the value is indeterminate. 4) These registers are available in the CA step and later steps.

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Memory Organization

The following paragraphs give a general overview of the special function registers and refer to sections where a more detailed description can be found. Accumulator, SFR Address 0E0H ACC is the symbol for the accumulator register. The mnemonics for accumulator-specific instructions, however, refer to the accumulator simply as A. Program Status Word Register (PSW), SFR Address 0D0H 0D7H 0D0H CY 0D6H AC 0D5H F0 0D4H RS1 0D3H RS0 0D2H OV 0D1H F1 0D0H P PSW

The PSW register contains program status information. Bit CY AC F0 RS1 0 0 1 1 OV F1 P RS0 0 1 0 1 Function Carry Flag Auxiliary carry flag (for BCD operations) General purpose user flag 0 Register bank select control bits Bank 0 selected, data address 00H-07H Bank 1 selected, data address 08H-0FH Bank 2 selected, data address 10H-17H Bank 3 selected, data address 18H-1FH Overflow flag General purpose user flag 1 Parity flag. Set/cleared by hardware each instruction cycle to indicate an odd/even number of "one" bits in the accumulator, i.e. even parity.

B Register, SFR Address 0F0H The B register is used during multiply and divide and serves as both source and destination. For other instructions it can be treated as another scratch pad register.

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Memory Organization

Stack Pointer, SFR Address 081H The stack pointer (SP) register is 8 bits wide. lt is incremented before data is stored during PUSH and CALL executions and decremented after data is popped during a POP and RET (RETI) execution, i.e. it always points to the last valid stack byte. While the stack may reside anywhere in on-chip RAM, the stack pointer is initialized to 07H after a reset. This causes the stack to begin at location 08H above register bank zero. The SP can be read or written under software control. Datapointer, SFR Address 082H and 083H Datapointer Select Register, SFR Address 092H As a functional enhancement to standard 8051 controllers, the SAB 80C517 contains eight 16-bit registers which can be used as datapointers. To be compatible with 8051 architecture, the instruction set uses just one of these datapointers at a time. The selection of the actual datapointer is done in special function register DPSEL (datapointer select register, address 92H). Each 16-bit datapointer (DPTRx) register is a concatenation of registers DPHx (data pointer's high order byte) and DPLx (data pointer's low order byte). These pointers are used in register-indirect addressing to move program memory constants and external data memory variables, as well as to branch within the 64-Kbyte program memory address space. Since the datapointers are mainly used to access the external world, they are described in more detail in section 5.2. Ports 0 to 8 P0 to P8 are the SFR latches to port 0 to 8, respectively. The port SFRs 0 to 5 are bit-addressable. Ports 0 to 6 are 8-bit I/O ports (that is in total 56 I/O lines) which may be used as general purpose ports and which provide alternate output functions dedicated to the on-chip peripherals of the SAB 80C517. Port 7 (8-bit) and port 8 (4-bit) are general purpose input ports and have no internal latch. That means, these port lines are used for the 12 multiplexed input lines of the A/D converter but can also be used as digital inputs. P7/P8 are the associated SFRs when the digital value is to be read by the CPU. Both ports can be read only. You can find more about the ports in section 7.1 (parallel I/O).

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Memory Organization

Peripheral Control, Data and Status Registers Most of the special function registers are used as control, status and data registers to handle the on-chip peripherals. In the special function register table the register names are organized in groups and each of these groups refer to one peripheral unit. More details on how to program these registers are given in the descriptions of the following peripheral units:

Unit Ports Serial channels Timer 0/1 A/D converter Compare/capture unit Arithmetic unit (MUL/DIV unit) Power saving control unit Watchdog unit Interrupt system

Symbol ADC CCU MDU WDT/OWD

Section 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 8

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External Bus Interface

5

External Bus Interface

The SAB 80C517 allows for external memory expansion. To accomplish this, the external bus interface common to most 8051-based controllers is employed. To speed up external bus accesses, the SAB 80C517 contains eight 16-bit registers used as datapointers. This enhancement to the 8051 architecture is described in section 5.2. 5.1 Accessing External Memory

lt is possible to distinguish between accesses to external program memory and external data memory or other peripheral components respectively. This distinction is made by hardware: Accesses to external program memory use the signal PSEN (program store enable) as a read strobe. Accesses to external data memory use RD and WR to strobe the memory (alternate functions of P3.7 and P3.6, see section 7.1.). Port 0 and port 2 (with exceptions) are used to provide data and address signals. In this section only the port 0 and port 2 functions relevant to external memory accesses are described (for further details see chapter 7.1). Fetches from external program memory always use a 16-bit address. Accesses to external data memory can use either a 16-bit address (MOVX @DPTR) or an 8-bit address (MOVX @Ri). Role of P0 and P2 as Data/Address Bus When used for accessing external memory, port 0 provides the data byte time-multiplexed with the low byte of the address. In this state, port 0 is disconnected from its own port latch, and the address/ data signal drives both FETs in the port 0 output buffers. Thus, in this application, the port 0 pins are not open-drain outputs and do not require external pullup resistors. During any access to external memory, the CPU writes 0FFH to the port 0 latch (the special function register), thus obliterating whatever information the port 0 SFR may have been holding. Whenever a 16-bit address is used, the high byte of the address comes out on port 2, where it is held for the duration of the read or write cycle. During this time, the port 2 lines are disconnected from the port 2 latch (the special function register). Thus the port 2 latch does not have to contain 1s, and the contents of the port 2 SFR are not modified. lf an 8-bit address is used (MOVX @Ri), the contents of the port 2 SFR remain at the port 2 pins throughout the external memory cycle. This will facilitate paging. lt should be noted that, if a port 2 pin outputs an address bit that is a 1, strong pullups will be used for the entire read/write cycle and not only for two oscillator periods.

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External Bus Interface

Timing The timing of the external bus interface, in particular the relationship between the control signals ALE, PSEN, RD/WR and information on port 0 and port 2, is illustrated in figure 5-2 a) and b). Data memory: In a write cycle, the data byte to be written appears on port 0 just before WR is activated, and remains there until after WR is deactivated. In a read cycle, the incoming byte is accepted at port 0 before the read strobe is deactivated. Program memory: Signal PSEN functions as a read strobe. For further information see section 5.3. External Program Memory Access The external program memory is accessed under two conditions: whenever signal EA is active; or whenever the program counter (PC) contains a number that is larger than 01FFFH This requires the ROMIess version SAB 80C537 to have EA wired low to allow the lower 8 K program bytes to be fetched from external memory. When the CPU is executing out of external program memory, all 8 bits of port 2 are dedicated to an output function and may not be used for general-purpose I/O. The contents of the port 2 SFR however is not affected. During external program memory fetches port 2 lines output the high byte of the PC, and during accesses to external data memory they output either DPH or the port 2 SFR (depending on whether the external data memory access is a MOVX @DPTR or a MOVX @Ri). Since the SAB 80C537 has no internal program memory, accesses to program memory are always external, and port 2 is at all times dedicated to output the high-order address byte. This means that port 0 and port 2 of the SAB 80C537 can never be used as general-purpose I/O. This also applies to the SAB 80C517 when it is operated with only an external program memory.

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External Bus Interface

5.2

Eight Datapointers for Faster External Bus Access

The Importance of Additional Datapointers The standard 8051 architecture provides just one 16-bit pointer for indirect addressing of external devices (memories, peripherals, latches, etc.). Except for a 16-bit "move immediate" to this datapointer and an increment instruction, any other pointer handling is to be done byte by byte. For complex applications with numerous external peripherals or extended data storage capacity this turned out to be a "bottle neck" for the 8051's communication to the external world. Especially programming in high-level languages (PLM51, "C", PASCAL51) requires extended RAM capacity and at the same time a fast access to this additional RAM because of the reduced code efficiency of these languages. How the Eight Datapointers of the SAB 80C517 are Realized Simply adding more datapointers is not suitable because of the need to keep up 100% compatibility to the 8051 instruction set. This instruction set, however, allows the handling of only one single 16bit datapointer (DPTR, consisting of the two 8-bit SFRs DPH and DPL). To meet both of the above requirements (speed up external accesses, 100% compatibility to 8051 architecture) the SAB 80C517 contains a set of eight 16-bit registers from which the actual datapointer can be selected. This means that the user's program may keep up to eight 16-bit addresses resident in these registers, but only one register at a time is selected to be the datapointer. Thus the datapointer in turn is accessed (or selected) via indirect addressing. This indirect addressing is done through a special function register called DPSEL (data pointer select register). All instructions of the SAB 80C517 which handle the datapointer therefore affect only one of the eight pointers which is addressed by DPSEL at that very moment. Figure 5-1 illustrates the addressing mechanism: a 3-bit field in register DPSEL points to the currently used DPTRx. Any standard 8051 instruction (e.g. MOVX @DPTR, A - transfer a byte from accumulator to an external location addressed by DPTR) now uses this activated DPTRx.

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External Bus Interface

Figure 5-1 Accessing of External Data Memory via Multiple Datapointers Advantages of Multiple Datapointers Using the above addressing mechanism for external data memory results in less code and faster execution of external accesses. Whenever the contents of the datapointer must be altered between two or more 16-bit addresses, one single instruction, which selects a new datapointer, does this job. lf the program uses just one datapointer, then it has to save the old value (with two 8-bit instructions) and load the new address, byte by byte. This not only takes more time, it also requires additional space in the internal RAM. Application Example and Performance Analysis The following example shall demonstrate the involvement of multiple data pointers in a table transfer from the code memory to external data memory. Start address of ROM source table: Start address of table in external RAM: 1FFFH 2FA0H

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External Bus Interface

1) Using only One Datapointer (Code for an 8051) Initialization Routine Action Initialize shadow_variables with source_pointer Initialize shadow_variables with destination_pointer Code MOV LOW(SRC_PTR), #0FFH MOV HIGH(SRC_PTR), #1FH MOV LOW(DES_PTR), #0A0H MOV HIGH(DES_PTR), #2FH

Table Look-up Routine under Real Time Conditions Action Save old datapointer Load Source Pointer Increment and check for end of table (execution time not relevant for this consideration) Fetch source data byte from ROM table Save source_pointer and load destination_pointer Code PUSH DPL PUSH DPH MOV DPL, LOW(SRC_PTR) MOV DPH, HIGH(SRC_PTR) INC DPTR CJNE... ... MOVC A,@DPTR MOV LOW(SRC_PTR), DPL MOV HIGH(SRC_PTR), DPH MOV DPL, LOW(DES_PTR) MOV DPH, HIGH(DES_PTR) INC DPTR MOVX @DPTR, A MOV LOW(DES_PTR), DPL MOV HIGH(DES_PTR),DPH POP DPH POP DPL Machine Cycles 2 2 2 2 2 2 2 2 2 2 2 2 2 2 28

Increment destination_pointer (ex. time not relevant) Transfer byte to destination address Save destination_pointer Restore old datapointer Total execution time (machine cycles)

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External Bus Interface

2) Using Two Datapointers (Code for an SAB 80C517) Initialization Routine Action Initialize DPTR6 with source pointer Initialize DPTR7 with destination pointer Code MOV DPSEL, #06H MOV DPTR, #1FFFH MOV DPSEL, #07H MOV DPTR, #2FA0H

Table Look-up Routine under Real Time Conditions Action Save old source pointer Load source pointer Increment and check for end of table (execution time not relevant for this consideration) Fetch source data byte from ROM table Save source_pointer and load destination_pointer Transfer byte to destination address Save destination pointer and restore old datapointer Total execution time (machine cycles) Code PUSH DPSEL MOV DPSEL, #06H INC DPTR CJNE... ... MOVC A,@DPTR MOV DPSEL, #07H MOVX @DPTR, A POP DPSEL Machine Cycles 2 2 2 2 2 2 12

The above example shows that utilization of the SAB 80C517's multiple datapointers can make external bus accesses two times as fast as with a standard 8051 or 8051 derivative. Here, four data variables in the internal RAM and two additional stack bytes were spared, too. This means for some applications where all eight datapointers are employed that an SAB 80C517 program has up to 24 byte (16 variables and 8 stack bytes) of the internal RAM free for other use.

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External Bus Interface

5.3

PSEN, Program Store Enable

The read strobe for external fetches is PSEN. PSEN is not activated for internal fetches. When the CPU is accessing external program memory, PSEN is activated twice every cycle (except during a MOVX instruction) no matter whether or not the byte fetched is actually needed for the current instruction. When PSEN is activated its timing is not the same as for RD. A complete RD cycle, including activation and deactivation of ALE and RD, takes 12 osillator periods. A complete PSEN cycle, including activation and deactivation of ALE and PSEN takes 6 oscillator periods. The execution sequence for these two types of read cycles is shown in figure 5-2 a) and b). 5.4 ALE, Address Latch Enable

The main function of ALE is to provide a properly timed signal to latch the low byte of an address from P0 into an external latch during fetches from external memory. The address byte is valid at the negative transition of ALE. For that purpose, ALE is activated twice every machine cycle. This activation takes place even if the cycle involves no external fetch. The only time no ALE pulse comes out is during an access to external data memory when RD/WR signals are active. The first ALE of the second cycle of a MOVX instruction is missing (see figure 5-2 b) ). Consequently, in any system that does not use data memory, ALE is activated at a constant rate of 1/6 of the oscillator frequency and can be used for external clocking or timing purposes. 5.5 Overlapping External Data and Program Memory Spaces

In some applications it is desirable to execute a program from the same physical memory that is used for storing data. In the SAB 80C517, the external program and data memory spaces can be combined by AND-ing PSEN and RD. A positive logic AND of these two signals produces an active low read strobe that can be used for the combined physical memory. Since the PSEN cycle is faster than the RD cycle, the external memory needs to be fast enough to adapt to the PSEN cycle.

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External Bus Interface

Figure 5-2 a) and b) External Program Memory Execution Semiconductor Group 34

System Reset

6 6.1 6.1.1

System Reset Hardware Reset and Power-Up Reset Reset Function and Circuitries

The hardware reset function incorporated in the SAB 80C517 allows for an easy automatic start-up at a minimum of additional hardware and forces the controller to a predefined default state. The hardware reset function can also be used during normal operation in order to restart the device. This is particularly done when the power-down mode (see section 7.7) is to be terminated. Additionally to the hardware reset, which is applied externally to the SAB 80C517, there are two internal reset sources, the watchdog timer and the oscillator watchdog. They are described in detail in section 7.8 "Fail-Save Mechanisms". The chapter at hand only deals with the external hardware reset. The reset input is an active low input at pin 10 (RESET). An internal Schmitt trigger is used at the input for noise rejection. Since the reset is synchronized internally, the RESET pin must be held low for at least two machine cycles (24 oscillator periods) while the oscillator is running. With the oscillator running the internal reset is executed during the second machine cycle in which RESET is low and is repeated every cycle until RESET goes high again. During reset, pins ALE and PSEN are configured as inputs and should not be stimulated externally. (An external stimulation at these lines during reset activates several test modes which are reserved for test purposes. This in turn may cause unpredictable output operations at several port pins). A pullup resistor is internally connected to VCC to allow a power-up reset with an external capacitor only. An automatic reset can be obtained when VCC is applied by connecting the reset pin to VSS via a capacitor as shown in figure 6-1 a) and c). After VCC has been turned on, the capacitor must hold the voltage level at the reset pin for a specified time below the upper threshold of the Schmitt trigger to effect a complete reset.

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System Reset

The time required is the oscillator start-up time plus 2 machine cycles, which, under normal conditions, must be at least 10 - 20 ms for a crystal oscillator. This requirement is usually met using a capacitor of 4.7 to 10 microfarad. The same considerations apply if the reset signal is generated externally (figure 6-1 b). In each case it must be assured that the oscillator has started up properly and that at least two machine cycles have passed before the reset signal goes inactive.

Figure 6-1 Reset Circuitries A correct reset leaves the processor in a defined state. The program execution starts at location 0000H. The default values of the special function registers (SFR) to which they are forced during reset are listed in table 6-1. After reset is internally accomplished the port latches of ports 0 to 6 default in 0FFH. This leaves port 0 floating, since it is an open drain port when not used as data/ address bus. All other I/O port lines (ports 1 through 6) output a one (1). Ports 7 and 8, which are input-only ports, have no internal latch and therefore the contents of the special function registers P7 and P8 depend on the levels applied to ports 7 and 8. The contents of the internal RAM of the SAB 80C517 is not affected by a reset. After power-up the contents is undefined, while it remains unchanged during a reset it the power supply is not turned off.

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System Reset

Table 6-1 Register PC ACC ADCON0 ADCON1 ADDAT ARCON B CCL1-4 CCH1-4 CCEN CC4EN CMEN CML0-7 CMH0-7 CMSEL CRCL, CRCH CTCON CTRELL, CTRELH DAPR DPSEL DPTR0-7 Contents 0000H 00H 00H XXXX 0000B 00H 0XXX XXXXB 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 0XXX 0000B 00H 00H XXXX X000B 0000H Register IEN0, IEN1 IEN2 IP0 IP1 IRCON MD0-5 P0-P6 PCON PSW S0BUF, S1BUF S0CON S1CON S1REL SP TCON TL0, TH0 TL1, TH1 TL2, TH2 TMOD T2CON WDTREL Contents 00H XXXX 00X0B 00H XX00.0000B 00H XXH 0FFH 00H 00H 0XXH 00H 0X00 0000B 00H 07H 00H 00H 00H 00H 00H 00H 00H

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System Reset

6.1.2

Hardware Reset Timing

This section describes the timing of the hardware reset signal. The input pin RESET is sampled once during each machine cycle. This happens in state 5 phase 2. Thus, the external reset signal is synchronized to the internal CPU timing. When the reset is found active (low level at pin 10) the internal reset procedure is started. lt needs two complete machine cycles to put the complete device to its correct reset state, i.e. all special function registers contain their default values, the port latches contain 1's etc. Note that this reset procedure is not performed if there is no clock available at the device (This can be avoided using the oscillator watchdog, which provides an auxiliary clock for performing a correct reset without clock at the XTAL1 and XTAL2 pins. See section 7.8 for further details). The RESET signal must be active for at least two machine cycles; after this time the SAB 80C517 remains in its reset state as long as the signal is active. When the signal goes inactive this transition is recognized in the following state 5 phase 2 of the machine cycle. Then the processor starts its address output (when configured for external ROM) in the following state 5 phase 1. One phase later (state 5 phase 2) the first falling edge at pin ALE occurs. Figure 6-2 shows this timing for a configuration with EA = 0 (external program memory). Thus, between the release of the RESET signal and the first falling edge at ALE there is a time period of at least one machine cycle but less than two machine cycles.

Figure 6-2 CPU Timing after Reset

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System Reset

6.2

Reset Output Pin (RO)

As mentioned before the SAB 80C517 internally synchronizes an external reset signal at pin RESET in order to perform a reset procedure. Additionally, the SAB 80C517 provides several "failsave" mechanisms, e.g. watchdog timer and oscillator watchdog, which can internally generate a reset, too. Thus, it is often important to inform also the peripherals external to the chip that a reset is being performed and that the controller will soon start its program again. For that purpose, the SAB 80C517 has a pin dedicated to output the internal reset request. This reset output (RO) at pin 82 shows the internal (and already synchronized) reset signal requested by any of the three possible sources in the SAB 80C517: external hardware reset, watchdog timer reset, oscillator watchdog reset. The duration of the active low signal of the reset output depends on the source which requests it. In the case of the external hardware reset it is the synchronized external reset signal at pin RESET. In the case of a watchdog timer reset or oscillator watchdog reset the RESET OUT signal takes at least two machine cycles, which is the minimal duration for a reset request allowed. For details - how the reset requests are OR-ed together and how long they last - see also chapter 7.8 "Fail-Save Mechanisms".

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On-Chip Peripheral Components

7

On-Chip Peripheral Components

This chapter gives detailed information about all on-chip peripherals of the SAB 80C517 except for the integrated interrupt controller, which is described separately in chapter 8. Sections 7.1 and 7.2 are associated with the general parallel and serial I/O facilities while the remaining sections describe the miscellaneous functions such as the timers, A/D converter, compare/capture unit, multiplication/division unit, power saving modes, "fail-save" mechanisms, oscillator and clock circuitries and system clock output. 7.1 7.1.1 Parallel I/O Port Structures

Digital I/O The SAB 80C517 allows for digital I/O on 56 lines grouped into 7 bidirectional 8-bit ports. Each port bit consists of a latch, an output driver and an input buffer. Read and write accesses to the I/O ports P0 through P6 are performed via their corresponding special function registers P0 to P6. The output drivers of port 0 and 2 and the input buffers of port 0 are also used for accessing external memory. In this application, port 0 outputs the low byte of the external memory address, timemultiplexed with the byte being written or read. Port 2 outputs the high byte of the external memory address when the address is 16 bits wide. Otherwise, the port 2 pins continue emitting the P2 SFR contents (see also chapter 7.1.2 and chapter 5 for more details about the external bus interface). Digital/Analog Input Ports Ports 7 and 8 are available as input ports only and provide for two functions. When used as digital inputs, the corresponding SFR's P7 and P8 contain the digital value applied to port 7 and port 8 lines. When used for analog inputs the desired analog channel is selected by a three-bit field in SFR ADCON0 or a four-bit field in SFR ADCON1, as described in section 7.4. Of course, it makes no sense to output a value to these input-only ports by writing to the SFR's P7 or P8; this will have no effect. lf a digital value is to be read, the voltage levels are to be held within the input voltage specifications (VIL/VIH). Since P7 and P8 are not bit-addressable registers, all input lines of P7 or P8 are read at the same time by byte instructions.

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Nevertheless, it is possible to use ports 7 and 8 simultaneously for analog and digital input. However, care must be taken that all bits of P7 or P8 that have an undetermined value caused by their analog function are masked. In order to guarantee a high-quality A/D conversion, digital input lines of port 7 and port 8 should not toggle while a neighbouring port pin is executing an A/D conversion. This could produce crosstalk to the analog signal. Digital I/O Port Circuitry Figure 7-1 shows a functional diagram of a typical bit latch and I/O buffer, which is the core of each of the 7 I/O-ports. The bit latch (one bit in the port's SFR) is represented as a type-D flip-flop, which will clock in a value from the internal bus in response to a "write-to-latch" signal from the CPU. The Q output of the flip-flop is placed on the internal bus in response to a "r