Text preview for : ati_agp_r300_128mb_bga_dvii_vga_vo_rev_11_sch.pdf part of ATI ati agp r300 128mb bga dvii vga vo rev 11 sch ATI ati_agp_r300_128mb_bga_dvii_vga_vo_rev_11_sch.pdf
Back to : ati_agp_r300_128mb_bga_dv | Home
8 7 6 5 4 3 2 1
Title Schematic No. Date:
AGP R300 128MB BGA DVII VGA VO 105-942XX-30_11 Tuesday, October 01, 2002
Rev
REVISION HISTORY 11
D D
Sch PCB Date REVISION DESCRIPTION
Rev Rev
6 11 07/26/02 PRODUCTION RELEASE IIII
PCB silkscreen update only. No schematic changes.
7 12 08/19/02 PRODUCTION RELEASE IV
PCB silkscreen update only. No schematic changes.
1. Rev letter changed from 109-94200-11 to 109-94200-12
2. Remove CGND flood on L1 and L6 for MJ4.18
8 20 08/24/02 PRODUCTION RELEASE V
Sheet 1: Added traces to hijack circuit (sheet 24), AGP_TRDY#_R, and AGP_STOP#_R. Removed R12.
Sheet 6: Added R938 and R939 for selection of either 12V or 5V for Vtt regulator.
Sheet 7: Added R936 and R937 for selection of either 12V or 5V for MVDDC regulator.
C
Sheet 8: Added R934 and R935 for selection of either 12V or 5V for MVDDQ regulator. C
Sheet 24: Added Hijack Circuit to compensate for R300 cold boot issues.
9 30A 09/06/02 PROTOTYPE IV
Sheet 1: Added C1127.
Sheet 2: Added trace 8X_DET# to hijack circuit (sheet 24).
Sheet 6: Added C762 to Vc pin of Vtt regulator.
Sheet 7: Added C763 to 12V for MVDDC regulator. Added R954 and C764 to low gate of Q8B.
Sheet 8: Added C765 to Vc pin of MVDDQ regulator.
Sheet 24: Changed Hijack Circuit to compensate for R300 cold boot issues.
10 30B 09/18/02 PROTOTYPE V
PCB silkscreen update. Changed some component location in order to shorten the AGP_CLK lentgh after R946 resistor. No schematic changes.
11 30 09/26/02 PRODUCTION RELEASE VI
Sheet 6: Added R1552 between pins 2 and 3 of VDDC regulator.
B B
A A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Title Schematic No. Date:
AGP R300 128MB BGA DVII VGA VO 105-942XX-30_11 Tuesday, October 01, 2002
Rev
REVISION HISTORY 11
D D
Sch PCB Date REVISION DESCRIPTION
Rev Rev
0 00A PROTOTYPE I.i.
1 00B PROTOTYPE I.i.i.
BASED ON 109-94200-00A.
Sheet 2: Added C731 to input 2 of U2 to provide RC circuit for RESET.
Sheet 3: Added MOSFET Q19 to AGPREF pin of the ASIC to disconnect VREF from the motherboard during RESET time.
Replaced values for R39 (180R) and R40 (68R)
Sheet 4: Added C738 to TPVDD.
Sheet 6: Added header JU2 , capacitor C101, C739,C737 for external +5V power source, B18 connected to external +5V, added C732 to the output of the core regulator.
Added R910, R911.
Replaced values for Q3, Q4, L1, L2, R76, R89, R77, R90, C86, C92.
Removed diodes D4, D5.
Sheet 7: Added C734, and C736. Replaced internal +12V with external 12V. Replaced C120 with the bigger value 470uF. Removed C123, C124. Removed resistor R112 from U48-6 to 12V, that is not used. Added option to short one diode in D6
with R112. Added diode D24 to provide +12v power to MVDDC regulator when external power is not connected.
C C
Sheet 8: Regulator circuit for VDDC_CT replaced with one regulator. Changed source voltage for PVDD, and TPVDD regulators from +5V to +3.3V.
Sheet 9: Added resistors for selection between 4MX32 and 8MX32 memories.
Sheet 10: Added resistors for selection between 4MX32 and 8MX32 memories.
Sheet 11: Connected address lines MAA14 and MAB14 .
Sheet 12: Connected address lines MAC14 and MAD14 .
Sheet 13: Added MAA14, MAB14 as chip selects for Hynix 8MX32 memory.
Sheet 14: Added MAC14, MAD14 as chip selects for Hynix 8MX32 memory.
Sheet 15: Added circuit for detection of external power supply connection.
Sheet 16: Added fail-safe circuit for fan control, and connected internal thermistor from ASIC, VTERM1 is connected through the 0R resistor, R912, to have an option to use A11. Removed 3-pin
header.
Sheet 21: Added pull down resistor R877 on VSYNC_DAC2 for TVout filter enable.
Sheet 22: Added resistor R878 on connector J7. Removed MOSFET switch, and replaced with demultiplexer U96. Added also resistors to bridge the demultiplexer.
Sheet 23: Change GPIO used for Si168 reset to DVALID.
2 00C 06/28/2002 PROTOTYPE I.i.i.I
BASED ON 109-94200-00B.
B
Sheet 3: Replaced Q2 and Q1 with different type 2N7002E. B
Sheet 6: Added capacitors C740, C742 to the drains of the Q3A and Q5A. Added diode D25 to the second phase of the core regulator. Changed resistors values R94, and R98.
Sheet 7: Added capacitors C743, C744, C745, C746 and C747. Changed values for R114 and R117.
Sheet 8: Added capacitors C748. Changed values for R124, R131, R130, R126, R143, R139 and C133.
Sheet 9: Changed value for R138 to 75R.
Sheet10: Changed value for R774 to 75R.
Sheet19: Changed values for R800 and R803 to 0R. Replaced L11, L13, and L15 with R26, R27 and R28 respectively 0R. Added capacitors for HSYNC and VSYNC C749, and
C750.
Sheet20: Added capacitors at HSYNC and VSYNC, at C751, C752.
Sheet21: Added R29, R30, R31 and R32.
Sheet22: Added R925, R926, R927 to remove stubs when VO is used on HDH. Added R928, R929, and R930 to short DMUX (U96) when no VO is installed on the main board. Added R931, R932, and R933 to short DMUX (U96) when
no second VGA is installed.
Sheet23: Removed resistors R805 and R807.
PRODUCTION RELEASE
3 00 07/08/2002
Sheet 6: Replaced diode D25 with Scottkey diode. C91 replaced with 10MM footprint, better quality part.
A A
PRODUCTION RELEASE II
4 10 07/10/2002
Sheet 2: Removed series resistors R7 on AGP_SBSTB#, R9 on AGP_ADSTB1#, and R16 on AGP_ADSTB0#. Added instead pull-up 10K resistors to +VDDQ_BUS with the same designators.
PRODUCTION RELEASE III
5 01 07/19/2002 Adjusted trace on AGP to give clearance for fingers. Remove N625 declaration. Changed soldermask requirement to red.
8 7 6 5 4 3 2 1
5 4 3 2 1
MEMORY CHANNEL A B MEMORY CHANNEL C D
D D
DDR 4M X 32 (BGA)
SHT 13
DDR 4M X 32 (BGA)
SHT 14
MEMORY TERMINATIONS A B MEMORY TERMINATIONS C D
SHT 11 SHT 12
VGA1
PRIMARY CRT DB15
MA/B[14..0] MDA/B[63..0] QSA/B[7..0]CS0A/B# DQMA/B[0..7] MC/D[14..0]MDC/D[63..0]QSC/D[7..0] S0C/D# DQMC/D[0..7]
C
CASA/B#RASA/B# WEA/B# CKEA/BCLKA/B01 CLKA/B01# CASC/D# RASC/D# WEA/B# CKEC/D CLKC/D01CLKC/D01# LOGIC CONN
SHEET 19 SHT 19
MEM A B MEM C D
DAC1 R G B HSY VSY DDC1DATA DDC1CLK
C C
STRAPS
SHT 15
DVI-I1
T MDS TMDS_TX[C,2..0]N TMDS_TX[C,2..0]P HPD, DDC2CLK DDC2DATA
INTEG TMDS CONN
LOGIC SHT 18
BIOS ROMCS# ROM
SHT 17
TVO
R300 DVO DVO, VIP Host, VIP Data
External
FAN SHEET 3, 4, 5, 09, 10 VIP HDH
power
SHT 16
SHT 23
Y/R C/G COMP/B H2SYNC CRT2DDCDATA CRT2DDCCLK V2SYNC
B B
POWER VDDC VDDC18 VDD VTT VDDQ
PVDD TPVDD MPVDD
REGULATION A2VDD Vref
SHT 6,7,8 TVOUT TVout
D
DAC2 LOGIC
E SHT 22
CONN
M
GPIO U
SEL
AGP X SECONDARY
CRT LOGIC
SHT 22 SHT 19
AD31..0 CBE3..0 CPUCLK STOP# PAR REQ#
IR DY# GNT# TR DY# DEVSEL# RESET#
FRAME# CLK INTR SUSPEND# SERR#
AGPREF SBA[7..0] ST2..0 SB_STB SB_STB#
+3.3V +5V +12V AD_STB1 AD_STB1# AD_STB0 AD_STB0# RBF#
A A
AGP BUS REFERENCE RESTRICTION ATI Technologies Inc.
2X/4X/8X DESIGN NOTICE 1 Commerce Valley Drive East
Markham, Ontario
SHT 2 Canada, L3T 7X6
THESE SCHEMATICS ARE THESE SCHEMATICS CONTAIN (905) 882-2600
SUBJECT TO MODIFICATION INFORMATION W HICH IS PROPRIETARY
AND DESIGN IMPROVEMENTS. TO AND IS THE PROPERTY OF ATI, AND Title
PLEASE CONTACT ATI FIELD MAY NOT BE USED, REPRODUCED OR AGP R300 128MB BGA DVII VGA VO
APPLICATION ENGINEERING DISCLOSED IN ANY MANNER W ITHOUT Size Document Number Rev
BEFORE USING THE INFOR- EXPRESSED WRITTEN PERMISSION B 105-942XX-30_11 11
MATION CONTAINED HEREIN. FROM ATI. Date: Tuesday, October 01, 2002 Sheet 1 of 25
5 4 3 2 1
8 7 6 5 4 3 2 1
2X/4X/8X AGP BUS +12V_BUS +5V_BUS +3.3V_BUS
C1 C2 C3
GND_MPVSS GND_TPVSS GND_A2VSSN GND_AVSSQ GND_RSET 100uF 16V 100uF 16V 100uF 16V
GND_TVVSSN ALU
GND_AVSSN GND_PVSS GND_TXVSSR GND_A2VSSQ GND_R2SET
NOTE: THIS IS A DRAWING. THESE
AGP_C/BE#[3..0]
D GROUNDS MUST BE MANUALLY AGP_C/BE#[3..0] (3) D
AGP_AD[31..0]
CONNECTED TO THE GROUND PLANE AGP_AD[31..0] (3)
AGP_SBA[7..0]
AGP_SBA[7..0] (3)
AGP_ST[2..0]
AGP_ST[2..0] (3)
+12V_BUS
(3) AGP_INTR#
+3.3V_BUS TYDET R1 0R G ND_TY +3.3V_BUS
+VDDQ_BUS +5V_BUS
MAGP1 +VDDQ_BUS
A1 12V OVRCNT# B1
TYDET A2 B2
AGP_GC_8X_DET# TYPEDET# 5.0V
A3 GC_DET#/RESEVED 5.0V B3
R2 0R A4 B4
G ND_TY A5 USB- USB+
GND GND B5
A6 INTA# INTB# B6
AGP_RST# A7 B7 AGP_AGPCLK_R R3 0R
RST# CLK AGP_AGPCLK (3,24)
(3) AGP_GNT# A8 GNT# REQ# B8 AGP_REQ# (3)
A9 VCC3.3 VCC3.3 B9
AGP_ST1 A10 B10 AGP_ST0 C4
R4 0R ST1 ST0 AGP_ST2 10pF
(3) AGP_MB_8X_DET# A11 MB_DET#/RESERVED ST2 B11
R5 0R AGP_DBI_HI_R A12 B12 DNI
(3) AGP_DBI_HI DBI_HI/PIPE# RBF# AGP_RBF# (3)
A13 B13 AGP_DBI_LO_R R6 0R
(3) AGP_WBF# GND GND AGP_DBI_LO (3)
A14 WBF# DBI_LO/RESERVED B14
+VDDQ_BUS AGP_SBA1 A15 B15 AGP_SBA0
R7 8K2 SBA1 SBA0
A16 VCC3.3 VCC3.3 B16
AGP_SBA3 A17 B17 AGP_SBA2
AGP_SBSTB#_R SBA3 SBA2 AGP_SBSTB_R R8 0R
(3) AGP_SBSTB# A18 SB_STB# SB_STB B18 AGP_SBSTB (3)
C A19 B19 C
AGP_SBA5 GND GND AGP_SBA4
A20 SBA5 SBA4 B20
AGP_SBA7 A21 B21 AGP_SBA6
SBA7 SBA6
A22 KEY KEY B22
A23 KEY KEY B23
A24 KEY KEY B24
A25 KEY KEY B25
AGP_AD30 A26 B26 AGP_AD31
+VDDQ_BUS AGP_AD28 AD30 AD31 AGP_AD29
A27 AD28 AD29 B27
A28 VCC3.3 VCC3.3 B28
R9 8K2 AGP_AD26 A29 B29 AGP_AD27
AGP_AD24 AD26 AD27 AGP_AD25
A30 AD24 AD25 B30
AGP_ADSTB1#_R A31 B31 AGP_ADSTB1_R R10 0R
(3) AGP_ADSTB1# GND GND AGP_ADSTB1 (3)
A32 AD_STB1# AD_STB1 B32
AGP_C/BE#3 A33 B33 AGP_AD23
C/BE3# AD23
A34 VDDQ VDDQ B34
AGP_AD22 A35 B35 AGP_AD21
AGP_AD20 AD22 AD21 AGP_AD19
A36 AD20 AD19 B36
A37 GND GND B37
AGP_AD18 A38 B38 AGP_AD17
AGP_AD16 AD18 AD17 AGP_C/BE#2
A39 AD16 C/BE2# B39
A40 VDDQ VDDQ B40
(3) AGP_FRAME# A41 FRAME# IRDY# B41 AGP_IRDY# (3)
A42 KEY KEY B42
A43 KEY KEY B43
A44 KEY KEY B44
(24) AGP_TRDY#_R A45 KEY KEY B45
DNI R13 0R AGP_TRDY#_R A46 B46 AGP_DEVSEL#_R
(3,24) AGP_TRDY# DNI R15 TRDY# DEVSEL# AGP_DEVSEL#_R (3,24)
0R AGP_STOP#_R A47 B47
(3,24) AGP_STOP# STOP# VDDQ
(24) AGP_STOP#_R A48 PME# PERR# B48
B AGP_PAR_R A49 B49 B
GND GND
A50 PAR SERR# B50
AGP_AD15 A51 B51 AGP_C/BE#1
(3) AGP_PAR AD15 C/BE1#
A52 VDDQ VDDQ B52
AGP_AD13 A53 B53 AGP_AD14
+VDDQ_BUS AGP_AD11 AD13 AD14 AGP_AD12
A54 AD11 AD12 B54
A55 GND GND B55
R16 8K2 AGP_AD9 A56 B56 AGP_AD10
AGP_C/BE#0 AD9 AD10 AGP_AD8
A57 C/BE0# AD8 B57
AGP_ADSTB0#_R A58 B58 AGP_ADSTB0_R R17 0R
(3) AGP_ADSTB0# VDDQ VDDQ AGP_ADSTB0 (3)
A59 AD_STB0# AD_STB0 B59
AGP_AD6 A60 B60 AGP_AD7
AD6 AD7
A61 GND GND B61
AGP_AD4 A62 B62 AGP_AD5
AGP_AD2 AD4 AD5 AGP_AD3
A63 AD2 AD3 B63
A64 VDDQ VDDQ B64
AGP_AD0 A65 B65 AGP_AD1
AGP_VREFGC AD0 AD1
(3,24) AGP_VREFGC A66 VREFGC VREFCG B66 AGP_AGPREF (3)
UNIVERSAL AGP BUS
C1127
+5V_BUS 1.0uF
SYMBOL LEGEND
C5 R19
100nF 10K DNI DO NOT
INSTALL
14
A U2A A
1 AGP_RST# # ACTIVE
R22 100R 3 LOW
(3,9,10,23,24) AGP_RESET#
2 PW GOOD_VDDC (6) ATI Technologies Inc.
DIGITAL
74ACT08MTC DNI G ROUND 1 Commerce Valley Drive East
7
Markham, Ontario
DNI R854 R25 ANALOG Canada, L3T 7X6
180R 180R C731 G ROUND (905) 882-2600
100nF
Title AGP R300 128MB BGA DVII VGA VO
Size Document Number 105-942XX-30_11 Rev
B 11
Date: Tuesday, October 01, 2002 Sheet 2 of 25
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U42A
D PART 1 OF 8 D
AV39 Y36 AGP_AD0
(2,24) AGP_AGPCLK PCICLK AD0
A Y37 AGP_AD1
AD1 AGP_AD2
(2) AGP_GNT# AP38 AA36
AU39
GNT# G AD2
AA37 AGP_AD3
(2) AGP_REQ# REQ# AD3
AM39 P AB36 AGP_AD4
(2) AGP_RBF# RBF# AD4
AU37 AB37 AGP_AD5
(2) AGP_INTR# INTA# / AD5
AP35 AC36 AGP_AD6
(2,9,10,23,24) AGP_RESET# RST# AD6
(2) AGP_WBF# AM36 WBF# P AD7 AD37 AGP_AD7
AG35 AF37 AGP_AD8
PLACE
(2) AGP_FRAME#
AE35
FRAME# C AD8
AG36 AGP_AD9
(2,24) AGP_TRDY# TRDY# AD9
CLOSE TO
(2) AGP_IRDY# AH35 IRDY#
I AD10 AG37 AGP_AD10
THE ASIC AD35 AH36 AGP_AD11
(2,24) AGP_DEVSEL#_R DEVSEL# AD11
PIN AB35 AH37 AGP_AD12
(2,24) AGP_STOP# STOP# AD12
(2) AGP_PAR AA35 PAR
I AD13 AJ36 AGP_AD13
AGPREFCG AG34 AK37 AGP_AD14