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5 4 3 2 1
DDR3 PWR CHARGER
BOM MARK TPS51116 P40 ISL88731A P36
IV@: INT VGA
EV@: STUFF FOR EXT VGA THERMAL 3/5V SYS PWR
SP@: STUFF FOR UMA or VGA X'TAL PROTECTION P44 RT8206 P37
14.318MHz
Penryn 478 Thermal Sensor Fan Driver
DISCHARGER CPU CORE PWR
D
CLOCK GENERATOR uFCPGA (G780P81U) (G991) P42 ISL6266A P39
D
P3, P4 P3 P25
ICS:
SELGO: SLG8SP513VTR VGA CORE
+1.05V
P2 MAX8792 P41 UP6111A P38
FSB
667/800/1067 Mhz
EXT_LVDS
ATI-Park CRT
EXT_CRT P24
PCIE 16X
VRAM DDRIII EXT_HDMI SWITCH
DDRIII NB 512MB P18-P23 LVDS
P24
SO-DIMM 0 Dual Channel DDR3 CIRCUIT
Cantiga LVDS INT_LVDS
SO-DIMM 1 667/800 MHz
P16,P17 (GM45/ PM45/ GL40) HDMI
RGB INT_CRT P25 P25
C C
P5, P6, P7, P8, P9, P10, P11
HDMI switch
INT_HDMI
(PS8101T)
X4 DMI interface P25
HDD (SATA) *1
P26
Ext USB Port x 2
USB 0,2 P27 SATA0
PCI-Express PCIE-4 Mini Card
Int USB Port x 1 ODD (SATA) SATA1 WLAN
USB 6 P27
P26
SB P27
USB 2.0 ICH9M
Bluetooth USB1
USB3 P27
B
X'TAL PCIE-6 B
32.768KHz X'TAL
CCD Azalia P12,P13,P14,P15
25MHz
USB11 P24
Media
LPC Cardreader Giga-LAN
(AU6437)
BCM57780
USB2 P30 P30
Audio CODEC EC (WPC781)
(272) P28
P33
X'TAL
32.768KHz
Card Reader Transformer P31
Connector
P32
SPI ROM
P33
RJ45
A
Audio Amplifier MIC Jack Int. MIC P31 A
P29 P29
G1453L P28 Touch Pad K/B COON.
P26 P33
Int.
Speaker
P29 Size Document Number Rev
1A
Block Diagram
Date: Monday, July 12, 2010 Sheet 1 of 43
5 4 3 2 1
5 4 3 2 1
+3V
PBY160808T-301Y-N/2A/300ohm_6
+3V
L42
C544
*0.1u/10V_4
C434 C573 C574
Modfiy it 5/4
C545 C568 C551 C546 C435
+1.05V_VDD
PBY160808T-301Y-N/2A/300ohm_6
C437
L43 +1.05V
5/7 Modfiy
PM_STPPCI#
PM_STPCPU#
R313
R316
*2.2K_4
*2.2K_4
02
*0.1u/10V_4
C542 *10u/10V_8 10u/10V_8 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 *0.1u/10V_4 CLK_PCIE_SRC11# R322 10K_4
*10u/10V_8
D C569 U15 D
0.1u/10V_4 9 55 SATA_CLKREQ#_R R324 10K_4
C557 16 VDD_PCI IO_VOUT
0.1u/10V_4 23 VDD_48 7 SMBCK1
C550 VDD_CK_VDD_REF 4 VDD_PLL3 SCLK 6 SMBDT1 LAN_CLKREQ#_R R320 10K_4
0.1u/10V_4 VDD_REF SDA
C450 46
CK505 45 PM_STPPCI#
VDD_SRC SRC5/PCI_STOP# PM_STPPCI# 14
0.1u/10V_4 62 44 PM_STPCPU# PM_STPCPU# 14 To SB CLK_PCIE_SRC3 R349 10K_4
VDD_CPU SRC5#/CPU_STOP#
+1.05V_VDD
C541 19 61
27 VDD_96_IO CPU0 60
CLK_CPU_BCLK 3
To CPU CLK_MCH_OE#_C R317 10K_4
5/5 Add
VDD_PLL3_IO CPU0# CLK_CPU_BCLK# 3
10u/10V_8 33
52 VDD_SRC_IO_1 58
VDD_SRC_IO_3 CPU1 CLK_MCH_BCLK 5
43 57 To NB
VDD_SRC_IO_2 CPU1# CLK_MCH_BCLK# 5
56 For EMI
VDD_CPU_IO 54 T91
SRC8/ITP 53 T92
SRC8#/ITP# PCLK_591_R C571 *33p/50V_4
14 SATACLKREQ# R321 475/F_4 SATA_CLKREQ#_R 8 42
PCI0/CR#_A SRC10# CLK_PCIE_3GPLL# 6
41 To NB
SRC10 CLK_PCIE_3GPLL 6
31 LAN_CLKREQ# R325 475/F_4 LAN_CLKREQ#_R 10 CLKUSB_48 C581 *15p/50V_4
PCI1/CR#_B 40 CLK_MCH_OE#_C R319 475/F_4
SRC11/CR#_H CLK_MCH_OE# 6
R330 33_4 PCLK_DEBUG_R 11 39 CLK_PCIE_SRC11# R323 475/F_4 MINI_CLKREQ# 28
28 PCLK_DEBUG PCI2/TME SRC11#/CR#_G 14M_ICH C554 *33p/50V_4
T95 PCI_CLK_SIO 12 37
PCI3 SRC9 CLK_PCIE_MINI1 28
C 38 To Mini Card 1 (WLAN) C
SRC9# CLK_PCIE_MINI1# 28
R334 33_4 PCLK_591_R 13 PCLK_ICH_R C578 *33p/50V_4
35 PCLK_591 PCI4/SRC5_EN 51 CLK_PCIE_SRC7
SRC7/CR#_F T94
PCLK_ICH R346 33_4 PCLK_ICH_R 14 50 CLK_PCIE_SRC7#
13 PCLK_ICH PCIF5/ITP_EN SRC7#/CR#_E T93
SEL2 SEL1 SEL0 Frequence select
CG_XIN 3 48
XTAL_IN SRC6 CLK_PCIE_ICH 13
47 To ICH FSC FSB FSA CPU SRC PCI
SRC6# CLK_PCIE_ICH# 13
CG_XOUT 2
R345 22_4 XTAL_OUT 34
33 CLK_Card48 R337 22_4 FSA 17 SRC4 35
CLK_PCIE_LAN 31 1 0 1 100 100 33
14 CLKUSB_48 USB_48/FSA SRC4# CLK_PCIE_LAN# 31 To LAN
CPU_BSEL0 R338 2.2K_4 0 0 1 133 100 33 Default
CPU_BSEL1 64 31 CLK_PCIE_SRC3 R348 *EV@475/F_4 PEG_CLKREQ# 19 Modfiy it 5/4
CPU_BSEL2 R314 10K_4 FSB/TEST/MODE SRC3/CR#_C 32 CLK_PCIE_SRC3#
R318 33_4 FSC 5 SRC3#/CR#_D T97 0 1 1 166 100 33
14 14M_ICH REF0/FSC/TESTSEL
65 28 0 1 0 200 100 33
VSS_BODY SRC2/SATA CLK_PCIE_SATA 12
15 29 To ICH
VSS_PCI SRC2#/SATA# CLK_PCIE_SATA# 12
C549 18 0 0 0 266 100 33
33p/50V_4 CG_XIN 22 VSS_48 24 CLK_DREFSSCLK_R
26 VSS_IO SRC1/SE1 25 CLK_DREFSSCLK#_R
VSS_PLL3 SRC1#/SE2 To NB or VGA 1 0 0 333 100 33
2
Y2 59
CL=20p 30 VSS_CPU 20 CLK_DREFCLK_R
14.318MHZ 36 VSS_SRC1 SRC0/DOT96 21 CLK_DREFCLK#_R
1 1 0 400 100 33
VSS_SRC2 SRC0#/DOT96# To NB or VGA
C548 49 1 1 1 Reserved
1
33p/50V_4 CG_XOUT 1 VSS_SRC3 63
VSS_REF CKPWRGD/PWRDWN# CK_PWRGD 14
B SLG8SP513 B
SLG8SP513VTR ,ICS9LPRS365BKLFT +3V R329 10K_4 PCLK_DEBUG_R
5/5 modify R331 *10K_4
RN15
ICS9LRS3165BKLFT RTM875T-606
+3V R336 EV@10K_4 PCLK_591_R CLK_DREFCLK_R 3 4
(ALPRS365000) (AL000875000) CLK_DREFCLK 6
PULL HIGH PULL DOWN HIGH 27MHz CLK_DREFCLK#_R 1 2 IV@0_4P2R
LOW SRC CLK_DREFCLK# 6
R332 IV@10K_4 From GMCH RN14
PCI2/TME CLK_DREFSSCLK_R 3 4
internal PD CLK_DREFSSCLK 6
Pin 11 PCI2/TME NO OVERCLOCKING (default) NORMAL RUN
+3V R342 *10K_4 PCLK_ICH_R CLK_DREFSSCLK#_R 1 2 IV@0_4P2R
CLK_DREFSSCLK# 6
PCI-3/SRC5_EN PIN37/38 IS R343 10K_4 RN10
Pin 12 PCI-3 internal PD PIN37/38 IS SRC5 PCI_STOP/CPU_STOP (default) CLK_DREFCLK_R 1 2
CLK_PCIE_VGA 18
To NB CLK_DREFCLK#_R 3 4 EV@0_4P2R
PCI-4/27M_SEL PIN 17/18 CLK_PCIE_VGA# 18
Pin 13 PCI-4/27M_SEL internal PD PIN 17/18 IS 27MHz IS SRC/DOT (default) R347 0_4
From Deisceret RN9
3 CPU_BSEL0 MCH_BSEL0 6
CLK_DREFSSCLK_R 1 2
27M_NONSS 19
PCIF-5/ITP_EN R267 0_4 MCH_BSEL1 6 CLK_DREFSSCLK#_R 3 4
Pin 14 PCIF-5/ITP_EN internal PD PIN 46/47 IS CPUITP PIN 46/47 IS SRC8 (default) 3 CPU_BSEL1 *EV@33_4P2R
R315 0_4
3 CPU_BSEL2 MCH_BSEL2 6
5/18 Modify 5/22 modify
+3V +3V
:ICS9LRS3165BKLFT QCI:ALPRS365000
A
R258
:SLG8SP513VTR QCI:AL8SP513000 R259
A
4.7K_4 :RTM875N-606-VD-GRT QCI:AL000875000 4.7K_4
2
2
Q13 Q12
3 1 SMBDT1 3 1 SMBCK1
14,16,28 PDAT_SMB 14,16,28 PCLK_SMB
2N7002E 2N7002E
Size Document Number Rev
REV:B 6/12 REV:B 6/11 1A
CLOCK GENERATOR
Date: Monday, July 12, 2010 Sheet 2 of 43
5 4 3 2 1
5 4 3 2 1
5 H_A#[3..16]
H_A#3 J4
U17A
A[3]# ADS#
H1
H_ADS# 5
03
ADDR GROUP_0
H_A#4 L5 E2 H_D#[0..15] U17B H_D#[32..47]
A[4]# BNR# H_BNR# 5 5 H_D#[0..15] H_D#[32..47] 5
H_A#5 L4 G5 H_D#0 E22 Y22 H_D#32
A[5]# BPRI# H_BPRI# 5 D[0]# D[32]#
H_A#6 K5 H_D#1 F24 AB24 H_D#33
H_A#7 M3 A[6]# H5 H_D#2 E26 D[1]# D[33]# V24 H_D#34
A[7]# DEFER# H_DEFER# 5 D[2]# D[34]#
DATA GRP 0
H_A#8 N2 F21 H_D#3 G22 V26 H_D#35
H_DRDY# 5
DATA GRP 2
H_A#9 J1 A[8]# DRDY# E1 H_D#4 F23 D[3]# D[35]# V23 H_D#36
A[9]# DBSY# H_DBSY# 5 D[4]# D[36]#
H_A#10 N3 H_D#5 G25 T22 H_D#37
H_A#11 P5 A[10]# F1 H_D#6 E25 D[5]# D[37]# U25 H_D#38
A[11]# BR0# H_BREQ# 5 D[6]# D[38]#
H_A#12 P2 H_D#7 E23 U23 H_D#39
D A[12]# D[7]# D[39]# D
CONTROL
H_A#13 L2 D20 H_IERR# R245 56_4 +1.05V H_D#8 K24 Y25 H_D#40
H_A#14 P4 A[13]# IERR# B3 H_D#9 G24 D[8]# D[40]# W22 H_D#41
A[14]# INIT# H_INIT# 12 D[9]# D[41]#
H_A#15 P1 H_D#10 J24 Y23 H_D#42
H_A#16 R1 A[15]# H4 H_D#11 J23 D[10]# D[42]# W24 H_D#43
A[16]# LOCK# H_LOCK# 5 D[11]# D[43]#
M1 H_D#12 H22 W25 H_D#44
5 H_ADSTB#0 ADSTB[0]# D[12]# D[44]#
C1 H_D#13 F26 AA23 H_D#45
5 H_REQ#[0..4] RESET# H_CPURST# 5 D[13]# D[45]#
H_REQ#0 K3 F3 H_D#14 K22 AA24 H_D#46
REQ[0]# RS[0]# H_RS#0 5 D[14]# D[46]#
H_REQ#1 H2 F4 H_D#15 H23 AB25 H_D#47
REQ[1]# RS[1]# H_RS#1 5 D[15]# D[47]#
H_REQ#2 K2 G3 J26 Y26
REQ[2]# RS[2]# H_RS#2 5 5 H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 5
H_REQ#3 J3 G2 H26 AA26
REQ[3]# TRDY# H_TRDY# 5 5 H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 5
H_REQ#4 L1 H25 U22
REQ[4]# 5 H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 5
G6
5 H_A#[17..35] HIT# H_HIT# 5 H_D#[16..31] H_D#[48..63]
H_A#17 Y2 E4 H_D#[48..63] 5
A[17]# HITM# H_HITM# 5 5 H_D#[16..31]
H_A#18 U5 H_D#16 N22 AE24 H_D#48
H_A#19 R3 A[18]# AD4 XDP_BPM#0 H_D#17 K25 D[16]# D[48]# AD24 H_D#49
A[19]# BPM[0]# T56 D[17]# D[49]#
ADDR GROUP_1
H_A#20 W6