Text preview for : Quanta_ZRP.PDF part of Quanta Quanta ZRP Quanta Quanta_ZRP.PDF
Back to : Quanta_ZRP.PDF | Home
5 4 3 2 1
PCB STACK UP
LAYER 1 : TOP 15.6" ZRP Block Diagram 01
LAYER 2 : SVCC
LAYER 3 : IN1
LAYER 4 : IN2
D
LAYER 5 : GND Channel A D
DDRIII-SODIMM TRAVIS_L
LAYER 6 : BOT P12 1333 MHZ
DP0 ANX3111(1 Ch) LVDS PANEL
CPU P25
Memory Down P24
Channel B eDP
512MB*16
Trinity APU eDP PANEL
P25
(17,19,25W)
Max. 2G P13
DP1 HDMI CONN
35mm X 35mm P26
LAN (Charger) PCIE-1
24PIN FFC
GPP
FP2 813pin BGA
RJ45 Conn. AR8151L P32 Thames Pro VRAM DDR3-256M*4
10/100/1G
P2, 3, 4, 5
PCI-E x 8
GPU Thames XT/Mars VRAM DDR3-128M*8
Thames XT/Mars VRAM DDR3-256M*8
PCIE-0 GFX
X'TAL
25MHz
MINI CARD DP2 UMI Thames Pro/XT VRAM DDRIII
PEG0~8
WLAN+BT USB2-7
Mars P22, 23
Daugther board P30
UMI LINK 29mm X 29mm
DP1(x4) 2.5GT /s P14~21
C C
X'TAL
UMI(x4) 27.0MHz
SATA0
SATA - HDD
P29
14PIN FFC
SATA - ODD
SATA1
SATA VGA-DAC
CRT Con.
P29 P25
Daugther board
SATA2
SATA - SSD
P30
Card Reader 5 IN 1 USB2-5 USB 2.0 (Port0~13) AMD USB 3.0 (Port0~3) USB3-0
Card Reader Con. USB2.0 USB3.0 USB3.0 Con.
P27 (AU6435B53-GDL-GR) P27 Hudson M3 USB2-10 (charger) P31 Charger (BQ24707A)
USB2-6 LAN Daugther board
CCD
P25 FCH SYSTEM 5V/3V (RT8223MP
24.5mm X 24.5mm P35
USB2-0 12PIN FFC
USB Con. DDR 1.5V(TPS51216)
X'TAL
B
P31 25MHz
P8 B
P36
RTC
USB2-3 1.1V_DUAL(TPS51211)
USB Con. X'TAL
32.768KHz P8
P37
BATTERY
P8 +1.2V(TPS51211)/+2.5V
Daugther board P7, 8, 9, 10, 11
Azalia P38
IHDA
NVRAM
LPC +VDD_CORE 1+1 (ISL62771)
SPI P39
P9
LPC
+VGPU CORE(TPS51728)
P40
Audio Codec GPU_POWER/+1.8V_GPU
EC 885L
CX20584 P30 P34
P41
VDDCI(TPS51518)
P42
A INT. MIC HP/MIC Seaker FAN HALL Sensor LED K/B Touch Pad A
Discharge /Thermal
P30 P30 P30 P33 P25 P32 P33 P33
P43
Quanta Computer Inc.
PROJECT : ZRP
Size Document Number Rev
BLOCK DIAGRAM A1A
Date: Tuesday, May 29, 2012 Sheet 1 of 44
5 4 3 2 1
5 4 3 2 1
BOM Option
ITEM DESCRIPTION MARK
AC IN
Power Sequence
02
1 LVDS Panel Sku LVDS@ Hudson M3 SM BUS
3V/5VPCU
2 eDP Panel Sku eDP@
FCH SMBUS Pin NO. SMBUS Function Define
3 VGA Sku EV@ NBSWON#
D D
PCLK_SMB AD26
4 VGA Thames Sku EV_T@ DDR / RFID
DNBSWON# PDAT_SMB AD25
5 VGA Mars Sku EV_M@ (+3V)
S5_ON/S5
VGA Sku for Thames and Mars stuff SCLK1 T7
6 different value parts EV_SP@ not used
SDATA1 R7
RSMRST#
(+3V_S5)
7 GPU 128bit Sku EV_128@
SCLK2 H19
GPU 128bit Sku of Special part PCIE_WAKE# EC
8 value change EV_128SP@ SDATA2 G19
(+3V_S5)
SUSC
9 USB Charge Functions Sku CH@
SCLK3 G22
BATTERY
SUSB SDATA3 G21
10 No USB Charge Functions Sku NCH@
(+3VPCU)
SUSON
11 USB3.0 Re-Driver Sku RD@ SCL4 J19
not used
SDATA4 K19
MAINON
12 No USB3.0 Re-Driver Sku NRD@ (+3V_S5)
VR_ON
C C
13 Always connect functions Sku AC@
CPU_CORE
14 No Always connect functions Sku NAC@
KBC(EC) SM BUS
VRM_PWRGD
KBC SMBUS Pin NO. SMBUS Function Define
Special part value change or modify
15 for different BOM sku SP@ HWPG
MBCLK 110
Battery
ECPWROK MBDATA 111
(+3VPCU)
SB_PWRGD_IN
MBCLK_THRM 115
Thermal
MBDATA_THRM 116
CPU RESET
(+3VPCU)
CPU POWER OK
EC FCH Device I2C_Device(S)
B B
I2Ce_1(M) I2Cf_2(M) Charger Battery ALL/S5
I2Ce_2(M) APU ALL
I2Ce_3(M)
I2Cf_3(M) APU S5
I2Cf_1(M) S5
I2Cf_0(M) DDR WLAN/3G Image Sensor S0
EC will Conflict with FCH.
Do not mount
A A
Quanta Computer Inc.
PROJECT : ZRP
Size Document Number Rev
SYSTEM INFORMATION A1A
Date: Tuesday, May 29, 2012 Sheet 2 of 44
5 4 3 2 1
5 4 3 2 1
03
U25A
14 PEG_RXP0 AP1 AN1 PEG_TXP0_C C537 [email protected]/10V_4 PEG_TXP0 14
D P_GFX_RXP[0] P_GFX_TXP[0] PEG_TXN0_C C534 [email protected]/10V_4 D
14 PEG_RXN0 AP2 P_GFX_RXN[0] P_GFX_TXN[0] AN2 PEG_TXN0 14
14 PEG_RXP1 AM1 AM4 PEG_TXP1_C C540 [email protected]/10V_4 PEG_TXP1 14
P_GFX_RXP[1] P_GFX_TXP[1] PEG_TXN1_C C538 [email protected]/10V_4
14 PEG_RXN1 AM2 P_GFX_RXN[1] P_GFX_TXN[1] AM3 PEG_TXN1 14
14 PEG_RXP2 AK3 AK2 PEG_TXP2_C C541 [email protected]/10V_4 PEG_TXP2 14
P_GFX_RXP[2] P_GFX_TXP[2]
PEG X 8
PEG X 8
14 PEG_RXN2 AK4 AK1 PEG_TXN2_C C544 [email protected]/10V_4 PEG_TXN2 14
P_GFX_RXN[2] P_GFX_TXN[2] PEG_TXP3_C C550 [email protected]/10V_4
14 PEG_RXP3 AJ1 P_GFX_RXP[3] P_GFX_TXP[3] AH1 PEG_TXP3 14
14 PEG_RXN3 AJ2 AH2 PEG_TXN3_C C557 [email protected]/10V_4 PEG_TXN3 14
P_GFX_RXN[3] P_GFX_TXN[3] PEG_TXP4_C C555 [email protected]/10V_4
14 PEG_RXP4 AH4 P_GFX_RXP[4] P_GFX_TXP[4] AF3 PEG_TXP4 14
14 PEG_RXN4 AH3 AF4 PEG_TXN4_C C561 [email protected]/10V_4 PEG_TXN4 14
P_GFX_RXN[4] P_GFX_TXN[4] PEG_TXP5_C C563 [email protected]/10V_4
14 PEG_RXP5 AF2 P_GFX_RXP[5] P_GFX_TXP[5] AE1 PEG_TXP5 14
14 PEG_RXN5 AF1 AE2 PEG_TXN5_C C568 [email protected]/10V_4 PEG_TXN5 14
P_GFX_RXN[5] P_GFX_TXN[5] PEG_TXP6_C C569 [email protected]/10V_4
14 PEG_RXP6 AD1 P_GFX_RXP[6] P_GFX_TXP[6] AD4 PEG_TXP6 14
14 PEG_RXN6 AD2 AD3 PEG_TXN6_C C565 [email protected]/10V_4 PEG_TXN6 14
P_GFX_RXN[6] P_GFX_TXN[6] PEG_TXP7_C C575 [email protected]/10V_4
AB3 AB2
GRAPHICS
14 PEG_RXP7 P_GFX_RXP[7] P_GFX_TXP[7] PEG_TXP7 14
14 PEG_RXN7 AB4 AB1 PEG_TXN7_C C572 [email protected]/10V_4 PEG_TXN7 14
P_GFX_RXN[7] P_GFX_TXN[7]
AA1 P_GFX_RXP[8] P_GFX_TXP[8] Y1
FP2 only support PEG X 8 AA2 P_GFX_RXN[8] P_GFX_TXN[8] Y2 FP2 only support PEG X 8
Y4 P_GFX_RXP[9] P_GFX_TXP[9] V3
Y3 P_GFX_RXN[9] P_GFX_TXN[9] V4
V2 P_GFX_RXP[10] P_GFX_TXP[10] U1
V1 P_GFX_RXN[10] P_GFX_TXN[10] U2
T1 P_GFX_RXP[11] P_GFX_TXP[11] T4
C C
T2 P_GFX_RXN[11] P_GFX_TXN[11] T3
P3 P_GFX_RXP[12] P_GFX_TXP[12] P2
P4 P_GFX_RXN[12] P_GFX_TXN[12] P1
N1 P_GFX_RXP[13] P_GFX_TXP[13] M1
N2 P_GFX_RXN[13] P_GFX_TXN[13] M2
M4 P_GFX_RXP[14] P_GFX_TXP[14] K3
M3 P_GFX_RXN[14] P_GFX_TXN[14] K4
K2 P_GFX_RXP[15] P_GFX_TXP[15] J1
K1 P_GFX_RXN[15] P_GFX_TXN[15] J2
AH5 AG7 PCIE_TXP0_C C45 0.1u/10V_4 PCIE_TXP0_WLAN 28
28 PCIE_RXP0_WLAN P_GPP_RXP[0] P_GPP_TXP[0]
TO WLAN AH6 AG8 PCIE_TXN0_C C53 0.1u/10V_4 PCIE_TXN0_WLAN 28 TO WLAN
28 PCIE_RXN0_WLAN P_GPP_RXN[0] P_GPP_TXN[0]
AG5 AE7 PCIE_TXP1_C C74 0.1u/10V_4 PCIE_TXP1_LAN 32
32 PCIE_RXP1_LAN P_GPP_RXP[1] P_GPP_TXP[1]
TO LAN AG6 AE8 PCIE_TXN1_C C67 0.1u/10V_4 PCIE_TXN1_LAN 32 TO LAN
32 PCIE_RXN1_LAN P_GPP_RXN[1] P_GPP_TXN[1]
AE6 P_GPP_RXP[2] P_GPP_TXP[2] AD7
AE5 P_GPP_RXN[2] P_GPP_TXN[2] AD8
AD6 P_GPP_RXP[3] P_GPP_TXP[3] AB6
AD5 AB5
GPP
P_GPP_RXN[3] P_GPP_TXN[3]
8 UMI_RXP0 AM10 AN6 UMI_TXP0_C C508 0.1u/10V_4 UMI_TXP0 8
P_UMI_RXP[0] P_UMI_TXP[0] UMI_TXN0_C C509 0.1u/10V_4
8 UMI_RXN0 AN10 P_UMI_RXN[0] P_UMI_TXN[0] AM6 UMI_TXN0 8
8 UMI_RXP1 AN8 AP6 UMI_TXP1_C C507 0.1u/10V_4 UMI_TXP1 8
B P_UMI_RXP[1] P_UMI_TXP[1] UMI_TXN1_C C506 0.1u/10V_4 B
8 UMI_RXN1 AM8 P_UMI_RXN[1] P_UMI_TXN[1] AR6 UMI_TXN1 8
8 UMI_RXP2 AP8 AP4 UMI_TXP2_C C511 0.1u/10V_4 UMI_TXP2 8
P_UMI_RXP[2] P_UMI_TXP[2] UMI_TXN2_C C510 0.1u/10V_4
8 UMI_RXN2 AR8 P_UMI_RXN[2] P_UMI_TXN[2] AR4 UMI_TXN2 8
8 UMI_RXP3 AR7 AP3 UMI_TXP3_C C513 0.1u/10V_4 UMI_TXP3 8
P_UMI_RXP[3] P_UMI_TXP[3] UMI_TXN3_C C512 0.1u/10V_4
8 UMI_RXN3 AP7 P_UMI_RXN[3] P_UMI_TXN[3] AR3 UMI_TXN3 8
UMI
+1.2V_VDDP R372 196/F_6 P_ZVDDP AR11 AP11 P_ZVSS R371 196/F_6
P_ZVDDP P_ZVSS
SP@TRINITY APU_BGA813
SP : A10(AJ04655UT01)
A8(AJ04555VT01)
A6(AJ04455UT01)
A4(AJ04355UT00)
A A
Quanta Computer Inc.
PROJECT : ZRP
Size Document Number Rev
A1A
APU 1/4(PCIE/UMI/GPP/HDT)
Date: Friday, June 01, 2012 Sheet 3 of 44
5 4 3 2 1
5 4 3 2 1
Soldermask openings for all bottom side vias/TPs under FS1
04
M_B_DQ[0..63] 13
U25B M_A_DQ[0..63] 12 13 M_B_A[15:0] U25C
12 M_A_A[15:0] M_A_A0 M_A_DQ0 M_B_A0 M_B_DQ0
AA28 MA_ADD[0] MA_DATA[0] F15 Y33 MB_ADD[0] MB_DATA[0] C16
M_A_A1 R29 E15 M_A_DQ1 M_B_A1 R32 B17 M_B_DQ1
M_A_A2 MA_ADD[1] MA_DATA[1] M_A_DQ2 M_B_A2 MB_ADD[1] MB_DATA[1] M_B_DQ2
T30 MA_ADD[2] MA_DATA[2] H19 T31 MB_ADD[2] MB_DATA[2] B20
M_A_A3 R28 F19 M_A_DQ3 M_B_A3 P33 C20 M_B_DQ3
M_A_A4 MA_ADD[3] MA_DATA[3] M_A_DQ4 M_B_A4 MB_ADD[3] MB_DATA[3] M_B_DQ4
R26 MA_ADD[4] MA_DATA[4] E14 P32 MB_ADD[4] MB_DATA[4] A16
D M_A_A5 P26 H15 M_A_DQ5 M_B_A5 P31 B16 M_B_DQ5 D
M_A_A6 MA_ADD[5] MA_DATA[5] M_A_DQ6 M_B_A6 MB_ADD[5] MB_DATA[5] M_B_DQ6
P27 MA_ADD[6] MA_DATA[6] E17 N32 MB_ADD[6] MB_DATA[6] B19
M_A_A7 P30 D18 M_A_DQ7 M_B_A7 M33 A20 M_B_DQ7
M_A_A8 MA_ADD[7] MA_DATA[7] M_B_A8 MB_ADD[7] MB_DATA[7]
P29 MA_ADD[8] M32 MB_ADD[8]
M_A_A9 M28 G20 M_A_DQ8 M_B_A9 L32 B22 M_B_DQ8
M_A_A10 MA_ADD[9] MA_DATA[8] M_A_DQ9 M_B_A10 MB_ADD[9] MB_DATA[8] M_B_DQ9
AB26 MA_ADD[10] MA_DATA[9] E20 AB31 MB_ADD[10] MB_DATA[9] C22
M_A_A11 M26 H23 M_A_DQ10 M_B_A11 M31 A26 M_B_DQ10
M_A_A12 MA_ADD[11] MA_DATA[10] M_A_DQ11 M_B_A12 MB_ADD[11] MB_DATA[10] M_B_DQ11
M29 MA_ADD[12] MA_DATA[11] G23 K32 MB_ADD[12] MB_DATA[11] B26
M_A_A13 AE27 E19 M_A_DQ12 M_B_A13 AF33 B21 M_B_DQ12
M_A_A14 MA_ADD[13] MA_DATA[12] M_A_DQ13 M_B_A14 MB_ADD[13] MB_DATA[12] M_B_DQ13
L26 MA_ADD[14] MA_DATA[13] H20 K33 MB_ADD[14] MB_DATA[13] A22
M_A_A15 L27 E22 M_A_DQ14 M_B_A15 J32 C24 M_B_DQ14
12 M_A_BS#[2..0] MA_ADD[15] MA_DATA[14] 13 M_B_BS#[2..0] MB_ADD[15] MB_DATA[14]
D22 M_A_DQ15 B25 M_B_DQ15
M_A_BS#0 MA_DATA[15] M_B_BS#0 MB_DATA[15]
AB27 MA_BANK[0] AB33 MB_BANK[0]
M_A_BS#1 AA29 H25 M_A_DQ16 M_B_BS#1 AA32 A28 M_B_DQ16
M_A_BS#2 MA_BANK[1] MA_DATA[16] M_A_DQ17 M_B_BS#2 MB_BANK[1] MB_DATA[16] M_B_DQ17
12 M_A_DM[7..0] M30 MA_BANK[2] MA_DATA[17] F25 K31 MB_BANK[2] MB_DATA[17] B28
D28 M_A_DQ18 B31 M_B_DQ18
M_A_DM0 MA_DATA[18] M_A_DQ19 MB_DATA[18] M_B_DQ19
D16 MA_DM[0] MA_DATA[19] D29 13 M_B_DM0 C18 MB_DM[0] MB_DATA[19] A32
M_A_DM1 D20 E23 M_A_DQ20 B23 C26 M_B_DQ20
MA_DM[1] MA_DATA[20] 13 M_B_DM1 MB_DM[1] MB_DATA[20]
M_A_DM2 E25 D24 M_A_DQ21 C28 B27 M_B_DQ21
MA_DM[2] MA_DATA[21] 13 M_B_DM2 MB_DM[2] MB_DATA[21]
M_A_DM3 F30 D26 M_A_DQ22 D31 A30 M_B_DQ22
MA_DM[3] MA_DATA[22] 13 M_B_DM3 MB_DM[3] MB_DATA[22]
M_A_DM4 AK29 D27 M_A_DQ23 AM31 C30 M_B_DQ23
MA_DM[4] MA_DATA[23] 13 M_B_DM4 MB_DM[4] MB_DATA[23]
M_A_DM5 AL25 AN30
M_A_DM6 MA_DM[5] M_A_DQ24 13 M_B_DM5 MB_DM[5] M_B_DQ24
AM20 MA_DM[6] MA_DATA[24] G28 13 M_B_DM6 AR24 MB_DM[6] MB_DATA[24] B33
M_A_DM7 AM16 G29 M_A_DQ25 AN18 C32 M_B_DQ25
MA_DM[7] MA_DATA[25] 13 M_B_DM7 MB_DM[7] MB_DATA[25]
H27 M_A_DQ26 F33 M_B_DQ26
MA_DATA[26] M_A_DQ27 MB_DATA[26] M_B_DQ27
12 M_A_DQSP0 G17 MA_DQS_H[0] MA_DATA[27] J29 13 M_B_DQSP0 B18 MB_DQS_H[0] MB_DATA[27] F32
H17 E28 M_A_DQ28 A18 B32 M_B_DQ28
12 M_A_DQSN0 MA_DQS_L[0] MA_DATA[28] M_A_DQ29 13 M_B_DQSN0 MB_DQS_L[0] MB_DATA[28] M_B_DQ29
12 M_A_DQSP1 F22 MA_DQS_H[1] MA_DATA[29] F27 13 M_B_DQSP1 B24 MB_DQS_H[1] MB_DATA[29] C31
G22 H29 M_A_DQ30 A24 E32 M_B_DQ30
12 M_A_DQSN1 MA_DQS_L[1] MA_DATA[30] 13 M_B_DQSN1 MB_DQS_L[1] MB_DATA[30]
E26 H28 M_A_DQ31 B30 F31 M_B_DQ31
C 12 M_A_DQSP2 MA_DQS_H[2] MA_DATA[31] 13 M_B_DQSP2 MB_DQS_H[2] MB_DATA[31] C
12 M_A_DQSN2 F26 MA_DQS_L[2] 13 M_B_DQSN2 B29 MB_DQS_L[2]
12 M_A_DQSP3 H30 MA_DQS_H[3] MA_DATA[32] AH29 M_A_DQ32 13 M_B_DQSP3 D32 MB_DQS_H[3] MB_DATA[32] AK32 M_B_DQ32
12 M_A_DQSN3 G30 MA_DQS_L[3] MA_DATA[33] AJ30 M_A_DQ33 13 M_B_DQSN3 D33 MB_DQS_L[3] MB_DATA[33] AL32 M_B_DQ33
12 M_A_DQSP4 AL29 MA_DQS_H[4] MA_DATA[34] AM28 M_A_DQ34 13 M_B_DQSP4 AM32 MB_DQS_H[4] MB_DATA[34] AP32 M_B_DQ34
12 M_A_DQSN4 AL30 MA_DQS_L[4] MA_DATA[35] AM27 M_A_DQ35 13 M_B_DQSN4 AM33 MB_DQS_L[4] MB_DATA[35] AN31 M_B_DQ35
12 M_A_DQSP5 AH25 MA_DQS_H[5] MA_DATA[36] AH27 M_A_DQ36 13 M_B_DQSP5 AN28 MB_DQS_H[5] MB_DATA[36] AK31 M_B_DQ36
12 M_A_DQSN5 AJ25 MA_DQS_L[5] MA_DATA[37] AH28 M_A_DQ37 13 M_B_DQSN5 AP29 MB_DQS_L[5] MB_DATA[37] AK33 M_B_DQ37
12 M_A_DQSP6 AK20 MA_DQS_H[6] MA_DATA[38] AJ29 M_A_DQ38 13 M_B_DQSP6 AP23 MB_DQS_H[6] MB_DATA[38] AN32 M_B_DQ38