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Intel Calpella INTEL DISCRETE SYSTEM DIAGRAM 01
BlOCK DIAGRAM FAN & THERMAL POWER
REGULATOR CPU VR
A A
+1.5V_SUS/+0.75V_DDR_VTT
SYSTEM CLOCK DC/DC
RESET CIRCUIT SLG8SP585VTR +1.05V_PCH +3VPCU/+5VPCU/
POWER (QFN-32)
+1.05V_VTT
BATT
CHARGER
AC/BATT RUN POWER SW
CONNECTOR
+3V_S5/+5V_S5 CPU AMD
CRT CRT
+3V_SUS/+5V_SUS
+5V_RUN/+3V_RUN/+1.8V_RUN PCI-E x16 PARK-LP
Arrandale 35W LVDS
23mm X 23mm LVDS
DDR3-SODIMM1
CHA
37.5mm X 37.5mm TDP 8W
Dual Channel DDR3
B
1066 1.5V ( S3 ) B
DDR3-SODIMM2 ( rPGA 989 )
DDR3 800MHz
CHB
VRAM
64Mx16x2,32bit
DMI X 4
USB conn x 3
SATA-ODD SATA
PCH Card Reader SD MS CARD
USB2.0 x 3 RTS5159
SATA-HDD SATA
82801IBM
USB2.0
(HM55)
PCIEx1 LAN
C 27mm X 25mm Realtek 10/100/ LAN RTL8103EL
C
IHDA
PCIEx2
MINI-CARD
AUDIO/AMP WLAN
ALC269
SPI
LPC
Audio Audio FLASH
SPK conn Jacks 2Mbyts
EC
ITE8502
18X8
Keyboard
D D
SPI PS/2
FLASH Touchpad Quanta Computer Inc.
2Mbyts
PROJECT : FH1A
Size Document Number Rev
1A
BLOCK DIAGRAM
Date: Tuesday, December 15, 2009 Sheet 1 of 45
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1 2 3 4 5 6 7 8
Table of Contents
PAGE
01
02
Schematic Block Diagram
Front Page
DESCRIPTION
Power Sequence 02
03 Clock Generator
ACIN
04-07 Arrandale
+3VPCU/+5VPCU
A 08-13 Ibex Peak-M A
NBSWON#
14-15 DDRIII SO-DIMM(204P)
16 LCD/CCD CONN
17 CRT CONN RVCC_ON
T1
18 Card Reader (RTS5159)
ICH_RSMRST#
19 LAN RTL8103EL/RJ45 T2
DNBSWON#
20 HDD/ODD/HOLE
21 USB/BLUE TOOTH
22 MINI-Card (WLAN)/ XDP
SUSB#,SUSC#,SUSD#
23 KB/TOUCH PAD/LED
24 CODEC (ALC269)
SUSON
25 EC_ ITE8502
26 FAN/SW CON MAINON
27 +5V/+3V (RT8206B)
28 +1.05V/ +1.8V (RT8204C) DGPU_PWR_EN
T3
B 29 CPU Core ( ADP3212) B
T5
30 +1.05V_VTT (VT358) MAINON2
31 DDR3 (RT8207)
+1.5VSUS/+3VSUS/+5VSUS
32 DISCHARGE/3VS5/5VS5/LAN
33 CHARGER (ISL88731) +1.5V_RUN/+1.8V_RUN
/+3V_RUN/+5V_RUN
34 Clock Distribution
35 Power Tree +VGPU_CORE/+3V_GPU/+1.8V_GPU
/+1.5V_GPU/+1.0V_GPU
36 SMBUS Address
37 PARK-S3_PCIE_Interface +1.05V_PCH/+1.05V_VTT
/+0.75V_DDR_VTT
38 PARK-S3_Main
39 PARK-S3_GND/LVDS/Straps
HWPG
40 PARK-S3_Power_and_NC
41 PARK-S3_MEM_Interface VRON
42 PARK_VRAM (DDR3 BGA96)
43 +VGACORE (RT8208/1.8V) +VCC_CORE
C C
44 +1.5V_VGA/+1.0V_VGA
VR_PWRGD_CLKEN# 3ms~20ms
IMVP_PWRGD
T4
MPWROK
H_VTTPWRGD
DRAMPWROK
VCCPPWRGOOD
PLTRST#
CPU_RST#
D D
T1: RVCCON TO RSMRST# = 30ms (spec:mini 10ms)
T2: RSMRST# TO-DNBSWON = 110ms (spec:mini 100ms)
T3: MAINON2 TO VRON = 110ms (spec:mini 99ms)
T4: VRON TO MPWROK = 10ms (HWPG NEED TO BE HIGH at that time) Quanta Computer Inc.
Note: IMVP_CLK_EN# (inverted) assertion to SYS_PWROK/PCH_PWROK assertion. PROJECT : FH1A
SPEC:3ms~20ms Size Document Number Rev
1A
T5: MAINON to MAINON2 =500us
Frontpage
Date: Tuesday, December 15, 2009 Sheet 2 of 45
1 2 3 4 5 6 7 8
5 4 3 2 1
D D
+3V_RUN
L11 BLM21PG600SN1D 40mil +3.3V_CLK_VDD 1 VDD_USB CLK_BUF_BCLK_P
5 VDD_LCD CPU-0 23 CLK_BUF_BCLK_P 10
17 22 CLK_BUF_BCLK_N
VDD_SRC CPU-0# CLK_BUF_BCLK_N 10
C185 C149 C148 C179 C181 C165 +VDDIO_CLK 24 VDD_CPU
29 20
10U/10V_8 0.1U/16V_4 0.1U/16V_4 0.1U/16V_4 0.1U/16V_4 0.1U/16V_4 15
18
VDD_REF
VDD_SRC_IO CK505 CPU-1
CPU-1# 19
VDD_CPU_IO
9 VSS_SATA
QFN32 DOT96T_LPR 3 CLK_BUF_DREFCLKP
CLK_BUF_DREFCLKP 10
0.1uF near the every power pin. 2 4 CLK_BUF_DREFCLKN
VSS_USB DOT96C_LPR CLK_BUF_DREFCLKN 10
8 VSS_LCD
12 13 CLK_BUF_PCIE_3GPLLP
VSS_SRC SRC-2 CLK_BUF_PCIE_3GPLLP 10
21 14 CLK_BUF_PCIE_3GPLLN
VSS_CPU SRC-2# CLK_BUF_PCIE_3GPLLN 10
26 VSS_REF
10 CLK_BUF_DREFSSCLKP
SRC-1/SATA CLK_BUF_DREFSSCLKP 10
+3V_RUN 11 CLK_BUF_DREFSSCLKN
SRC-1#/SATA# CLK_BUF_DREFSSCLKN 10
C C
R139 10K/J_4 16 6 27MHZ_NONSS R343 33_4 EVGA-XTALI
CPU_STOP# 27MHz_nonSS EVGA-XTALI 38
CK_PWRGD_R 25 7 27MHZ_SS R416 *33_4 CLK_27M_SS
CK_PWRGD/PD#_3.3 27MHz_SS CLK_27M_SS 38
CLK_PCH_14M R125 33/J_4 CPU_SEL 30
10 CLK_PCH_14M REF_0/CPU_SEL
A-01
Place the 33 ohm XTAL_OUT 27
XTAL_IN XOUT
resistors close to the CK 505 28 XIN
10,14,15 CGDAT_SMB 31 SDATA GND 33
10,14,15 CGCLK_SMB 32 SCLK
SLG8SP585VTR U6
C145 C146 Realtek: 0.1uFx3pcs, 22uFx1pcs
*33P/50V_4 *33P/50V_4 IDT: 0.1uFx2pcs, 10uFx1pcs
+3V_RUN
+VDDIO_CLK
Y1 L12 BLM21PG600SN1D
XTAL_IN 1 2 XTAL_OUT R142 *0/J_8 40mil
805
B 14.318MHZ +1.05V_PCH B
2
C186 C167 C180
C166 C173 10U/10V_8 0.1U/16V_4 0.1U/16V_4
+3V_S5 33P/50V_4 33P/50V_4 R144 0/J_8
1
HP: 10u x2pcs
C182 SLG,IDT: +1.05V Place each 0.1uF cap as close as
0.1U/16V_4
Realtek: +3.3V possible to each VDD IO pin. Place
the 10uF caps on the VDD_IO plane.
5
29 VR_PWRGD_CLKEN# 2 4 R140 0/J_4 CK_PWRGD_R
+VDDIO_CLK:
U8
TC7SZ04FU(T5L,F,T)
SLG date sheet (V0.2) P15: Min 1.05V,Max3.465V.
3
Realtek date sheet(V1.2) P11: Min 1.05V,Max 3.3V.
IDT date sheet(V0.7) P10: Min 0.9975V,Max 3.465V.
+3V_RUN
CPU_SEL:
2
PIN 30 CPU_0 CPU_1 SLG date sheet (V0.2) P15:
R126
*4.7K/J_4
High Voltage: Min 0.7V, Max 1.5V.
A 0(default) 133MHz 133MHz Low Voltage: Min Vss-0.3V, Max 0.35V. A
Realtek date sheet(V1.2) P11:
1
CPU_SEL
High Voltage: Min 0.7V, Max 1.5V.
1(0.7V-1.5V) 100MHz 100MHz
2
Low Voltage: Min Vss-0.3V, Max 0.35V.
R127 C152 IDT date sheet(V0.7) P10: Quanta Computer Inc.
4.7K/J_4 *10P/50V_4 High Voltage: Min 0.7V, Max 1.5V.
Low Voltage: Min Vss-0.3V, Max 0.35V. PROJECT : FH1A
1
EMI Capacitor Size Document Number Rev
1A
Clock Generator
Date: Tuesday, December 15, 2009 Sheet 3 of 45
5 4 3 2 1
5 4 3 2 1
04
U19A
PEG_ICOMPI B26 PEG_ICOMPI R251 49.9/F_4 U19B
A26 H_COMP3 AT23
PEG_ICOMPO COMP3
8 DMI_TXN0 A24 DMI_RX#[0] PEG_RCOMPO B27 BCLK A16 CLK_CPU_BCLKP 11
MISC
C23 A25 R254 750/F_4 H_COMP2 AT24 B16
D 8
8
DMI_TXN1
DMI_TXN2 B22
DMI_RX#[1]
DMI_RX#[2]
PEG_RBIAS A-03 COMP2 BCLK# CLK_CPU_BCLKN 11 D
CLOCKS
A21 K35 PEG_RXN15 PEG_RXN15 37 H_COMP1 G16 AR30 CLK_BCLK_ITPP 22
8 DMI_TXN3 DMI_RX#[3] PEG_RX#[0] COMP1 BCLK_ITP
J34 PEG_RXN14 PEG_RXN14 37 AT30 CLK_BCLK_ITPN 22
PEG_RX#[1] PEG_RXN13 H_COMP0 BCLK_ITP#
8 DMI_TXP0 B24 DMI_RX[0] PEG_RX#[2] J33 PEG_RXN13 37 AT26 COMP0
D23 G35 PEG_RXN12 PEG_RXN12 37 E16 CLK_PCIE_3GPLLP 10
8 DMI_TXP1 DMI_RX[1] PEG_RX#[3] PEG_CLK
DMI
B23 G32 PEG_RXN11 PEG_RXN11 37 D16 CLK_PCIE_3GPLLN 10
8 DMI_TXP2 DMI_RX[2] PEG_RX#[4] PEG_CLK#
A22 F34 PEG_RXN10 PEG_RXN10 37 T13 TP_SKT0CC# AH24
8 DMI_TXP3 DMI_RX[3] PEG_RX#[5] SKTOCC#
F31 PEG_RXN9 A18
8 DMI_RXN0 D24 DMI_TX#[0]
PEG_RX#[6]
PEG_RX#[7] D35 PEG_RXN8
PEG_RXN9 37
PEG_RXN8 37
DPLL_REF_SSCLK
DPLL_REF_SSCLK# A17 A-04
G24 E33 PEG_RXN7 PEG_RXN7 37 H_CATERR# AK14 Disable UMA
8 DMI_RXN1 DMI_TX#[1] PEG_RX#[8] CATERR#
THERMAL
F23 C33 PEG_RXN6 PEG_RXN6 37
8 DMI_RXN2 DMI_TX#[2] PEG_RX#[9]
H23 D32 PEG_RXN5 PEG_RXN5 37
8 DMI_RXN3 DMI_TX#[3] PEG_RX#[10]
B32 PEG_RXN4 PEG_RXN4 37 F6 DDR3_DRAMRST#_C for S3 power reduction
PEG_RX#[11] PEG_RXN3 R271 0/J_4 H_PECI_ISO AT15 SM_DRAMRST#
8 DMI_RXP0 D25 DMI_TX[0] PEG_RX#[12] C31 PEG_RXN3 37 11 H_PECI PECI
F24 B28 PEG_RXN2 PEG_RXN2 37 AL1 SM_RCOMP_0
8 DMI_RXP1 DMI_TX[1] PEG_RX#[13] SM_RCOMP[0]
E23 B30 PEG_RXN1 PEG_RXN1 37 AM1 SM_RCOMP_1
8 DMI_RXP2 DMI_TX[2] PEG_RX#[14] SM_RCOMP[1]
G23 A31 PEG_RXN0 PEG_RXN0 37 AN1 SM_RCOMP_2 +1.05V_VTT
8 DMI_RXP3 DMI_TX[3] PEG_RX#[15] SM_RCOMP[2]
29 H_PROCHOT#_D H_PROCHOT#_D AN26
PEG_RXP15 PROCHOT# R91 2
PEG_RX[0] J35 PEG_RXP15 37 PM_EXT_TS#[0] AN15 1 10K/J_4
DDR3
MISC
H34 PEG_RXP14 PEG_RXP14 37 AP15 R86 2 1 10K/J_4
PEG_RX[1] PEG_RXP13 PM_EXT_TS#[1] R103 0/J_4
H33
A-02 E22 FDI_TX#[0]
PEG_RX[2]
PEG_RX[3] F35 PEG_RXP12
PEG_RXP13 37
PEG_RXP12 37 11 H_THERM H_THERM R105 0/J_4 AK15 THERMTRIP#
R83 0/J_4
PM_EXTTS#0 14
PM_EXTTS#1 15
D21 G33 PEG_RXP11 PEG_RXP11 37
FDI_TX#[1] PEG_RX[4] PEG_RXP10
D19 FDI_TX#[2] PEG_RX[5] E34 PEG_RXP10 37
D18 F32 PEG_RXP9 PEG_RXP9 37 AT28 XDP_PRDY# 22
FDI_TX#[3] PEG_RX[6] PEG_RXP8 PRDY# XDP_PREQ# R80
G21 FDI_TX#[4] PEG_RX[7] D34 PEG_RXP8 37 PREQ# AP27 XDP_PREQ# 22
PCI EXPRESS -- GRAPHICS
E19 F33 PEG_RXP7 PEG_RXP7 37 *12.4K/F_4
FDI_TX#[5] PEG_RX[8] PEG_RXP6 XDP_TCLK
F21 FDI_TX#[6] PEG_RX[9] B33 PEG_RXP6 37 TCK AN28 XDP_TCLK 22
Intel(R) FDI
G18 D31 PEG_RXP5 PEG_RXP5 37 22 H_CPURST# H_CPURST# AP26 AP28 XDP_TMS XDP_TMS 22
FDI_TX#[7] PEG_RX[10] RESET_OBS# TMS
PWR MANAGEMENT
PWR MANAGEMENT
A32 PEG_RXP4 PEG_RXP4 37 AT27 XDP_TRST# XDP_TRST# 22
PEG_RX[11] TRST#
JTAG & BPM
C30 PEG_RXP3 PEG_RXP3 37 T41
PEG_RX[12] PEG_RXP2 XDP_TDI_R T38
D22 FDI_TX[0] PEG_RX[13] A28 PEG_RXP2 37 8 PM_SYNC AL15 PM_SYNC TDI AT29
C21 B29 PEG_RXP1 PEG_RXP1 37 AR27 XDP_TDO_R T39
FDI_TX[1] PEG_RX[14] PEG_RXP0 TDO XDP_TDI_M
D20 FDI_TX[2] PEG_RX[15] A30 PEG_RXP0 37