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AG1(Alviso) Block Diagram 2005/11/01
A B C D E




Mobile CPU G792 Project Code:91.4G301.001
CLK GEN.
4
19
PCB:05223-01 4

IDT CV125 Dothan
3 4, 5
RGB CRT CPU DC/DC
HOST BUS 400MHz ISL6218CV-T
CONN 14 34
DDR II 400MHz
LCD INPUTS OUTPUTS
400 MHz Intel 910GML
11,12 LVDS XGA VCC_CORE
13 DCBATOUT
0.844~1.3V
DDR II 400MHz
27A

400 MHz 6,7,8,9,10
11,12 SYSTEM DC/DC
DMI I/F 100MHz TPS51120 35
3 3

INPUTS OUTPUTS
Line In27 ACLINK ENE DCBATOUT 3D3V_S5
Codec PCI BUS CB1410 PWR SW 5V_S5
PCMCIA APL5912-LAC
ALC655 CP2211
Int. 26 25 APL5308-25AC 36
24,25
ONE SLOT
MIC In 27 25 INPUTS OUTPUTS
5V_S5 1D5V_S0
3D3V_S0 2D5V_S0

Mini-PCI SYSTEM DC/DC

Line Out OP AMP ICH6-M 802.11A/B/G 28
ISL6227 37
27
G1421B 27 LAN
10/100
INPUTS OUTPUTS

RTL8110CL
TXFM RJ4523 5V_S5
23 DCBATOUT
22, 23 3D3V_S3
2 2

INT.SPKR MODEM TPS51100DGQ 37
27
MDC Card DDR_VREF
5V_S5
21 DDR_VREF_S3

LPC BUS
CHARGER
ISL6255
15,16,17,18 38
Xbus BIOS ROM
PATA




INPUTS OUTPUTS
KBC 4M BITS
ENE KB3910 PM39LV040-70JCE


PCB Layer Stackup USB 29 31 DCBATOUT
BT+
16.8V 3A
4 PORT
L1: Signal 1 HDD CD ROM 21
20 20
L2:VCC
1 1
L3: Signal 2 MINI USB 21
Touch INT_KB Wistron Corporation
L4: Signal 3 Blue-tooth Pad 30 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
30
L5: GND Title

L6: Signal 4 BLOCK DIAGRAM
Size Document Number Rev
Custom
AG1(Alviso) 01
Date: Tuesday, November 01, 2005 Sheet 1 of 40

A B C D E
A B C D E
Alviso Strapping Signals ICH6-M Integrated Pull-up
and Configuration page 7 and Pull-down Resistors ICH6-M EDS 14308 0.8V1
Pin Name Strap Description Configuration
ACZ_BIT_CLK, DPRSLP#, EE_DIN,
CFG[2:0] FSB Frequency Select 000 = Reserved
001 = FSB533 EE_DOUT, GNT[5]#/GPO[17],
010 = FSB800 ICH6 internal 20K pull-ups
011-111 = Reversed GNT[6]#/GPO[16], LDRQ[1]/GPI[41],
4 CFG[3:4] Reversed LAD[3:0]#/FB[3:0]#, LDRQ[0],
4
CFG5 DMI x2 Select 0 = DMI x2 PME#, PWRBTN#, TP[3]
1 = DMI x4 (Default)
0 = DDR II
CFG6 DDR I / DDR II 1 = DDR I LAN_RXD[2:0] ICH6 internal 10K pull-ups
CFG7 CPU Strap 0 = Prescott
1 = Dothan (Default) ACZ_RST#, ACZ_SDIN[2:0], ACZ_SYNC, ICH6 internal 20K pull-downs
CFG[8:11] Reversed ACZ_SDOUT,ACZ_BITCLK, DPRSLPVR,
CFG[12:13] XOR/ALL Z test 00 = Reserved SPKR, EE_CS,
straps 01 = XOR mode enabled
10 = All Z mode enabled
11 = Normal Operation USB[7:0][P,N] ICH6 internal 15K pull-downs
(Default)
CFG[14:15] Reversed DD[7], SDDREQ ICH6 internal 11.5K pull-downs
CFG16 FSB Dynamic ODT 0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled LAN_CLK ICH6 internal 100K pull-downs
(Default)
CFG17 Reversed
CFG18 CPU core VCC 0 = 1.05V (Default)
Select 1 = 1.5V
3 CFG19 CPU VTT Select 0 = 1.05V (Default)
ICH6-M IDE Integrated Series 3
1 = 1.2V
CFG20 Reversed
PCI Routing Termination Resistors
DD[15:0], DIOW#, DIOR#, DREQ,
SDVOCRTL SDVO Present 0 = No SDVO device present IDSEL IRQ REQ/GNT approximately 33 ohm
_DATA (Default) DDACK#, IORDY, DA[2:0], DCS1#,
1= SDVO device present
1410 25 B.F.G 0 DCS3#, IDEIRQ
NOTE: All strap signals are sampled with respect to the leading
edge of the Alviso GMCH PWORK In signal.
MiniPCI 21 F 1
LAN 23 E 2




2 2





1 1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.

Title

Memo
Size Document Number Rev
A3
AG1(Alviso) 01
Date: Tuesday, November 01, 2005 Sheet 2 of 40
3D3V_S0 3D3V_S0 3D3V_S0

1 R122 2 3D3V_APWR_S0 1 R105 2 3D3V_48MPWR_S0 1 R110 2 3D3V_CLKGEN_S0
0R0603-PAD 2R3J-2-GP 0R0603-PAD




1




1




1




1




1




1




1




1
C295 C103 C108 C109 C122 C105




SCD1U16V2ZY-2GP




SCD1U16V2ZY-2GP




SCD1U16V2ZY-2GP




SCD1U16V2ZY-2GP




SCD1U16V2ZY-2GP
SC10U10V5ZY-1GP
C124 C104




SC4D7U10V5ZY-3GP




SC4D7U6D3V3KX-GP
2




2




2




2




2




2




2




2
IN EN OUT
(3D3V_S0) (6218_PGOOD) (VTT_PWRGD#)
H L H
X H Hi - Z

AG1-910-01
3D3V_CLKGEN_S0 R251 1 U28
28 PCLK_MINI 2 33R2J-2-GP 2nd

AG1-A-SA PCLK_MINI_1 56 17 DREFSSCLK1 2 3 DREFSSCLK 7
PCLK_LAN_1 PCI0 LVDS DREFSSCLK#1
22 PCLK_LAN 8 1 3 PCI1 LVDS# 18 1 4 DREFSSCLK# 7
1

1




7 2 PCLK_PCM_1 4
24 PCLK_PCM PCLK_KBC_1 PCI2 RN62
AG1-910-01 29 PCLK_KBC 6 3 5 PCI3 SRC1 19
R98 R369 5 4 H/L: 100/96MHz 20 SRN33J-5-GP-U
1KR2J-1-GP 1KR2J-1-GP 16 CLK_ICHPCI SS_SEL SRC1#
9 PCIF1/SEL100/96# SRC2 22
RN7 ITP_EN 8 23
2

2




FS_A SRN33J-4-GP PCIF0/ITP_EN SRC2#
H/L : CPU_ITP/SRC7 SRC3 24
16 PM_STPPCI# 55 PCI_STOP# SRC3# 25
CPU_SEL1 7 26 RN10 1 4 SRN33J-5-GP-U CLK_PCIE_ICH 16
SRC4
CPU_SEL0 4,7 SRC4# 27 2 3 CLK_PCIE_ICH# 16
46 31 CLK_PCIE_ICH1
11,18 SMBC_ICH SCL SRC5
1




47 30 CLK_PCIE_ICH#1
11,18 SMBD_ICH SDA SRC5#
R102 33 CLK_MCH_3GPLL1 RN18 1 4 SRN47J-7-GP CLK_MCH_3GPLL 7
1KR2J-1-GP RN63 SRN33J-5-GP-U SRC6 CLK_MCH_3GPLL#1
SRC6# 32 2 3 CLK_MCH_3GPLL# 7
AG1-910-01 AG1-910-SB 3 2 DREFCLK_1 14
7 DREFCLK DREFCLK#_1 DOT96
4 1 15 36
2




SC22P50V2JN-4GP 7 DREFCLK# DOT96# CPU2_ITP/SRC7
CPU2_ITP#/SRC7# 35
C116 XTAL_IN 50 44 CLK_CPU_BCLK1 RN12 1 4 SRN33J-5-GP-U CLK_CPU_BCLK 4
XTAL_OUT XTAL_IN CPU0 CLK_CPU_BCLK#1
1 2 49 XTAL_OUT CPU0# 43 2 3 CLK_CPU_BCLK# 4
3 2 41 CLK_MCH_BCLK1
2 26 CLK_Audio CPU1
4 1 40 CLK_MCH_BCLK#1 RN11 1 4 SRN33J-5-GP-U CLK_MCH_BCLK 6
16 CLK_ICH14 CPU1#
RN13 SRN33J-5-GP-U 52 2 3 CLK_MCH_BCLK# 6
X1 REF
1 2 39 IREF CPU_STOP# 54 PM_STPCPU# 16,34
X-14D31818M-31GP R252 475R2F-L1-GP 53 CPU_SEL0
1



FSC/TEST_SEL CPU_SEL1
1 2 FSB/TEST_MODE 16
VTT_PWRGD# 10 12 FS_A 2 1
CPU C120 VTT_PWRGD#/PD USB48/FSA R103 22R2J-2-GP CLK48_ICH 16
FS_C FS_B FS_A CLK_ICH14 & CLK14_SIO
SC27P50V2JN-2-GP AG1-910-01
0 0 0 266M need equal length 2 34 3D3V_CLKGEN_S0
0 0 1 133M VSS_PCI VDD_SRC
6 VSS_PCI VDD_SRC 21
0 1 0 200M AG1-910-01
0 1 1 166M 51 7
1 0 0 333M VSS_REF VDD_PCI
45 VSS_CPU VDD_PCI 1
1 0 1 100M 38
1 1 0 400M VSSA
13 VSS48 VDD_REF 48
1 1 1 Reserved 29 42
VSS_SRC VDD_CPU 3D3V_APWR_S0
VDDA 37
11 3D3V_48MPWR_S0
VDD48
VDD_SRC 28
3D3V_S0

IDTCV125PAG-GP
8
7
6
5




AG1-A-SA
RN64
SRN10KJ-4-GP CLK_CPU_BCLK RN20 1 4 SRN49D9F-GP
CLK_CPU_BCLK# 2 3 EMI capacitor
1
2
3
4




CLK_MCH_BCLK RN19 1 4 SRN49D9F-GP CLK_ICH14 EC45 1 2 SC10P50V2JN-4GP
CLK_MCH_BCLK# 2 3 DY
PCLK_PCM EC41 1 2 SC10P50V2JN-4GP
DY
PCLK_MINI EC70 1 2 SC10P50V2JN-4GP
AG1-A-SA CLK_MCH_3GPLL RN14 1 4 SRN49D9F-GP DY
CLK_MCH_3GPLL# 2 3 PCLK_KBC EC42 1 2 SC10P50V2JN-4GP
VTT_PWRGD# ITP_EN DY
SS_SEL CLK_ICHPCI EC43 1 2 SC10P50V2JN-4GP
D DY
1




1




CLK_PCIE_ICH RN9 1 4 SRN49D9F-GP CLK48_ICH EC39 1 2 SC10P50V2JN-4GP
DY DY DY
3




CLK_PCIE_ICH# 2 3
Q23 R106 R104
10KR2J-2-GP 10KR2J-2-GP
2N7002PT-U




1
2




2




32,34 6218_PGOOD
G
AG1-910-01
2




S DREFSSCLK# 2 3
DREFSSCLK
RN60