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1 1
2 2
Compal Confidential
HGW51 Schematics Document
AMD/Sempron/ATI RS482M/SB450
3
2005 / 08 / 18 Rev:0.3 For C test 3
4 4
Security Classification Compal Secret Data
Issued Date 2005/05/09 Deciphered Date 2006/03/08 Title
Cover Sheet
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2931 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, August 18, 2005 Sheet 1 of 48
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A B C D E
Compal confidential
Project Code: HGW51 Thermal Sensor Clock Generator AMD Turion/Sempron CPU DDR-1 DDRI-SO-DIMM X2
File Name : LA-2931 BANK 0, 1, 2, 3page 8,9,10
ADM1032ARM ICS951412
page 4,5,6,7
page 4 page 15 One Channel DDR-1
1 1
H_A#(3..31) H_D#(0..63)
HT 16x16 800MHZ
CRT & TV-OUT ATI-RS482M
page 16
705 BGA
page 11,12,13,14
A-Link Express
2 x PCIE
LCD CONN
page 17
2
USB 2.0 USB conn x 3 2
page 35
ATI-SB450 USB 2.0 BT Conn
page 30
PCI BUS 564 BGA
Audio CKT
AC-LINK AMP & Audio Jack
AD1888 page 29
page 18,19,20,21 page 28
Mini PCI Realtek 1394 Controller
RTL8100CL ENE Controller MDC Conn. RJ11 CONN
Socket CB714 VT6311S page 30 page 26
page 31 page 26 page 27
page 24
SATA SATA HDD Conn.
page 23
6in1 CardReader LPC BUS
3
RJ45 CONN Slot 0 1 394 3
page 26 Slot page 25 Conn.
page 25 page 27
PATA HDD Conn.
CDROM Conn.
page 23
Power On/Off CKT.
page 36
SMsC LPC47N207 ENE KB910L
page 32 page 33
DC/DC Interface CKT. RTC CKT.
page 37 page 18
Int. KBD
Power Circuit DC/DC Power OK CKT. FIR module page 30
page 32
page 39~48 page 36 Touch Pad
4 4
CONN.page 30 BIOS
page 34
Button LED
page 36
Security Classification Compal Secret Data
Issued Date 2005/05/09 Deciphered Date 2006/03/08 Title
Block Diagrams
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2931 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, August 18, 2005 Sheet 2 of 48
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SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Voltage Rails
Full ON HIGH HIGH HIGH HIGH ON ON ON ON
Power Plane Description S1 S3 S4/ S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
VIN Adapter power supply (19V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
1 B+ AC or battery power rail for power circuit. N/A N/A N/A 1
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
+CPU_CORE Core voltage for CPU ON OFF OFF
+1.05VS 1.05V switched power rail ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+DDRVTT 0.9V switched power rail for DDR terminator ON OFF OFF
+1.5VALW 1.5V always on power rail ON ON ON*
+1.5VS 1.5V switched power rail ON OFF OFF Board ID Table for AD channel
+1.8VS 1.8V switched power rail ON OFF OFF Vcc 3.3V +/- 5%
+DDRVCC 1.8V power rail for DDR ON ON OFF Ra / Rc 100K +/- 5%
+2.5VS 2.5V switched power rail ON OFF OFF Board ID Rb / Rd V AD_BID min V AD_BID typ V AD_BID max
+3VALW 3.3V always on power rail ON ON ON* 0 0 0 V 0 V 0 V
+3V 3.3V power rail ON ON OFF 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+3VS 3.3V switched power rail ON OFF OFF 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+5VALW 5V always on power rail ON ON ON* 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+5VS 5V switched power rail ON OFF OFF 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+5VMOD 5V switched power rail for Module Bay ON OFF OFF 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
2 2
+12VALW 12V always on power rail ON ON ON* 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
+RTCVCC RTC power ON ON ON 7 NC 2.500 V 3.300 V 3.300 V
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF. BOARD ID Table BTO Option Table
External PCI Devices Board ID PCB Revision BTO Item BOM Structure
Device IDSEL# REQ#/GNT# Interrupts 0 0.1
C ardBus AD20 2 PIRQE/PIRQH 1 0.2
1394 AD16 0 PIRQE 2
SD AD20 2 PIRQE/PIRQH 3
Mini-PCI AD18 1 PIRQF 4
LAN AD22 3 PIRQG 5
6
3 3
7
EC SM Bus1 address EC SM Bus2 address
Device Address Device Address
Smart Battery 0001 011X b ADM1032 1001 110X b
EEPROM(24C16/02) 1010 000X b
(24C04) 1011 000Xb
SB450 SM Bus address
Device Address
4 4
Clock Generator 1101 001Xb
(ICS 951412AGT)
DDRII DIMM0 1001 000Xb
DDRII DIMM2 1001 010Xb Security Classification Compal Secret Data
Issued Date 2005/03/08 Deciphered Date 2006/03/08 Title
Notes
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom EFL50 LA-2761 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, August 18, 2005 Sheet 3 of 48
A B C D E
A B C D E
H_CADIP[0..15] H_CADOP[0..15]
<11> H_CADIP[0..15] H_CADIN[0..15] H_CADON[0..15] H_CADOP[0..15] <11>
<11> H_CADIN[0..15] H_CADON[0..15] <11>
U50A
4 Claw Hammer-DTR 4
H_CADIP15 T25 N26 H_CADOP15
H_CADIN15 L0_CADIN_H15 L0_CADOUT_H15 H_CADON15
R25 L0_CADIN_L15 L0_CADOUT_L15 N27
H_CADIP14 U27 L25 H_CADOP14
H_CADIN14 L0_CADIN_H14 L0_CADOUT_H14 H_CADON14
U26 L0_CADIN_L14 L0_CADOUT_L14 M25
H_CADIP13 V25 L26 H_CADOP13
H_CADIN13 L0_CADIN_H13 L0_CADOUT_H13 H_CADON13
U25 L0_CADIN_L13 L0_CADOUT_L13 L27
H_CADIP12 W27 J25 H_CADOP12
H_CADIN12 W26
L0_CADIN_H12
L0_CADIN_L12
L0_CADOUT_H12
L0_CADOUT_L12 K25 H_CADON12 FAN Conn
HTT Interface
H_CADIP11 AA27 G25 H_CADOP11
H_CADIN11 L0_CADIN_H11 L0_CADOUT_H11 H_CADON11
AA26 L0_CADIN_L11 L0_CADOUT_L11 H25
H_CADIP10 AB25 G26 H_CADOP10 +VSB
H_CADIN10 L0_CADIN_H10 L0_CADOUT_H10 H_CADON10
AA25 L0_CADIN_L10 L0_CADOUT_L10 G27
H_CADIP9 AC27 E25 H_CADOP9 +VSB
H_CADIN9 L0_CADIN_H9 L0_CADOUT_H9 H_CADON9
AC26 L0_CADIN_L9 L0_CADOUT_L9 F25 1
H_CADIP8 AD25 E26 H_CADOP8 +5VS U3B
H_CADIN8 L0_CADIN_H8 L0_CADOUT_H8 H_CADON8 C696
AC25 L0_CADIN_L8 L0_CADOUT_L8 E27
H_CADIP7 T27 N29 H_CADOP7 0.1U_0402_16V4Z 5
H_CADIN7 L0_CADIN_H7 L0_CADOUT_H7 H_CADON7 2 +IN
T28 L0_CADIN_L7 L0_CADOUT_L7 P29 OUT 7
8
1
2
5
6
H_CADIP6 V29 M28 H_CADOP6 U3A 6
H_CADIN6 L0_CADIN_H6 L0_CADOUT_H6 H_CADON6 D Q47 -IN
U29 M27
P
H_CADIP5 L0_CADIN_L6 L0_CADOUT_L6 H_CADOP5 EN_DFAN1 G
V27 L0_CADIN_H5 L0_CADOUT_H5 L29 <33> EN_DFAN1 3 +IN
H_CADIN5 V28 M29 H_CADON5 1FAN1 3 LM358A_SO8
H_CADIP4 L0_CADIN_L5 L0_CADOUT_L5 H_CADOP4 OUT S SI3456DV-T1_TSOP6 +3VS
Y29 L0_CADIN_H4 L0_CADOUT_H4 K28 2 -IN
H_CADIN4 W29 K27 H_CADON4
4
L0_CADIN_L4 L0_CADOUT_L4
G
1
H_CADIP3 AB29 H28 H_CADOP3 1
H_CADIN3 L0_CADIN_H3 L0_CADOUT_H3 H_CADON3 C698 LM358A_SO8 R639
AA29 H27
4
H_CADIP2 L0_CADIN_L3 L0_CADOUT_L3 H_CADOP2 10K_0402_5%
AB27 L0_CADIN_H2 L0_CADOUT_H2 G29
3 H_CADIN2 AB28 H29 H_CADON2 1U_0603_10V4Z 3
H_CADIP1 L0_CADIN_L2 L0_CADOUT_L2 H_CADOP1 2
AD29 F28
2
H_CADIN1 L0_CADIN_H1 L0_CADOUT_H1 H_CADON1
AC29 L0_CADIN_L1 L0_CADOUT_L1 F27 FAN_SPEED1 <33>
H_CADIP0 AD27 E29 H_CADOP0 C697 1
H_CADIN0 L0_CADIN_H0 L0_CADOUT_H0 H_CADON0 2200P_0402_50V7K
AD28 L0_CADIN_L0 L0_CADOUT_L0 F29
1 2 C699
0.01U_0402_16V7K
2
H_CLKIP1 Y25 J26 H_CLKOP1 R640
+1.2V_HT <11> H_CLKIP1 L0_CLKIN_H1 L0_CLKOUT_H1 H_CLKOP1 <11>
H_CLKIN1 W25 J27 H_CLKON1 100K_0402_5% JP43
<11> H_CLKIN1 L0_CLKIN_L1 L0_CLKOUT_L1 H_CLKON1 <11>
H_CLKIP0 Y27 J29 H_CLKOP0 1 2 FANVOUT1
<11> H_CLKIP0 L0_CLKIN_H0 L0_CLKOUT_H0 H_CLKOP0 <11> 1
22U_1206_10V4Z
H_CLKIN0 Y28 K29 H_CLKON0 2
<11> H_CLKIN0 L0_CLKIN_L0 L0_CLKOUT_L0 H_CLKON0 <11> 2
1
1
0.001U_0402_50V7M
150K_0402_5%
1 3
C1
R642 1 2 49.9_0402_1% H_CTLIP1 R27 N25 D25 C700
L0_CTLIN_H1 L0_CTLOUT_H1
R641
R643 1 2 49.9_0402_1% H_CTLIN1 R26 P25 RB751V_SOD323 ACES_85205-0300
H_CTLIP0 L0_CTLIN_L1 L0_CTLOUT_L1 H_CTLOP0 1
<11> H_CTLIP0 T29 L0_CTLIN_H0 L0_CTLOUT_H0 P28 H_CTLOP0 <11> CONN@
H_CTLIN0 H_CTLON0 2
<11> H_CTLIN0 R29 P27 H_CTLON0 <11>
2
2
L0_CTLIN_L0 L0_CTLOUT_L0
+1.2V_HT AF27 AJ27 LDTSTOP#
L0_REF1 LDTSTOP_L LDTSTOP# <13,18>
AE26 L0_REF0
R645 44.2_0603_1% 1 2 +2.5VS
2 1 LVREF1 FOX_PZ75403-2941-42 R644 680_0402_5%
CONN@
LVREF0
1
R646
2 2
44.2_0603_1%
2
+3VS
<6> THERMDA_CPU
THERMDA_CPU
Thermal Sensor
THERMDC_CPU
<6> THERMDC_CPU from EFL50
1
ADM1032
1
C702 R647
0.1U_0402_16V4Z @ 10K_0402_5%
2
1
C703
2
U53
2200P_0402_50V7K THERMDA_CPU 2 1
2 D+ VDD1
THERMDC_CPU 3 6
D- ALERT#
EC_SMB_CK2 8 4 THERM#
<33> EC_SMB_CK2 SCLK THERM#
EC_SMB_DA2 7 5
<33> EC_SMB_DA2 SDATA GND
1 1
ADM1032ARM_RM8
SMBus Address: 1001110X (b)
Security Classification Compal Secret Data
Issued Date 2005/05/09 Deciphered Date 2006/03/11 Title
Claw Harmmer CPU (Host Bus)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-2931 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, August 18, 2005 Sheet 4 of 48
A B C D E
A B C D E
+1.25VREF_CPU
+2.5V U50B
50 mil width AG12 MEMVREF1
DDR_CLK5/5# & DDR_CLK7/7#
34.8_0603_1% 2 1 R648 MEMZN D14
34.8_0603_1% 2 1 R649 MEMZP C14
MEMZN Claw Hammer-DTR route to nearest DIMM
MEMZP DDR_CLK4/4# & DDR_CLK6/6#
<8> DDR_SDQ[0..63]
DDR_SDQ63 A16 AE8 DDR_CKE0 route to farthest DIMM
MEMDATA63 MEMCKEA DDR_CKE0 <8>
DDR_SDQ62 B15 AE7 DDR_CKE1
MEMDATA62 MEMCKEB DDR_CKE1 <9>
DDR_SDQ61 A12
DDR_SDQ60 MEMDATA61 DDR_CLK7
1 B11 MEMDATA60 MEMCLK_H7 D10 DDR_CLK7 <8> 1
DDR_SDQ59 A17 C10 DDR_CLK7#
MEMDATA59 MEMCLK_L7 DDR_CLK7# <8>
DDR_SDQ58 A15 E12 DDR_CLK6
MEMDATA58 MEMCLK_H6 DDR_CLK6 <9>
DDR_SDQ57 C13 E11 DDR_CLK6#
MEMDATA57 MEMCLK_L6 DDR_CLK6# <9>
DDR_SDQ56 A11 AF8 DDR_CLK5 DDR_CLK7 R650 1 2 120_0402_5% DDR_CLK7#
MEMDATA56 MEMCLK_H5 DDR_CLK5 <8>
DDR_SDQ55 A10 AG8 DDR_CLK5# DDR_CLK6 R651 1 2 120_0402_5% DDR_CLK6#
MEMDATA55 MEMCLK_L5 DDR_CLK5# <8>
DDR_SDQ54 B9 AF10 DDR_CLK4 DDR_CLK5 R652 1 2 120_0402_5% DDR_CLK5#
MEMDATA54 MEMCLK_H4 DDR_CLK4 <9>
DDR_SDQ53 C7 AE10 DDR_CLK4# DDR_CLK4 R653 1 2 120_0402_5% DDR_CLK4#
MEMDATA53 MEMCLK_L4 DDR_CLK4# <9>
DDR_SDQ52 A6 V3
DDR_SDQ51 MEMDATA52 MEMCLK_H3
C11 MEMDATA51 MEMCLK_L3 V4
DDR_SDQ50 A9 K5
DDR_SDQ49 MEMDATA50