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5 4 3 2 1
SJM80_MV/JV80_MV Block Diagram Project code: 91.4DW01.001
SYSTEM DC/DC
TPS51125 43
PCB P/N : 48.4DW01.0SB INPUTS OUTPUTS
REVISION : 09221 -1
5V_S5
CLK GEN. Mobile CPU DCBATOUT
3D3V_S5
D
RTM875N-606-VD Penryn THERMAL EMC2102 D
23 PCB STACKUP
ICS9LPRS365 3
SYSTEM DC/DC
4, 5 TOP TPS51124 45
HOST BUS 667/800/[email protected] CRT VCC INPUTS OUTPUTS
17
DDR3 DIMM1 S
DCBATOUT
1D05V_S0
800/1066 MHz 800/1066MHz LCD
Cantiga 15 S
1D5V_S3
12 AGTL+ CPU I/F GND RT9026 44
DDR Memory I/F HDMI DDR_VREF_S3
DDR3 DIMM2 INTEGRATED GRAHPICS
18 BOTTOM 1D5V_S3
DDR_VREF_S3_1
800/1066 MHz 800/1066MHz LVDS, CRT I/F PCIex16
13 6,7,8,9,10,11 MXM 3.0 CONN AO4468 44
X4 DMI 30 1D5V_S3 1D5V_S0
C
INT.MIC C-Link0 C
35
400MHz
Line In GFXCORE DC/DC
Giga LAN ISL6263A 46
Codec
ICH9M PCIex1 BCM5784 TXFM RJ45
35 AZALIA 29 29 INPUTS OUTPUTS
ALC888S 6 PCIe ports 28
VC 33 PCI/PCI BRIDGE VGFXCORE
PWR SW DCBATOUT
MIC In
ACPI 2.0 PCIex1 New card 0.7~1.25V
4 SATA 31 G577BR91U31
35 12 USB 2.0/1.1 ports PCIex1 CPU DC/DC
ETHERNET (10/100/1000MbE) Mini Card ISL6266A 42
Kedron a/b/g/n 32
High Definition Audio
PCIex1 INPUTS OUTPUTS
LPC I/F Mini Card
35 OP AMP Serial Peripheral I/F Kedron a/b/g/n 32 VCC_CORE_S0
G1454 34 DCBATOUT
Matrix Storage Technology(DO) LPC BUS 0.35~1.5V
B
INT.SPKR Active Managemnet Technology(DO) B
BIOS CHARGER
MX25L16 MAX8731A 47
35 OP AMP LPC
G1412 34 KBC W25X16
16M Bits37 INPUTS OUTPUTS
Line Out WPC773 DEBUG
(SPDIF) 36 CONN 36 BT+
19,20,21,22 Launch
MODEM USB Buttom DCBATOUT
RJ11 MDC Card 14 DCBATOUT
25 Blue Tooth Touch INT.
Camera
(USB) Pad 38 KB 36 CIR
25 (USB) 15
37
SATA Finger
Printer38
USB
1st HDD SATA
24 4 Port 26
2nd HDD SATA
A SATA CardReader MS/MS Pro/xD SJM80 UMA ONLY SB A
ODD SATA 24 Realtek /MMC/SD
27 5 in 1 27 Wistron Corporation
RTS5159 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
BLOCK DIAGRAM
Size Document Number Rev
Custom
SJM80/JV80 -1
Date: Monday, May 25, 2009 Sheet 1 of 51
5 4 3 2 1
A B C D E
ICH9M Integrated Pull-up Cantiga chipset and ICH9M I/O controller
ICH9M Functional Strap Definitions Rev.1.5 page 92 Hub strapping configuration
ICH9 EDS 642879 and Pull-down Resistors Montevina Platform Design guide 22339
page 218
0.5
Signal Usage/When Sampled Comment ICH9 EDS 642879 Rev.1.5
HDA_SDOUT XOR Chain Entrance/ Allows entrance to XOR Chain testing when TP3 Pin Name Strap Description Configuration
PCIE Port Config1 bit1, pulled low.When TP3 not pulled low at rising edge SIGNAL Resistor Type/Value
Rising Edge of PWROK of PWROK,sets bit1 of RPC.PC(Config Registers: CL_CLK[1:0] PULL-UP 20K CFG[2:0] FSB Frequency 000 = FSB1067
offset 224h). This signal has weak internal pull-down Select 011 = FSB667
CL_DATA[1:0] PULL-UP 20K 010 = FSB800
others = Reserved
4 HDA_SYNC PCIE config1 bit0,
Rising Edge of PWROK.
This signal has a weak internal pull-down.
Sets bit0 of RPC.PC(Config Registers:Offset 224h)
CL_RST0# PULL-UP 20K
CFG[4:3] Reserved
4
DPRSLPVR/GPIO16 PULL-DOWN 20K CFG8
GNT2#/ PCIE config2 bit2, This signal has a weak internal pull-up. CFG[15:14]
GPIO53 Rising Edge of PWROK. Sets bit2 of RPC.PC2(Config Registers:Offset 0224h) ENERGY_DETECT PULL-UP 20K CFG[18:17]
GPIO20 Reserved This signal should not be pulled high. HDA_BIT_CLK PULL-DOWN 20K
CFG5 DMI x2 Select 0 = DMI x2
GNT1#/ ESI Strap (Server Only) ESI compatible mode is for server platforms only. HDA_DOCK_EN#/GPIO33 PULL-UP 20K 1 = DMI x4 (Default)
GPIO51 Rising Edge of PWROK This signal should not be pulled low for desttop CFG6 iTPM Host 0= The iTPM Host Interface is enabled(Note2)
and mobile. HDA_RST# PULL-DOWN 20K Interface 1=The iTPM Host Interface is disalbed(default)
HDA_SDIN[3:0] PULL-DOWN 20K 0 = Transport Layer Security (TLS) cipher
Top-Block Sampled low:Top-Block Swap mode(inverts A16 for CFG7 Intel Management suite with no confidentiality
GNT3#/ Swap Override. all cycles targeting FWH BIOS space). HDA_SDOUT PULL-DOWN 20K engine Crypto strap 1 = TLS cipher suite with
GPIO55 Rising Edge of PWROK. Note: Software will not be able to clear the confidentiality (default)
Top-Swap bit until the system is rebooted HDA_SYNC PULL-DOWN 20K
0 = Reverse Lanes,15->0,14->1 ect..
without GNT3# being pulled down. GLAN_DOCK# The pull-up or pull-down active when configured for native CFG9 PCIE Graphics Lane 1= Normal operation(Default):Lane
GLAN_DOCK# functionality and determined by LAN controller Numbered in order
GNT0#: Boot BIOS Destination Controllable via Boot BIOS Destination bit GNT[3:0]#/GPIO[55,53,51] PULL-UP 20K
SPI_CS1#/ Selection 0:1. (Config Registers:Offset 3410h:bit 11:10). 0 = Enable (Note 3)
GPIO58 Rising Edge of PWROK. GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC. GPIO[20] PULL-DOWN 20K CFG10 PCIE Loopback enable 1= Disabled (default)
Integrated TPM Enable, Sample low: the Integrated TPM will be disabled. GPIO[49] PULL-UP 20K 00 = Reserve
Rising Edge of CLPWROK Sample high: the MCH TPM enable strap is sampled CFG[13:12] XOR/ALL 10 = XOR mode Enabled
SPI_MOSI low and the TPM Disable bit is clear, the LDA[3:0]#/FHW[3:0]# PULL-UP 20K 01 = ALLZ mode Enabled (Note 3)
Integrated TPM will be enable. 11 = Disabled (default)
LAN_RXD[2:0] PULL-UP 20K
3 DMI Termination Voltage, The signal is required to be low for desktop LDRQ[0] PULL-UP 20K
CFG16 FSB Dynamic ODT 0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled (Default) 3
Rising Edge of PWROK. applications and required to be high for
GPIO49 mobile applications. LDRQ[1]/GPIO23 PULL-UP 20K 0 = Normal operation(Default):
CFG19 DMI Lane Reversal Lane Numbered in Order
PME# PULL-UP 20K
1 = Reverse Lanes
PCI Express Lane Signal has weak internal pull-up. Sets bit 27 PWRBTN# PULL-UP 20K DMI x4 mode[MCH -> ICH]:(3->0,2->1,1->2and0->3)
SATALED# Reversal. Rising Edge of MPC.LR(Device 28:Function 0:Offset D8) DMI x2 mode[MCH -> ICH]:(3->0,2->1)
of PWROK. SATALED# PULL-UP 15K
SPKR No Reboot. If sampled high, the system is strapped to the SPI_CS1#/GPIO58/CLGPIO6 PULL-UP 20K Digital Display Port 0 = Only Digital Display Port
Rising Edge of PWROK. "No Reboot" mode(ICH9 will disable the TCO Timer (SDVO/DP/iHDMI) or PCIE is operational (Default)
system reboot feature). The status is readable SPI_MOSI PULL-DOWN 20K CFG20 Concurrent with PCIe 1 =Digital display Port and PCIe are
via the NO REBOOT bit. operting simulataneously via the PEG port
SPI_MISO PULL-UP 20K
0 =No SDVO Card Present (Default)
TP3 XOR Chain Entrance. This signal should not be pull low unless using SPKR PULL-DOWN 20K SDVO_CTRLDATA SDVO Present
Rising Edge of PWROK. XOR Chain testing. 1 = SDVO Card Present
TACH_[3:0] PULL-UP 20K
0 = LFP Disabled (Default)
GPIO33/ Flash Descriptor Sampled low:the Flash Descriptor Security will be TP[3] PULL-UP 20K Local Flat Panel
HDA_DOCK Security Override Strap overridden. If high,the security measures will be L_DDC_DATA (LFP) Present 1= LFP Card Present; PCIE disabled
_EN# Rising Edge of PWROK in effect.This should only be enabled in manufacturing USB[11:0][P,N] PULL-DOWN 15K
environments using an external pull-up resister. NOTE:
1. All strap signals are sampled with respect to the leading edge of
the (G)MCH Power OK (PWROK) signal.
2. iTPM can be disabled by a 'Soft-Strap' option in the
2 Flash-decriptor section of the Firmware. This 'Soft-Strap' is 2
activated only after enabling iTPM via CFG6.
Only one of the CFG10/CFG/12/CFG13 straps can be enabled at any time.
SMBus
USB Table
USB
Pair Device MMB Left
PCIE Routing 0 USB2
LAN
LANE1 LAN Broadcom 5784
1 USB3 Thermal
LANE2 MiniCard WLAN New Card (NC)
2 USB4 THER_SCL
LANE3 MiniCard TV THER_SDA
3 MINI1 (WL) MXM
LANE4 NC Mini Card1 (NC)
4 CCD ICH9M
LANE5 NewCard
5 NEW CARD KBC
LANE6 NC MMB Right Mini Card2 (NC)
1 6 FP BAT_SCL
SJM80 UMA ONLY SB
1
BAT_SDA
7 BT
BATTERY SO-DIMM Wistron Corporation
8 NC 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
9 USB1
CHARGER CLK Gen Title
10 MINI2
Reference
11 CARD READER Size Document Number Rev
A3
SJM80/JV80 -1
Date: Monday, May 25, 2009 Sheet 2 of 51
A B C D E
3D3V_S0 1D05V_S0 3D3V_S0
R216
R218 R227
1 2 3D3V_48MPWR_S0
1D05V_CLKPLL_S0 2 1 3D3V_CLKGEN_S0 2 1
1
1
Do Not Stuff C309 C316 Do Not Stuff Do Not Stuff
1
1
1
1
1
1
1
1
1
1
1
1
1
1
SC1U16V3ZY-GP
DY C312 C322 C314 C329 C330 C318 C310 C325 C311 C321 C323 C331 C301
Do Not Stuff
Do Not Stuff
Do Not Stuff
SCD1U16V2ZY-2GP
SC4D7U10V5ZY-3GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
Do Not Stuff
DY C306
2
2
SC4D7U10V5ZY-3GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
Do Not Stuff
Do Not Stuff
CLK48_ICH
2
2
2
2
2
2
2
2
2
2
2
2
2
2
EMI
1
3D3V_S0 DY
EC44 DY
Do Not Stuff
2
DY
4
3
2
1
4 4
RN51
SRN10KJ-6-GP
3D3V_CLKGEN_S0
5
6
7
8
RN50 1D05V_CLKPLL_S0
20 SATACLKREQ# 1 8 PCLKCLK0
7 CLK_MCH_OE# 2 7 PCLKCLK1
28 LAN_CLKREQ# 3 6 CR#_H 3D3V_48MPWR_S0
4 5 CR#_G
SRN470J-3-GP
16
46
62
23
19
27