Text preview for : Compal_LA-9103P_r02_R0.1_1127.pdf part of Compal Compal LA-9103P r02 R0.1 1127 Compal Compal_LA-9103P_r02_R0.1_1127.pdf
Back to : Compal_LA-9103P_r02_R0.1_ | Home
A B C D E
MODEL NAME :VAW03 Inspiron Value OAK(Essentials) 15 UMA (Comal Richland)
PCB NO : LA-9103P Inspiron Value OAK(Essentials) 15 Discrete#1 (Comal Richland, AMD Mars Pro)
1 BOM P/N : DA60000UT00 LA-9103P M/B Inspiron MainStream OAK(Essentials) 15 UMA (Comal Richland) 1
DA40001FO00 LS-9101P POWER BUTTON/B Inspiron MainStream OAK(Essentials) 15 Discrete#2 (Comal Richland, AMD Mars Pro)
DA40001FP00 LS-9102P USB/B Vostro Value OAK(Essentials) 15 UMA (Comal Richland)
DA40001FQ00 LS-9103P TP BUTTON/B
2
Dell / Compal Confidential 2
Schematic Document
AMD FP2 Richland Processor with DDRIII + Bolton M3 FCH
AMD VGA Sun XT
3
X76@ : VRAM Group 3
46@ : for 46 level 2012-11-26 CH@ : Chelsea M2
@ : Nopop Component Rev: 0.2 SE@ : Seymour M2
CONN@ : Connector Component TH@ : Thames-XT
UMA@ : Only for UMA R1@ : R1 P/N for PCB Mars@ : Mars Pro M2
DIS@ : Only for Discrete R3@ : R3 P/N for PCB A4R1@ : A4 APU-R1
GCLK@ : Green CLK implemented THR1@ : Thames-XT R1 P/N A6R1@ : A6 APU-R1
NGCLK@ : Non Green CLK implemented THR3@ : Thames-XT R3 P/N A8R1@ : A8 APU-R1
4
@3221: ALC 3221 CHR1@ : Chelsea-Pro R1 P/N A8@ : A8 APU Symbol 4
@3223 : ALC 3223 CHR3@ : Chelsea-Pro R3 P/N Hud@ : HUDSON-M3
EMC@ : EMC Parts R@ : RTD2132-R Bol@ : BOLTON-M3
Compal Electronics, Inc.
2nd@ : for APL3512 2nd source control S@ : RTD2132-S Security Classification
Issued Date 2012/09/11
Compal Secret Data
Deciphered Date 2014/03/12 Title
Cover Page
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
A
(RN9, RV32, RL22) B C
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
D
Custom
Date:
LA-9103P
Tuesday, November 27, 2012
E
Sheet 1 of 52
0.1
A B C D E
1 1
128M*16
VRAM * 4
P.27
DDR3 Memory BUS(DDRIII)
128M*16
64bit
PCIE x 8 Gen2 AMD FP2 APU Dual Channel DDRIII-DIMM X2
BANK 0, 1, 2, 3, 4 ,5 ,6 ,7
AMD 1.5V DDRIII 1333MT/s
VRAM * 4 Sun-XT_M2 Trinity LV page 10,11
Upgradeable to 4G Memory
DDR3 P.28 64bit
18 W P.34~39
BGA 813 pin 8GB Max
DP Port0
LVDS
Translator HDMI Conn. DP Port2 page 5,~9
RTD2132R page 19
page 17
x4 UMI Gen. 1 Port 0
SATA HDD Conn.
P.32
2.5GT/s per lane
LVDS Conn.
page 18
SATA Port 1
SATA ODD Conn.
P.32
2 2
USB 3.0 Port 2,3
PCI-E 2.0 USB 3.0 Conn. 1
Bolton M3 Port 1,2
USB 3.0 Conn. 2
GPP1 GPP0 USB2.0
uFCBGA-656 USB 2.0 Conn. 3
Daughter
WLAN/WiMAX LAN(10/100) Port 0,10
Board
Realtek 8105E USB 2.0 Conn. 4
page 35
page 29
page 12,~16 HD Audio Port 9
Digital Camera
P.18
RJ45 CONN Port 1
page 29 Mini Card (WLAN)
LPC BUS P.35
Port 6 Card Reader 3 in 1
RTS5179 P.31 Socket
RTC CKT. ENE KBC
P.12 SPI ROM KB9012page
3
page 13
36
Analog Mic. 3
Power On/Off CKT. PS/2 Headphone Jack
P.38
Audio Codec Mic. Jack combo
Int.KBD Touch Pad
DC/DC Interface CKT. page 38 page 38 ALC3223 P.30
P.39 Int. Speaker R / L
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/09/11 Deciphered Date 2014/03/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-9103P
Date: Tuesday, November 27, 2012 Sheet 2 of 52
A B C D E
A B C D E
Compal Confidential
Project Code : VAW03
File Name : LA-9103P
1 1
LS-9101P (PWR/B)
UE5
Lid (SA00003VQ00)
SW1 4 pin-Hot Bar
(SN100004Y00)
PBATT
Battery
JMINI
PWR-BTN FFC
4 pin MINI Card JLVDS
40 pin
PJPDC JKB
5 pin 30 pin
2 2
JTP
LS-9102P (USB/B)
6 pin
JHDMI HDMI
JPWR
JODD
4 pin JFAN
3 pin USB2.0 JUSB4
USB-DB FFC 8 pin
HDT 8 pin Hot Bar
JLAN RJ-45
JXDP
LA-9103P M/B JDB
8 pin
JUSB1 USB3.0 Top Side JHDD
RTC JRTC
Bottom Side
2 pin
JUSB2 USB3.0 (OAK 15")
3 3
JUSB3 USB2.0
JREAD
TP-MB FFC JSPK
6 pin 4 pin
JHP Card
HP Reader
Led1 Led3
Led2 Led4
TP-Module
TP-BTN FFC
4 4 pin 4
LS-9103P (TP-BTN/B)
4 pin
Hot Bar
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/09/11 Deciphered Date 2014/03/12 Title
SW2 SW3 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DaughterB block diagram
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9103P
Date: Tuesday, November 27, 2012 Sheet 3 of 52
A B C D E
A
Board ID Table for AD channel
Vcc 3.3V +/- 5% BOARD ID Table
Ra 100K +/- 5%
Board ID Rb V AD_BID min V AD_BID typ V AD_BID max EC AD3 Board ID PCB Revision USB PORT# DESTINATION
0 0 0 V 0 V 0.155 V 0x00-0x0C 0 0.1
1 8.2K +/- 5% 0.168 V 0.250 V 0.362 V 0x0D-0x1C 1 0.2 0 USB conn.3 DEBUG PORT
2 18K +/- 5% 0.375 V 0.503 V 0.621 V 0x1D-0x30 2 0.3
3 33K +/- 5% 0.634 V 0.819 V 0.945 V 0x31-0x49 3 1.0 1 MINI CARD (WLAN)
4 56K +/- 5% 0.958 V 1.185 V 1.359 V 0x4A-0x69 4
5 100K +/- 5% 1.372 V 1.650 V 1.838 V 0x6A-0x8E 5 2 USB conn.4
6 200K +/- 5% 1.851 V 2.200 V 2.420 V 0x8F-0xBB 6
7 NC 2.433 V 3.300 V 3.300 V 0xBC-0xFF 7 3 NC
4 NC
EC SM Bus1 address EC SM Bus2 address FCH
5 NC
Device Address HEX Device Address HEX
Smart Battery 000 1011 11h 0x16 ADM1032ARMZ 100 1101 4Dh 0x9A
6 Card Reader
Charger IC 000 1001 09h 0x12 SB-TSI 100 1100 4Ch 0x98
RTD2132 100 1010 4Ah 0x94
7 NC
GPU 100 0001 41h 0x82
SM Bus Controller 0 (FCH_SMB1 ~ FCH_SMB4, SMB_ALERT#) : etoN lobmyS 8 NC
Device Address HEX
dnuorG latigiD snaem : 9 Camera
APU SIC/SID (FCH_SMB3)
10 USB conn.2
SM Bus Controller 1 (FCH_SMB0)
dnuorG golanA snaem :
Device Address HEX 11 NC
DDR DIMM1 (FCH_SMB0) 1001-000xb 90 12 NC
DDR DIMM2 (FCH_SMB0) 1001-001xb 92
1 1
WLAN (FCH_SMB0)
13 USB conn.1
DIFFERENTIAL DESTINATION SATA DESTINATION PCI EXPRESS DESTINATION
CLKOUT_PCIE0 None SATA0 HDD Lane 1 10/100 LAN
CLKOUT_PCIE1 None SATA1 ODD Lane 2 MINI CARD (WLAN)
CLKOUT_PCIE2 10/100 LAN SATA2 None Lane 3 None
CLK CLKOUT_PCIE3 MINI CARD WLAN SATA3 None Lane 4 None
CLKOUT_PCIE4 None SATA4 None Lane 5 None
CLKOUT_PCIE5 None SATA5 None Lane 6 None
CLKOUT_PCIE6 None Lane 7 None
CLKOUT_PCIE7 None Lane 8 None
CLKOUT_PEG_B None
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/09/11 Deciphered Date 2014/03/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9103P
Date: Tuesday, November 27, 2012 Sheet 4 of 52
A
A B C D E
21 PCIE_CRX_GTX_P[0..7] PCIE_CTX_GRX_P[0..7] 21
21 PCIE_CRX_GTX_N[0..7] PCIE_CTX_GRX_N[0..7] 21
U1A
PCIE_CRX_GTX_P0 AP1 AN1 PCIE_CTX_C_GRX_P0 CC48 DIS@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_P0
PCIE_CRX_GTX_N0 AP2 P_GFX_RXP[0] P_GFX_TXP[0] AN2 PCIE_CTX_C_GRX_N0 CC49 DIS@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N0
PCIE_CRX_GTX_P1 AM1 P_GFX_RXN[0] P_GFX_TXN[0] AM4 PCIE_CTX_C_GRX_P1 CC50 DIS@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_P1
PCIE_CRX_GTX_N1 AM2 P_GFX_RXP[1] P_GFX_TXP[1] AM3 PCIE_CTX_C_GRX_N1 CC51 DIS@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N1
PCIE_CRX_GTX_P2 AK3 P_GFX_RXN[1] P_GFX_TXN[1] AK2 PCIE_CTX_C_GRX_P2 CC52 DIS@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_P2
PCIE_CRX_GTX_N2 AK4 P_GFX_RXP[2] P_GFX_TXP[2] AK1 PCIE_CTX_C_GRX_N2 CC53 DIS@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N2
1 PCIE_CRX_GTX_P3 AJ1 P_GFX_RXN[2] P_GFX_TXN[2] AH1 PCIE_CTX_C_GRX_P3 CC54 DIS@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_P3 1
PCIE_CRX_GTX_N3 AJ2 P_GFX_RXP[3] P_GFX_TXP[3] AH2 PCIE_CTX_C_GRX_N3 CC55 DIS@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N3 U1 A4R1@
PCIE_CRX_GTX_P4 AH4 P_GFX_RXN[3] P_GFX_TXN[3] AF3 PCIE_CTX_C_GRX_P4 CC56 DIS@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_P4
PCIE_CRX_GTX_N4 AH3 P_GFX_RXP[4] P_GFX_TXP[4] AF4 PCIE_CTX_C_GRX_N4 CC57 DIS@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N4
PCIE_CRX_GTX_P5 AF2 P_GFX_RXN[4] P_GFX_TXN[4] AE1 PCIE_CTX_C_GRX_P5 CC58 DIS@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_P5
PCIE_CRX_GTX_N5 AF1 P_GFX_RXP[5] P_GFX_TXP[5] AE2 PCIE_CTX_C_GRX_N5 CC59 DIS@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N5
XXXXXXXXXXX
PCIE_CRX_GTX_P6 AD1 P_GFX_RXN[5] P_GFX_TXN[5] AD4 PCIE_CTX_C_GRX_P6 CC60 DIS@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_P6
PCIE_CRX_GTX_N6 AD2 P_GFX_RXP[6] P_GFX_TXP[6] AD3 PCIE_CTX_C_GRX_N6 CC61 DIS@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N6
P_GFX_RXN[6] P_GFX_TXN[6] A4 SERIES AM4355SHE23HJ 1.9G BGA813
PCIE_CRX_GTX_P7 AB3 AB2 PCIE_CTX_C_GRX_P7 CC62 DIS@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_P7
GRAPHICS
PCIE_CRX_GTX_N7 AB4 P_GFX_RXP[7] P_GFX_TXP[7] AB1 PCIE_CTX_C_GRX_N7 CC63 DIS@ 1 2 0.1U_0402_16V7K PCIE_CTX_GRX_N7 U1 A6R1@
AA1 P_GFX_RXN[7] P_GFX_TXN[7] Y1
AA2 P_GFX_RXP[8] P_GFX_TXP[8] Y2
Y4 P_GFX_RXN[8] P_GFX_TXN[8] V3
Y3 P_GFX_RXP[9] P_GFX_TXP[9] V4
SA00006KB0L
V2 P_GFX_RXN[9] P_GFX_TXN[9] U1
V1 P_GFX_RXP[10] P_GFX_TXP[10] U2
P_GFX_RXN[10] P_GFX_TXN[10] A6 SERIES ZM229069E23HL 2.2G BGA 813P
T1 T4
T2 P_GFX_RXP[11] P_GFX_TXP[11] T3 U1 A8R1@
P3 P_GFX_RXN[11] P_GFX_TXN[11] P2
P4 P_GFX_RXP[12] P_GFX_TXP[12] P1
N1 P_GFX_RXN[12] P_GFX_TXN[12] M1
N2 P_GFX_RXP[13] P_GFX_TXP[13] M2
SA00006HK0L
M4 P_GFX_RXN[13] P_GFX_TXN[13] K3
M3 P_GFX_RXP[14] P_GFX_TXP[14] K4
P_GFX_RXN[14] P_GFX_TXN[14] A8 SERIES ZM178570E44HL 1.7G BGA 813P
K2 J1
K1 P_GFX_RXP[15] P_GFX_TXP[15] J2 ZZZ R1@
P_GFX_RXN[15] P_GFX_TXN[15]
AH5 AG7 PCIE_CTX_C_DRX_P0 CC80 1 2 0.1U_0402_16V7K
29 PCIE_CRX_DTX_P0 AH6 P_GPP_RXP[0] P_GPP_TXP[0] AG8 PCIE_CTX_C_DRX_N0 1 2 0.1U_0402_16V7K PCIE_CTX_DRX_P0 29
LAN CC81 LAN
29 PCIE_CRX_DTX_N0 AG5 P_GPP_RXN[0] P_GPP_TXN[0] AE7 PCIE_FTX_C_DRX_P1 0.1U_0402_16V7K 1 2 CC82 PCIE_CTX_DRX_N0 29
35 PCIE_FRX_DTX_P1 AG6 P_GPP_RXP[1] P_GPP_TXP[1] AE8 1 2 CC83 PCIE_FTX_DRX_P1 35
WLAN PCIE_FTX_C_DRX_N1 0.1U_0402_16V7K WLAN
35 PCIE_FRX_DTX_N1 AE6 P_GPP_RXN[1] P_GPP_TXN[1] AD7 PCIE_FTX_DRX_N1 35
P_GPP_RXP[2] P_GPP_TXP[2] PCB 0XO LA-9103P REV0 M/B
2 AE5 AD8 2
AD6 P_GPP_RXN[2] P_GPP_TXN[2] AB6
DA60000XN00
GPP
AD5 P_GPP_RXP[3] P_GPP_TXP[3] AB5
P_GPP_RXN[3] P_GPP_TXN[3] Move from FCH for WLAN/EXP PCIE I/F. 20110819
AM10 AN6 UMI_TXP0_C CC84 1 2 0.1U_0402_16V7K
12 UMI_RXP0 AN10 P_UMI_RXP[0] P_UMI_TXP[0] AM6 UMI_TXN0_C 1 2 UMI_TXP0 12
CC85 0.1U_0402_16V7K
12 UMI_RXN0 AN8 P_UMI_RXN[0] P_UMI_TXN[0] AP6 UMI_TXP1_C 1 2 UMI_TXN0 12
CC86 0.1U_0402_16V7K
12 UMI_RXP1 AM8 P_UMI_RXP[1] P_UMI_TXP[1] AR6 1 2 UMI_TXP1 12
UMI_TXN1_C CC87 0.1U_0402_16V7K
12 UMI_RXN1 AP8 P_UMI_RXN[1] P_UMI_TXN[1] AP4 UMI_TXP2_C 1 2 UMI_TXN1 12
CC88 0.1U_0402_16V7K
12 UMI_RXP2 AR8 P_UMI_RXP[2] P_UMI_TXP[2] AR4 UMI_TXN2_C 1 2 UMI_TXP2 12
CC89 0.1U_0402_16V7K
12 UMI_RXN2 AR7 P_UMI_RXN[2] P_UMI_TXN[2] AP3 UMI_TXP3_C 1 2 UMI_TXN2 12
CC90 0.1U_0402_16V7K
12 UMI_RXP3 AP7 P_UMI_RXP[3] P_UMI_TXP[3] AR3 1 2 UMI_TXP3 12
UMI_TXN3_C CC91 0.1U_0402_16V7K
UMI
12 UMI_RXN3 P_UMI_RXN[3] P_UMI_TXN[3] UMI_TXN3 12
1 2 P_ZVDDP AR11 AP11 P_ZVSS 1 2
+1.2VS P_ZVDDP P_ZVSS
RC1 196_0402_1% RC2 196_0402_1%
TRINITY-A8-SERIES_BGA813
A8@
3 3
Power Sequence of APU
+1.5V
+2.5VS Group A
+1.5VS
+APU_CORE
Group B
4 +APU_CORE_NB 4
+1.2VS
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/09/11 Deciphered Date 2014/03/12 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
FP2 PCIE/UMI
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-9103P
Date: Tuesday, November 27, 2012 Sheet 5 of 52
A B C D E
A B C D E
1 1
U1B
10 DDRA_SMA[15..0] DDRA_SMA0 AA28 F15 DDRA_SDQ0 DDRA_SDQ[63..0] 10 U1C
R29 MA_ADD[0] MA_DATA[0] E15 11 DDRB_SMA[15..0] Y33 C16 DDRB_SDQ[63..0] 11
DDRA_SMA1 DDRA_SDQ1 DDRB_SMA0 DDRB_SDQ0
DDRA_SMA2 T30 MA_ADD[1] MA_DATA[1] H19 DDRA_SDQ2 DDRB_SMA1 R32 MB_ADD[0] MB_DATA[0] B17 DDRB_SDQ1
DDRA_SMA3 R28 MA_ADD[2] MA_DATA[2] F19 DDRA_SDQ3 DDRB_SMA2 T31 MB_ADD[1] MB_DATA[1] B20 DDRB_SDQ2