Text preview for : Acer TravelMate 8572_8572Z_Quanta_ZR9_Rev1A.pdf part of acer Acer TravelMate 8572 8572Z Quanta ZR9 Rev1A acer Acer TravelMate 8572_8572Z_Quanta_ZR9_Rev1A.pdf



Back to : Acer TravelMate 8572_8572 | Home

5 4 3 2 1




GPU CORE PWR CHARGER
ISL6264 P44 ISL88731 P50
[email protected] --> iGPU & GPU Switch
[email protected] --> iGPU only GPU IO PWR 3/5V SYS PWR
[email protected] --> GPU only ISL62827 P45 ISL6237 P49
[email protected] --> GPU N11P only
D
[email protected] --> GPU N11M only DISCHARGER CPU CORE PWR D
+3V,+ 5V,+1.5V,+1.05V,+1.1V_VTT
[email protected] --> Operation P/N P51 ISL62882 P42
CLOCK GENERATOR Fan Driver
SELGO: SLG8SP585V
BCLK: 133MHz
PEG_CLK: 100MHz
DPLL_REF_SSCLK: 120MHz
intel (PWM Type) +1.0V/+1.5V CPU VTT
ARD: 1.05V
CFD: 1.1V

Optional X'TAL
14.318MHz P3
P34 G93334 + Linear P51 UP61111AQDD P46

DOCKING




DDR SYSTEM MEMORY
CPU VGFX_AXG VTT 1.05V
Dual Channel Arrandale (SG) * ISL62881 P43 UP61111AQDD P47

DVI DDR III
SO-DIMM 0
800/ 1066 MHz
THERMAL DDR3 PWR
SO-DIMM 1 800 MT/s 1066 MT/s PROTECTION P41 TPS5116 P48
VGA P14, 15 rPGA37.5mm)
989
(37.5mm X
PCI-E PCIE
RJ45 X16
P4.5.6.7 Nvidia GPU
FDI DMI 2.5GT/s CRT
USBX4 N11M 512M
(64Mb x 32 IO x 8 pcs) LVDS LVDS_CRT_Switch
AC JACK HDMI Grapgics CRT
C
* [Arrandale Only]
X4 DMI interface P16,17,18,19,20,21,22,23 P27 C



X'TAL
AUDIO/SPDIF 27.0MHz




Graphics Interfaces
FDI DMI P23 LVDS
MIC / LINE-IN INT_CRT * [Arrandale Only] P24

HDD (SATA) *1
intel INT_LVDS *[Arrandale Only]
Docking DVI P25
P29 SATA0
INT_HDMI *[Arrandale Only] HDMI/DVI PS8101 P24, 25
SATA
3.0 GT/s USB0
Ibex Peak_M
Card Reader SATA1
Connector ODD (SATA)
AU6437 P25 PCI-Express PCIE-2 Mini card
P29 PCI-E
2.5GT/s CLKOUT_PEG_4 3G/GPS P28
USB 10
USB Port x 4
USB 1, 3, 11, 12 P31 USB 2.0 PCIE-6
B
USB mBGA 676 CLKOUT_PEG_1&3
Mini Card B
(27mm X 25mm) RTC
X'TAL WLAN
P9
Bluetooth 32.768KHz PCIE-1 USB 13 P28
Azalia HDA
P8.9.10.11.12.13 CLKOUT_PEG_B
USB 4 P32
Broadcom
SPI LPC
CCD Giga-LAN
USB 8 P23 X'TAL BCM57760
32.768KHz P26
X'TAL
Audio CODEC SPI ROM EC (WPC781) TPM 25MHz
FingerPrint 4MB x1 (Basic ME+Braidwood) SLB 9635 P31
CX20672 P30 P9 Docking SW
USB 2 P34 P38
PI3L500 P27

SIMM card




Docking
MDC Transformer P27
USB 0 P28 P33
SPI ROM
P38

A A
RJ45 Connector
P27
Touch Pad
P34

Quanta Computer Inc.
AUDIO Jack Speaker Docking Docking MIC Jack Int. D-MIC PROJECT : ZR9
S/PDIF Line P33
in
K/B COON. Size Document Number Rev
P30 P30 P33 P30 P23 P34
1A
Block Diagram
Date: Thursday, April 29, 2010 Sheet 1 of 47
5 4 3 2 1
1 2 3 4 5 6 7 8



GPU PWR CTRL Option 1 (Default/ VDDR3 before VDDC)
+3.3V VIN VIN +1.5V +1.5V_SUS +1.8V +5V



VDDR3 +3V_D VDDC PG_GPUIO_EN VDDCI PG_1V_EN +1V (DP PLL PWR) PG_1.5V_EN VDDR1 PG_1.5V_EN VDDR4 PG_1.5V_EN BJT dGPU_PWROK MOS
dGPU_VRON dGPU_PWR_EN#
MOS (AO3413) ISL6264 ISL62872 G9334ADJ & MOS MOS (AO4710) MOS (AO6402) AO3413
P22 P44 P45 P47 P43 P43 P22 P22
A A




+3_D (0.5A) +VGPU_CORE (20A) +VGPU_IO (4.5A) +1V (3A) +1.5V_GPU (10A) +1.8V_GPU (3A) +5_GPU


GPU PWR CTRL Option 2 (VDDR3 after VDDR1)
VIN VIN +1.5V +1.5V_SUS +3.3V +1.8V +5V



VDDC PG_GPUIO_EN VDDCI PG_1V_EN +1V (DP PLL PWR) PG_1.5V_EN VDDR1 +1.5V_GPU VDDR3 +3V_D VDDR4 PG_1.5V_EN BJT dGPU_PWROK MOS
dGPU_VRON dGPU_PWR_EN#
ISL6264 ISL62872 G9334ADJ & MOS MOS (AO4710) MOS (AO3413) MOS (AO6402) AO3413
P44 P45 P47 P43 P22 P43 P22 P22



+VGPU_CORE (20A) +VGPU_IO (4.5A) +1V (3A) +1.5V_GPU (10A) +3_D (0.5A) +1.8V_GPU (3A) +5_GPU
B B



Power States Thermal Follow Chart
CONTROL
POWER PLANE VOLTAGE DESCRIPTION SIGNAL ACTIVE IN

VIN +10V~+19V MAIN POWER S0~S5

+RTC_CELL +3V~+3.3V RTC S0~S5 NTC
+3VPCU +3.3V 8051 POWER ALWON S0~S5 Thermal
Protection
+5VPCU +5V CHARGE POWER ALWON S0~S5

+15V +15V LARGE POWER +15V_ALWP S0~S5

3V_LAN_S5 +3.3V LAN POWER AUX_ON
CPU H_ORICHOT# PM_THRMTRIP# SYS_SHDN# 3V/5 V
+5VSUS +5V SUSD
CORE PWR H/W Throttling
CPU WIRE-AND SYS PWR
C C

+3VSUS +3.3V SUSD

+1.5VSUS +1.5V SODIMM POWER SUSON

+0.75V_DDR_VTT +0.9V SODIMM POWER MAINON SML1ALERT#

+5V +5V MAIND PCH FAN Driver FAN
+3V +3.3V MAIND

+1.8V +1.8V MAINON SM-Bus

+1.5V +1.5V PCH POWER MAIND

+1.1V_VTT +1.05V~+1.1V CPU POWER MAINON EC
CPUFAN#
+1.05V +1.05V PCH POWER MAINON

+VCC_CORE 0V~+1.5V CPU CORE POWER VRON
D D


LCDVCC +3.3V LCD Power LVDS_VDDEN

MBAT+ +10V~+17V MAIN BATTERY
Quanta Computer Inc.
+5V_S5 +5V S5_ON
PROJECT : ZR9
+3V_S5 +3.3V S5D Size Document Number Rev
1A
PWR Status & GPU PWR CRL & THRM
Date: Thursday, April 29, 2010 Sheet 2 of 47
1 2 3 4 5 6 7 8
5 4 3 2 1

+1.5V
180ohm/1.5A 150mA(20mil)
L33 BKP1608HS181T_6_1.5A +1.5V_CLK U26

C456 C452 C451 C492 1 80mA(20mil)
R324 VDD_DOT +VDDIO_CLK L37 BKP1608HS181T_6_1.5A
5 VDD_27 VDD_SRC_I/O 15 +1.05V
4.7U/10V_8 0.1U/16V_4 0.1U/16V_4 0.1U/16V_4 *[email protected]_6 17 18
+3V VDD_SRC VDD_CPU_I/O C476 C499 C475 C494
D 24 VDD_CPU D
29 VDD_REF DOT_96 3 CLK_BUF_DREFCLKP (10)
L38 BKP1608HS181T_6_1.5A +3V_CLK 4 0.1U/16V_4 0.1U/16V_4 10U/10V_8 10U/10V_8
DOT_96# CLK_BUF_DREFCLKN (10)
CLK_SDATA 31
C463 C471 C442 CLK_SCLK SDA R345 *0/J_4
32 SCL 27M 6 27M_CLK (18)
7 R354 *0/J_4
CLK_27M_SS (18)
Place each 0.1uF cap as close as
4.7U/10V_8 0.1U/16V_4 27M_SS C491 *10p/50V_4 possible to each VDD IO pin. Place
0.1U/16V_4 R320 33/J_4 CPU_SEL 30 10 the 10uF caps on the VDD_IO plane.
(10) CLK_ICH_14M REF_0/CPU_SEL SRC_1/SATA CLK_BUF_PCIE_3GPLLP (10)
SRC_1#/SATA# 11 CLK_BUF_PCIE_3GPLLN (10)
C432 33P/50V_4 13
SRC_2 CLK_BUF_DREFSSCLKP (10)
SRC_2# 14 CLK_BUF_DREFSSCLKN (10)




1
XTAL_IN 28
Y3 XTAL_IN +3V
14.318MHZ XTAL_OUT 27 16 R353 10K/J_4
XTAL_OUT *CPU_STOP#




2
C435 33P/50V_4 2 20
VSS_DOT CPU_1 TP34
8 VSS_27 CPU_1# 19 TP33
C 9 VSS_SATA CPU_0 23 CLK_BUF_BCLKP (10) C
12 VSS_SRC CPU_0# 22 CLK_BUF_BCLKN (10)
21 VSS_CPU
26 25 CK_PWRGD_R
VSS_REF CKPWRGD/PD#
33 GND

SLG8SP595V



+3V +3V
CPU_CLK select SMBus CLK Enable
+1.05V
R330
R327 1K/F_4
B B




2
R312 2.2K/J_4
*10K/J_4 CK_PWRGD_R
3 1 CLK_SDATA CLK_SDATA (14,15,28)
(10,26,28) ICH_SMBDATA




3
Q16
CPU_SEL Q39 2N7002K
2N7002K
(39) VR_PWRGD_CK505# 2 R329
R319 100K/F_4
10K/J_4 C430 +3V
*10P/50V_4




1
R326




2
2.2K/J_4
0 1
A
(10,26,28) ICH_SMBCLK 3 1 CLK_SCLK CLK_SCLK (14,15,28) Quanta Computer Inc. A



CPU_SEL CPU0/1=133MHz CPU0/1=100MHz Q38
2N7002K
PROJECT :ZR9
(default)
Size Document Number Rev
1A
Clock Generator
Date: Thursday, May 06, 2010 Sheet 3 of 47
5 4 3 2 1
5 4 3 2 1



AUBURNDALE/CLARKSFIELD PROCESSOR (DMI,PEG,FDI) AUBURNDALE/CLARKSFIELD PROCESSOR (CLK,MISC,JTAG)

Processor Compensation Signals
U42A U42B
B26 R517 49.9/F_4 R563 20/F_4 H_COMP3 AT23
PEG_ICOMPI COMP3
A26 A16 CLK_CPU_BCLKP (11)
PEG_ICOMPO BCLK




MISC
MISC
A24 B27 R565 20/F_4 H_COMP2 AT24 B16 CLK_CPU_BCLKN (11)
(8) DMI_TXN0 DMI_RX#[0] PEG_RCOMPO COMP2 BCLK#
C23 A25 R516 750/F_4
(8) DMI_TXN1 DMI_RX#[1] PEG_RBIAS R128 49.9/F_4 H_COMP1




CLOCKS
(8) DMI_TXN2 B22 PEG_RXN[0..15] (16) G16 AR30 TP58
DMI_RX#[2] PEG_RXN0 COMP1 BCLK_ITP
(8) DMI_TXN3 A21 K35 AT30 TP60
D DMI_RX#[3] PEG_RX#[0] PEG_RXN1 R564 49.9/F_4 H_COMP0 BCLK_ITP# D
J34 AT26
PEG_RX#[1] PEG_RXN2 COMP0
(8) DMI_TXP0 B24 J33 E16 CLK_PCIE_3GPLLP (10)
DMI_RX[0] PEG_RX#[2] PEG_RXN3 PEG_CLK
(8) DMI_TXP1 D23 G35 D16 CLK_PCIE_3GPLLN (10)
DMI_RX[1] PEG_RX#[3] PEG_CLK#




DMI
DMI
B23 G32 PEG_RXN4 R157 *1K/J_4 TP_SKT0CC# AH24
(8) DMI_TXP2 DMI_RX[2] PEG_RX#[4] SKTOCC#
A22 F34 PEG_RXN5 A18 DPLL_REF_SSCLKP (10)
(8) DMI_TXP3 DMI_RX[3] PEG_RX#[5] DPLL_REF_SSCLK
F31 PEG_RXN6 A17 DPLL_REF_SSCLKN (10)
PEG_RX#[6] PEG_RXN7