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1 1




Compal confidential
2



LC-Marseille 10AD 2




PWWAE LA-6843P Schematics Document

Mobile AMD S1G4/ RS880M / SB820M
3 3



2010-08-16 Rev. 1.0




4 4




Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010-08-25 Deciphered Date 2010-08-25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A6843
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401982 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, September 01, 2010 Sheet 1 of 40
A B C D E
A B C D E




Compal Confidential Thermal Sensor Fan Control AMD S1G4 CPU
Memory BUS(DDRIII)
200pin DDRIII-SO-DIMM X2
page 5 Dual Channel
ADM1032ARMZ page 7 BANK 0, 1, 2, 3 page 9,10
Model Name : PWWAA uFCPGA-638 Package 1.5V DDRIII 1066/1333MHZ

File Name : LA-6843P page 5,6,7,8

1 Hyper Transport Link 2.6GHz 1

16X16
RTL8105E 10/100M
PCIe port 3 RJ45
page 24
page 24

AMD
CRT
page 16
RS880M

LCD Conn. PCIe 4x
page 17 1.5V 2.5GHz(250MB/s)
WLAN
PCIe port 2
page 23
page 11,12,13,14,15
LAN
PCIe port 3
2 2
A-Link Express II page 24
4X PCI-E
IO/B-- USB Right
USB port 0,1
page 23
USB
5V 480MHz
SATA port 0 SATA HDD
Card Reader Int. Camera 5V 1.5GHz(150MB/s) page 23
USB port 5
page 25
USB port 9
page 17
AMD
SATA port 1 SATA ODD
5V 1.5GHz(150MB/s) page 23
SB820M
WLAN USB
USB port 8 5V 480MHz
page 27


page 18,19,20,21,22

3 3




3.3V 33 MHz
HD Audio 3.3V/1.5V 24MHz

LPC BUS
RTC CKT. HDA Codec
ALC259
page 26
Debug Port ENE KB926 E0
Power On/Off CKT. page 29 page 28
page 30
Power/B
Int.
page 30 MIC CONN MIC CONN HP CONN SPK CONN
page 17 page 27 page 27 page 27
DC/DC Interface CKT. Touch Pad Int.KBD EC ROM
page 30 page 29 page 29
page 31


Power Circuit DC/DC
4 4
page 31,32,33,34,35
36,37,38,39




Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010-08-25 Deciphered Date 2010-08-25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A6843
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 401982 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, September 01, 2010 Sheet 2 of 40
A B C D E
5 4 3 2 1




DESIGN CURRENT 0.1A +3VL
DESIGN CURRENT 0.1A +5VL
B+
RT8205EGQW DESIGN CURRENT 1A +3VALW
DESIGN CURRENT 3.5A +5VALW
D D

SUSP
N-CHANNEL DESIGN CURRENT 2A +5VS
SI4800

WOL_EN#
P-CHANNEL DESIGN CURRENT 330mA +3V_LAN
AO-3413
SUSP
DESIGN CURRENT 1.5A +3VS
N-CHANNEL
SI4800
ENVDD
P-CHANNEL DESIGN CURRENT 1A +LCD_VDD
AO-3413
C C
DESIGN CURRENT 300mA +2.5VS
APL5508
PWWAE LC-Marseille AMD
SUSP#
DESIGN CURRENT 2.5A +1.8VS
MP2121DQ

POK
DESIGN CURRENT 0.3A +1.1VALW
RT8209BGQW
VLDT_EN#
N-CHANNEL DESIGN CURRENT 3.5A +1.1VS
IRF8113
VLDT_EN#
N-CHANNEL DESIGN CURRENT 6A +NB_CORE
VR_ON
IRF8113
B DESIGN CURRENT 18A B
+CPU_CORE0
DESIGN CURRENT 18A +CPU_CORE1
ISL6265A
DESIGN CURRENT 4A +VDDNB

SYSON
DESIGN CURRENT 5A +1.5V
RT8209BGQW SUSP
N-CHANNEL DESIGN CURRENT 1A +1.5VS
IRF8113
SUSP
DESIGN CURRENT 1A +0.75VS
APL5331KAC
VR_ON#
DESIGN CURRENT 1.5A +1.05VS
A A
APL5331KAC



Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010-08-25 Deciphered Date 2010-08-25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A6843
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401982 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, September 01, 2010 Sheet 3 of 40
5 4 3 2 1
A B C D E



Voltage Rails
Platform CPU NB VGA SB Comment
O : ON
S1G4 RS880M NA SB820M
X : OFF Danube



+5VS
1
+3VS 1
power @ : just reserve , no build
plane +2.5VS
+1.8VS [email protected] : just reserve for SB820MR1 only
+1.5VS [email protected] : just reserve for R3 only
+1.1VS [email protected] : just reserve for Connector only
+B +5VALW [email protected] : just reserve for WebCam only
+1.05VS
+3VL +3VALW +1.5V [email protected] : just reserve for Blue Tooth only
+0.75VS
+5VL +1.1VALW [email protected]: just reserve for 880MR1 only
State +VGA_CORE
+RTCVCC [email protected]: just reserve for 10/100 LAN VC version only
+VDDNB
+CPU_CORE [email protected]: just reserve for 10/100 LAN VBversion only




S0
O O O O
S1
O O O O BTO (Build-To-Order) Option Table
2 2

S3 Function Camera
O O O X
Description (C)
S5 S4/AC
O O X X Explain
S5 S4/ Battery only
O X X X BTO [email protected]

S5 S4/AC & Battery
don't exist X X X X




SMBUS Control Table
3
I2C / SMBUS ADDRESSING CPU 3
SOURCE BATT SODIMM CLK LCD
THERMAL GEN WLAN DDC
I / II
DEVICE HEX ADDRESS SENSOR ROM
EC_SMB_CK1
DDR SO-DIMM 0 A0 10100000 KB926
EC_SMB_DA1 V
DDR SO-DIMM 1 A2 10100010
EC_SMB_CK2
KB926
EC_SMB_DA2 V
I2C_CLK
RS880M
I2C_DATA V
DDC_CLK0
RS880M
DDC_DATA0
EC SM Bus1 address EC SM Bus2 address
SCL0
SB820
Device HEX Address Device HEX Address SDA0 V V
Smart Battery 16H 0001 011X b EMC1032-1 CPU 98H 1001 100X b SCL1
SB820
EC KB926E0 EC KB926E0 SDA1 V

4 4




Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010-08-25 Deciphered Date 2010-08-25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A6843
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401982 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, September 01, 2010 Sheet 4 of 40
A B C D E
A B C D E




+1.1VS

250 mil VLDT CAP. Near CPU Socket

1 1 1 1 1 1
C1 C2 C3 C4 C5 C6

10U_0805_10V6K 10U_0805_10V6K 0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J
2 2 2 2 2 2

1 1




H_CADIP[0..15] H_CADOP[0..15]
<11> H_CADIP[0..15] H_CADOP[0..15] <11>
H_CADIN[0..15] H_CADON[0..15]
<11> H_CADIN[0..15] H_CADON[0..15] <11>




+1.1VS
+1.1VS
JCPUA
C7
D1 VLDT_A0 HT LINK VLDT_B0 AE2 1 2 10U_0805_10V6K < VLDT_A & VLDT_B : HyperTransport I/O ring power >
VLDT=500mA D2 VLDT_A1 VLDT_B1 AE3
D3 VLDT_A2 VLDT_B2 AE4
D4 VLDT_A3 VLDT_B3 AE5

H_CADIP0 E3 AD1 H_CADOP0
H_CADIN0 L0_CADIN_H0 L0_CADOUT_H0 H_CADON0
E2 L0_CADIN_L0 L0_CADOUT_L0 AC1
H_CADIP1 E1 AC2 H_CADOP1
H_CADIN1 L0_CADIN_H1 L0_CADOUT_H1 H_CADON1
F1 L0_CADIN_L1 L0_CADOUT_L1 AC3
H_CADIP2 G3 AB1 H_CADOP2
H_CADIN2 L0_CADIN_H2 L0_CADOUT_H2 H_CADON2
G2 L0_CADIN_L2 L0_CADOUT_L2 AA1
H_CADIP3 G1 AA2 H_CADOP3
H_CADIN3 L0_CADIN_H3 L0_CADOUT_H3 H_CADON3
H1 L0_CADIN_L3 L0_CADOUT_L3 AA3
2 H_CADIP4 H_CADOP4 2
J1 L0_CADIN_H4 L0_CADOUT_H4 W2
H_CADIN4 K1 W3 H_CADON4
H_CADIP5 L0_CADIN_L4 L0_CADOUT_L4 H_CADOP5
L3 L0_CADIN_H5 L0_CADOUT_H5 V1
H_CADIN5 L2 U1 H_CADON5
H_CADIP6 L0_CADIN_L5 L0_CADOUT_L5 H_CADOP6
L1 L0_CADIN_H6 L0_CADOUT_H6 U2
H_CADIN6 M1 U3 H_CADON6
H_CADIP7 L0_CADIN_L6 L0_CADOUT_L6 H_CADOP7
N3 L0_CADIN_H7 L0_CADOUT_H7 T1
H_CADIN7 N2 R1 H_CADON7
H_CADIP8 L0_CADIN_L7 L0_CADOUT_L7 H_CADOP8
E5 L0_CADIN_H8 L0_CADOUT_H8 AD4
H_CADIN8 F5 AD3 H_CADON8
H_CADIP9 L0_CADIN_L8 L0_CADOUT_L8 H_CADOP9
< From NB > F3 L0_CADIN_H9 L0_CADOUT_H9 AD5 < To NB >
H_CADIN9 F4 AC5 H_CADON9
H_CADIP10 L0_CADIN_L9 L0_CADOUT_L9 H_CADOP10
G5 L0_CADIN_H10 L0_CADOUT_H10 AB4
H_CADIN10 H5 AB3 H_CADON10
H_CADIP11 L0_CADIN_L10 L0_CADOUT_L10 H_CADOP11
H3 L0_CADIN_H11 L0_CADOUT_H11 AB5
H_CADIN11 H4 AA5 H_CADON11
H_CADIP12 L0_CADIN_L11 L0_CADOUT_L11 H_CADOP12
K3 L0_CADIN_H12 L0_CADOUT_H12 Y5
H_CADIN12 K4 W5 H_CADON12
H_CADIP13 L0_CADIN_L12 L0_CADOUT_L12 H_CADOP13
L5 L0_CADIN_H13 L0_CADOUT_H13 V4
H_CADIN13 M5 V3 H_CADON13
H_CADIP14 L0_CADIN_L13 L0_CADOUT_L13 H_CADOP14
M3 L0_CADIN_H14 L0_CADOUT_H14 V5
H_CADIN14 M4 U5 H_CADON14
H_CADIP15 L0_CADIN_L14 L0_CADOUT_L14 H_CADOP15
N5 L0_CADIN_H15 L0_CADOUT_H15 T4
H_CADIN15 P5 T3 H_CADON15
L0_CADIN_L15 L0_CADOUT_L15

<11> H_CLKIP0 J3 L0_CLKIN_H0 L0_CLKOUT_H0 Y1 H_CLKOP0 <11>
<11> H_CLKIN0 J2 L0_CLKIN_L0 L0_CLKOUT_L0 W1 H_CLKON0 <11>
<11> H_CLKIP1 J5 L0_CLKIN_H1 L0_CLKOUT_H1 Y4 H_CLKOP1 <11>
<11> H_CLKIN1 K5 L0_CLKIN_L1 L0_CLKOUT_L1 Y3 H_CLKON1 <11>

<11> H_CTLIP0 N1 L0_CTLIN_H0 L0_CTLOUT_H0 R2 H_CTLOP0 <11>
<11> H_CTLIN0 P1 L0_CTLIN_L0 L0_CTLOUT_L0 R3 H_CTLON0 <11>
3 3
<11> H_CTLIP1 P3 L0_CTLIN_H1 L0_CTLOUT_H1 T5 H_CTLOP1 <11>
<11> H_CTLIN1 P4 L0_CTLIN_L1 L0_CTLOUT_L1 R5 H_CTLON1 <11>

FOX_PZ6382A-284S-41F_Champlian
[email protected]




< FAN Control Circuit : Vout = 1.6 x Vset >

+5VS

1A



2
+FAN1
C1119 JFAN +3VS
1
10U_0805_10V4Z +FAN1 1
C1120 1 1
2 2
1

10U_0805_10V4Z 2 3
2 U31 @ 3
1 8 C1121 4 R795
EN GND 1000P_0402_25V8J GND 10K_0402_5%
2 VIN GND 7 5 GND
1
3 6
2




VOUT GND ACES_85204-0300N
<28> EN_DFAN1 4 VSET GND 5
4 [email protected] 4
FAN_SPEED1 <28>
APL5607KI-TRG_SO8 2
@
C1122
0.01U_0402_25V7K
1


Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010-08-25 Deciphered Date 2010-08-25 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS,MB A6843
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401982 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, September 01, 2010 Sheet 5 of 40
A B C D E
A B C D E




+1.5V < DDR2 VREF is 0.5 ratio > < Processor DDR3 Memory Interface >
< Close to CPU >
2




R1
JCPUC
<10> DDR_B_D[63..0]
1K_0402_1% MEM:DATA
DDR_A_D[63..0] <9>
< From/To SO_DIMMB > DDR_B_D0 C11 G12 DDR_A_D0
1




+MCH_REF DDR_B_D1 MB_DATA0 MA_DATA0 DDR_A_D1
A11 MB_DATA1 MA_DATA1 F12 < From/To SO_DIMMA >
DDR_B_D2 A14 H14 DDR_A_D2
MB_DATA2 MA_DATA2
2




1 1 DDR_B_D3 B14 G14 DDR_A_D3
R2 C9 C8 DDR_B_D4 MB_DATA3 MA_DATA3 DDR_A_D4
G11 MB_DATA4 MA_DATA4 H11
DDR_B_D5 E11 H12 DDR_A_D5
1 1K_0402_1% 0.1U_0402_16V7K 1000P_0402_25V8J DDR_B_D6 MB_DATA5 MA_DATA5 DDR_A_D6 1
D12 MB_DATA6 MA_DATA6 C13
2 2 DDR_B_D7 DDR_A_D7
A13 E13
1




DDR_B_D8 MB_DATA7 MA_DATA7 DDR_A_D8
A15 MB_DATA8 MA_DATA8 H15
DDR_B_D9 A16 E15 DDR_A_D9
DDR_B_D10 MB_DATA9 MA_DATA9 DDR_A_D10
A19 MB_DATA10 MA_DATA10 E17
DDR_B_D11 A20 H17 DDR_A_D11
DDR_B_D12 MB_DATA11 MA_DATA11 DDR_A_D12