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5 4 3 2 1
D
Gilbert D
REV : A00
@ : Nopop Component
C C
B B
Dothan Schematic with Capture CIS and Function field
uFCPGA Dothan
10-04-2004
A REV: 1.0 A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Cover Sheet
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-2501
Date: Tuesday, October 05, 2004 Sheet 1 of 48
5 4 3 2 1
5 4 3 2 1
Compal confidential Block Diagram
GUARDIAN Dothan/Banias
D
EMC6N300 Clock Generator D
page 13
uFCPGA CPU CK408M
page 7,8,9 page 6
HA#(3..31)
System Bus
HD#(0..63) Fan Control
CRT CONN. 400MHz
Memory page 13
& TV-OUT BUS(DDRI)
VGA page 17
Odem-B SO-DIMM X2 LED/B
2.5V 333MHz
Board BANK 0, 1, 2, 3page 14,15
page 35
MCH-M
AGP4X
593 FC-BGA
VGA CONN.
page 10,11,12
C page 16 C
DC IN
page 37
MINI PCI Hub Link MDC
BATT IN/+2.5V
page 24
page 30 page 38
3.3V 14.318MHz AC-LINK
PCI BUS
1.5V/1.05V(+VCCP)
ICH4M
ATA100 page 39
IDSEL:AD17
LAN 421 BGA
(PIRQA/B#,GNT#2,REQ#2) 3.3V 33MHz AC97 CODEC
BCM4401 page 18,19,20,21 ATA100 STAC9750 5V/3.3V/15V
CardBus Controller page 22 page 40
page 26
B RICHO R5C841 B
page 28,29
CDROM 2.5V / 1.25V
Transformer page 25
page 41
SDIO CONN. & RJ45 LPC BUS AMP & Subwoofer
1394 CONN. Slot 0 3.3V 33MHz HDD Phone Jack
page 27 page 24
page 29 page 28 page 29 page 19
page 23
VCORE
page 42
GPIO USBPORT 0
Macallan III JUSB3 U
USBPORT 1 CHARGER
LPC to X-BUS JUSB3 D
X BUS & Super I/O 48MHz / 480Mbps USBPORT 2 page 43
page 31,32 USB2.0 Blue Tooth
LCM CONN. USBPORT 3
NEW CARD
USBPORT 4 1.2V/1.8V
page33 SST39VF080 JUSB2 U page 44
USBPORT 5
A
page 33
JUSB2 D A
Touch Pad Int.KBD
Multi-media page 33
page 33
page 25
DELL CONFIDENTIAL/PROPRIETARY
Board Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Block Diagram
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-2501
Date: Tuesday, October 05, 2004 Sheet 2 of 48
5 4 3 2 1
5 4 3 2 1
D D
PM TABLE
C
+5VRUN USB TABLE C
+3VRUN PCI TABLE
power +3VALW +3VSUS +1.8VRUN
plane
USB PORT# DESTINATION
+5VALW +5VSUS +1.5VRUN
PCI DEVICE IDSEL REQ#/GNT# PIRQ
+2.5V_MEM +1.2VRUN
+1.5VSUS +VCC_CORE 0 JUSB3 (Top)
State
+15V +VCCP
CARD BUS AD17 1 B,C,D 1 JUSB3 (Bottom)
V_1P25V_DDR_VTT
2 Blue Tooth
S0 ON ON ON
MINI PCI AD19 3 D,B 3 NEW CARD
S1 ON ON ON
LAN AD16 4 C 4 JUSB2 (Top)
S3 ON ON OFF 5 JUSB2 (Bottom)
S5 S4/AC ON OFF OFF
B B
S5 S4/AC don't exist OFF OFF OFF
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Index and Config.
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-2501
Date: Tuesday, October 05, 2004 Sheet 3 of 48
5 4 3 2 1
5 4 3 2 1
D D
+5VALW
ADAPTER PWR_SRC
+3VALW
BATTERY
C C
SUSPWROK_5V
SUSPWROK_5V
SUSPWROK_1.5V
RUNPWROK
RUNPWROK
SUS_ON
SUS_ON
+5VSUS +3VSRC +VCC_CORE +1.5VSUS +VCCP +2.5VSUSP V_1P25V_DDR_VTT
AUDIO_AVDD_ON
SUSPWROK_5V
PJP11,PJP12
PL11, PD15
RUN_ON_D
B B
(Option)
RUN_ON
RUN_ON RUN_ON
+5VHDD +5VMOD +5VRUN +15V VDDA +3VRUN V3P3LAN +3VSUS +2.5VRUN +1.5VRUN +2.5V_MEM
RUN_ON_D
RUN_ON
L25
+1.8VRUN +1.2VRUN
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
Power Rail
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-2501
Date: Tuesday, October 05, 2004 Sheet 4 of 48
5 4 3 2 1
5 4 3 2 1
ICH_SMBCLK CK_SCLK
7002
D D
ICH4M ICH_SMBDATA +3VSUS +3VRUN CK_SDATA CLK GEN.
7002
DIMM0 DIMM1
CLK_SMB
DAT_SMB +3VALW GUARDIAN
C C
24C04
Device Address
SIO DIM0 A0h
LPC47N354 SMBCLK_VGA
DIM1 A2h
Macallan III SMBDAT_VGA +5VALW VGA ICH4M-SMBus
CLK GEN. D2h
GUARDIAN 5Eh
B 24C04 A2h B
EC-SMBus VGA 58h
Battery 16h
PBAT_SMBCLK
Charger 12h
PBAT_SMBDAT +5VALW BATTERY
CHARGER
A A
DELL CONFIDENTIAL/PROPRIETARY
Compal Electronics, Inc.
Title
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
SMBUS TOPOLOGY
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD Size Document Number Rev
1.0
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT. LA-2501
Date: Tuesday, October 05, 2004 Sheet 5 of 48
5 4 3 2 1
5 4 3 2 1
D Place near each pin
1 +3VRUN CK_VDD_MAIN W>40 mil
+3VRUN CK_VDD_MAIN
G 2 3 S 1 2
2.2K_0402_5%~D
2.2K_0402_5%~D
2 1 1 1 1
1
1
L20 C42 C49 C62 C44 C53
R117
R118
BLM21PG600SN1D_0805~D
2N7002 1
10U_0805_10V4M~D
2
0.1U_0402_10V6K~D
2
0.1U_0402_10V6K~D
2
0.1U_0402_10V6K~D
2
0.1U_0402_10V6K~D
2
2
Q9
ICH_SMBDATA 3 2N7002_SOT23~D CK_SDATA
D
S
<19> ICH_SMBDATA 1 CK_SDATA <14,15>
D D
1 1 1 1
G
2
C78 C89 C69 C72
+3VRUN
0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D 0.1U_0402_10V6K~D
2 2 2 2
2
G
Q10
ICH_SMBCLK 1 3 2N7002_SOT23~D CK_SCLK
<19> ICH_SMBCLK CK_SCLK <14,15>
D
S
U7
1 VDD_REF PCICLK_F0 5
8 VDD_PCI
14 VDD_PCI PCICLK_F1 6
19 VDD_3V66
32 7 PCICLK_F2 1 R83 2 CK_33M_ICHPCI
VDD_3V66 PCICLK_F2 CK_33M_ICHPCI <18>
46 33_0402_5%~D
VDD_CPU
50
S2 S1 S0 CPU 3V66[0..4] 3V66_5/66IN W=20 mils VDD_CPU
37 VDD_48MHZ
1 0 0 66 66IN 66 Input L21 10
BLM11A601S_0603~D PCICLK0
1 0 1 100 66IN 66 Input 1 2 CLK_VDD_CORE 26 11 PCICLK1 1 R95 2 CK_33M_SIOPCI
+3VRUN VDD_CORE PCICLK1 CK_33M_SIOPCI <31>
33_0402_5%~D
1 1 0 200 66IN 66 Input 12 PCICLK2 1 R123 2 CK_33M_LANPCI
PCICLK2 CK_33M_LANPCI <26>
1 1 33_0402_5%~D
1 1 1 133 66IN 66 Input C401 C57 13
PCICLK3
0 0 0 66 66 66 Input 10U_0805_10V4M~D 0.1U_0402_16V4Z~D 16
C 2 2 PCICLK4 C
* 0 0 1 100 66 66 Input 17 PCICLK5 1 R93 2 CK_33M_CBPCI
PCICLK5 CK_33M_CBPCI <28>
27 33_0402_5%~D
GND_CORE PCICLK6 R106 2 CK_33M_MINIPCI
0 1 0 200 66 66 Input 18 1
0 1 1 133 66 66 Input
CK408 PCICLK6 33_0402_5%~D
CK_33M_MINIPCI <30>
Rev 1.1
Mid 0 0 Hi-z Hi-z Hi-z H_STP_CPU# 53 52 CK_CPU0 1 R81 2 CK_BCLK
<20,42> H_STP_CPU# CPU_STOP# CPUCLKT0 CK_BCLK <7>
33_0402_5%~D
Mid 0 1 TCLK/2 TCLK/2 TCLK/2 1 R80 2
H_STP_PCI# 34 49.9_0402_1%~D
<20> H_STP_PCI# PCI_STOP#
Mid 1 0 Reserve Reserve Reserve CLK_ENABLE# CK_CPU0# R76 2 CK_BCLK#
<42> CLK_ENABLE# 28 VTT_PWRGD# CPUCLKC0 51 1 CK_BCLK# <7>
Mid 1 1 Reserve Reserve Reserve 33_0402_5%~D
ICH_SLP_S1# 25 1 R75 2
<20> ICH_SLP_S1# PWR_DWN# 49.9_0402_1%~D
CK_VDD_MAIN CK_SCLK 30 49 CK_CPU1 1 R59 2 CK_ITP
SCLK CPUCLKT1 CK_ITP <7>
33_0402_5%~D
CK_SDATA 29 1 R58 2
SDATA 49.9_0402_1%~D
1
R569
48 CK_CPU1# 1 R54 2 CK_ITP#
CPUCLKC1 CK_ITP# <7>