Text preview for : 5991-4081EN Improving IBIS-AMI Model Accuracy_ Model-to-Model and Model-to-Lab Correlation Case Stud part of
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DesignCon 2014
Improving IBIS-AMI Model
Accuracy: Model-to-Model and
Model-to-Lab Correlation Case
Studies
Dong Yang, Broadcom Corporation
[email protected]
Yunong Gan, Broadcom Corporation
[email protected]
Vivek Telang, Broadcom Corporation
[email protected]
Magesh Valliappan, Broadcom Corporation
[email protected]
Fred S. Tang, Broadcom Corporation
[email protected]
Todd Westerhoff, SiSoft
[email protected]
Fanyi Rao, Agilent
[email protected]
Abstract
As serial data link speed continues to increase and SerDes architecture becomes more
complex, the IBIS Algorithmic Modeling Interface (IBIS-AMI) has become popular
among system developers and SerDes vendors. To accurately and quickly predict high-
speed link performance at a bit error rate (BER) of 1E-12 or lower, IBIS-AMI models
need to accurately represent chip performance and be validated at certain levels. Two
methods have been widely used to validate an IBIS-AMI model. The first method,
model-to-model correlation, is used if the SerDes vendor already has an existing in-house
models built on a certain computing platform (Matlab, C/C++, Python, etc.) and validated
to be accurate. The second method, model-to-lab correlation, compares model simulation
results to data acquired in lab testing. This paper presents case studies for both methods
and compares favorable and unfavorable factors for both methods. 10G, 11.5G and 23G
SerDes data are used as examples.
Author(s) Biography
Dr. Dong Yang is currently working with Broadcom Corporation with the high-speed
interconnect products (HSIP) team and is responsible for designing and testing high-
speed SerDes and AMI modeling. He received his Bachelor degree in Engineering from
the University of Science and Technology of China (USTC) in 2001, Master of Applied
Science (M.A.Sc), and Doctor of Philosophy (Ph.D.) in 2006 and in 2010, respectively
from McMaster University, Canada.
Yunong Gan is currently an IC Design Manager in the ING business unit at Broadcom
Corp., Irvine, California. Since 2005, he has been working on SI and Modeling of high-
speed SerDes for electrical and optical communication links. Previously, he was with
Motorola and Corning and has developed transmitter and receivers for optical
communication solutions. Yunong received his M.S. degree in Electrical Engineering
from the University of Massachusetts at Amherst in 2000. He received his B.S. degree in
Electronics Engineering from Tsinghua University, China in 1997.
Vivek Telang is a Senior Director of Engineering in the Physical Layer Products Group
in Broadcom, where he has been working since 2004. His area of expertise is the system-
level design and implementation of high-speed SerDes systems used in Broadcom 10G
and 25G backplane and front-panel products. His current responsibilities include the
design of 25G-100G SerDes systems. Vivek received his Bachelor's degree in Electrical
Engineering from the Indian Institute of Technology in Bombay, India and his M.S. and
Ph.D. from the University of Notre Dame. .
Magesh Valliappan is the manager of the SerDes architecture and design team at
Broadcom. Since joining Broadcom in 2005, his work has focused on developing
technology for delivering high-performance SerDes IP for electrical and optical
applications. Mr. Valliappan received his M.S. degree from The University of Texas at
Austin in Electrical and Computer Engineering and his B.S. degree from the Indian
Institute of Technology, Madras in Electrical Engineering.
Fred S. Tang received his Ph.D. degree in Electrical Engineering from Stanford
University in 1998. He joined Broadcom in 2008 and works on Coherent DSP
algorithms, high-speed optoelectronic device simulation in ADS, Matlab, Rsoft, and VPI,
optical link modeling and validation. From 2005 to 2008 he was with the Intel's Optical
Platform Division, where he designed X2 and SFP+LRM transceivers. From 2001 to
2005 he was with Big Bear Networks where he made key contributions to the world's
first serial 40G transponder, the X2-LRM module, and LRM stress generator. Prior to
2001, he worked in the areas of wavelength tunable VCSELs and photo detectors,
pHEMTs, high-speed optoelectronic device modeling and optimization.
Todd Westerhoff is Vice President of software products for SiSoft. He has 34 years of
simulation experience, including 17 years of signal integrity. Prior to SiSoft, Todd
managed a signal integrity group that provided high-speed design services to various
ASIC and system engineering groups within Cisco. Todd was also the SPECCTRAQuest
Product Manager for Cadence Design Systems and a signal integrity consultant to a
number of Fortune 500 companies. He has held product marketing positions at Compact
Software, Racal-Redac, FutureNet, and HHB-Systems. Todd holds a Bachelors of
Engineering degree in Electrical Engineering from the Stevens Institute of Technology in
Hoboken, New Jersey.
Fangyi Rao received his Ph.D. in Theoretical Physics from Northwestern University in
1997. He joined Agilent EEsof in 2006 and works on analog/RF and SI simulation
technologies in ADS and RFDE. From 2003 to 2006 he was with Cadence Design
Systems where he made key contributions to the company's harmonic balance technology
and perturbation analysis of nonlinear circuits. Prior to 2003, he worked in the areas of
EM simulation, nonlinear device modeling, and optimization.
1. Introduction
With increasing data rates of SerDes channels and complexity of the associated digital
equalization blocks, classic time-domain simulations with legacy IBIS and SPICE models
have slowed to the point where their usefulness is limited. Extremely long simulation
times associated with transistor level models and vendor-specific encryption increase the
effort required to develop accurate models and decrease model portability. Furthermore,
even when such models are developed, simulation throughput is limited and design
validation takes a long time. With the release of the IBIS 5.0 in 2008 [1], Algorithmic
Modeling Interface (AMI) [2] [3] has provided an Industry- standard way of simulating
high-speed serial links with advanced signal processing elements, such as analog filters,
FFE and DFE, etc. IBIS-AMI models offer orders-of-magnitude of improvement in
simulation time, while IP remains hidden and protected within a compiled executable in
binary format called from EDA tools through a standard interface. This standard interface
allows AMI models to run on any EDA tools that support IBIS-AMI. With their high
flexibility and good IP protection, AMI models have become the choice of many design
customers and SerDes vendors.
To guarantee that an AMI model can correctly predict the performance of the
corresponding chips, detailed procedures to validate accuracy of AMI models must be
used by SerDes vendors. To date, there are two methods that have been widely used to
validate IBIS-AMI models; model-to-model correlation and model-to-lab correlation.
Model-to-model correlation utilizes existing in-house models developed by the SerDes
vendors on certain platforms such as Matlab, C/C++, or Python, etc., where these models
have already been validated and are known to be accurate. The Model-to-lab method
compares simulation results with measured data acquired from Lab testing to ensure the
developed IBIS-AMI model matches behavior observed with actual SerDes channels.
This paper is organized as follows. Section 2 describes the basics of SerDes designs.
Section 3 introduces LinkEye