Text preview for : sony FJ67C -FJseries -rd1-mb-0702a-ntel.pdf part of Sony sony FJ67C -FJseries -rd1-mb-0702a-ntel Sony Notebook sony FJ67C -FJseries -rd1-mb-0702a-ntel.pdf
Back to : sony FJ67C -FJseries -rd1 | Home
1 2 3 4 5
1
Dothan
RD1 Block Diagram
478 PIN (micro FC-PGA) P3,4
A A
400/533 MHz
14w inch XGA, SXGA+
LCD UNBUFFERED
P7
Alviso DDRII 400/533 DDRII
SODIMM
915GM P10
AVOUT P9
UNBUFFERED
DDRII 400/533 DDRII
CRT P9 1257 PIN (micro FCBGA) SODIMM
P5,6,7,8 P10
DMI
B B
ICH6-M
PCI BUS Azalia Link
609 BGA(31x31mm) P11,12,13 ALC260 MDC Module
P22
P17
USB 2.0
USB 2.0
USB 2.0
Realtek
3.3V LPC,33MHZ
Mini PCI 8100CL
PATA
SATA
TI_7420B Wireless LAN
TI-TPA6011A4 P23 RJ11
10/100M
P14,15,16 P17 P19
mini-PCI 802.11a/b/g
MIC.Jack
(Intel Calexico II
Int. MIC Audio Jack INT.SPKR.
module)
C C
RJ45 P19
USB*2 Felica Camera ODD HDD
Memory Stick Pro(DUO) P21 P18 P21 P18 P18
SLOT0 1394
P16 P14
PCU
NS PC97551
P20
USB*3 CRT RJ45 LPT DVI DC-IN
TOUCH PAD INT.K/B BIOS MS LED
P18 P21 P20
Wireless SW
T/P SWITCH
D Wireless LED D
Battery LED
Port Replicator charger Power/Speep/Bat/HDD QUANTA
P22 Camera SW
COMPUTER
Size Document Number Rev
RD1 Main Board 1A
Date: Saturday, June 25, 2005 Sheet 1 of 32
1 2 3 4 5
1 2 3 4 5 6 7 8
CLK_VDDA 1
L1
2
MLB_160808-0300P-N2
VCC3 2
C960 C959 C1 C2
C4 10U/10V/X5R 0.1U_4 10U/10V/X5R 0.1U_4
33P 14.318MHz/20PF/20ppm
XIN
Y1
2
11
37
38
R584 U1
C6 1M_4 50 52 R2 33_4 14M_ICH
VDDA
VDDA
GNDA
X1 REF1 14M_ICH (12)
A 33P HCLK_CPU RP41 1 2 49.9X2 A
R585 0_4 XOUT 49 44 R_HCLK_MCH RP30 1 2 33X2 HCLK_MCH HCLK_CPU# 3 4
1
X2 CPU0 HCLK_MCH (5)
43 R_HCLK_MCH# 3 4 HCLK_MCH# HCLK_MCH RP42 1 2 49.9X2
CPU0# HCLK_MCH# (5)
HCLK_MCH# 3 4
10 41 R_HCLK_CPU RP31 1 2 33X2 HCLK_CPU
(23) -CLK_EN VTT_PWRGD#/PD CPU1 HCLK_CPU (3)
55 40 R_HCLK_CPU# 3 4 HCLK_CPU#
(12) -STP_PCI PCI_STOP#/SRC_STOP# CPU1# HCLK_CPU# (3)
(12,23) -STP_CPU 54 CPU_STOP#
CPU2_ITP/SRC7 36
(10,12) PCLK_SMB 46 SCLK CPU2#_ITP/SRC7# 35
(10,12) PDAT_SMB 47 SDATA
VCC3
R46 10K_4
CLK48_7411 R17 12.1/F_4
CK-410M CLKREQA# 33
R544 10K_4
RP43
CLK_PCIE_SATA#
(14) CLK48_7420 CLKREQB# 32 1 2 49.9X2
CLK48_USB R20 12.1/F_4 CPU_BSEL2 CLK_PCIE_SATA
(12) CLK48_USB
CPU_BSEL1
12 FSA/USB_48 ICS954227 3 4
(4,5) CPU_BSEL1 16 FSB/TEST_MODE SRC5 31
CLK_VDD R50 10K_4 CPU_BSEL0 53 30 DREFSSCLK# RP44 1 2 49.9X2
(4,5) CPUBSEL0 REF0/FSC/TEST_SEL SRC5# DREFSSCLK 3 4
MLB_160808-0300P-N2 26 R_CLK_PCIE_SATA RP34 3 4 33X2 CLK_PCIE_SATA
SRC4_SATA CLK_PCIE_SATA (11)
L2 1 2 CLK_VDD 48 27 R_CLK_PCIE_SATA# 1 2 CLK_PCIE_SATA# DREFCLK# RP45 1 2 49.9X2
VCC3 VDD_REF SRC4_SATA# CLK_PCIE_SATA# (11)
42 DREFCLK 3 4
VDD_CPU R_CLK_PCIE_ICH RP35
SRC3 24 3 4 33X2 CLK_PCIE_ICH
CLK_PCIE_ICH (12)
C7 C8 C9 C10 C11 1 25 R_CLK_PCIE_ICH# 1 2 CLK_PCIE_ICH# CLK_PCIE_ICH# RP46 1 2 49.9X2
VDD_PCI_1 SRC3# CLK_PCIE_ICH# (12)
0.1U_4 0.1U_4 0.1U_4 0.1U_4 0.1U_4 7 CLK_PCIE_ICH 3 4
VDD_PCI_2 R_CLK_PCIE_MCH RP40
SRC2 22 3 4 33X2 CLK_PCIE_MCH
CLK_PCIE_MCH (7)
21 23 R_CLK_PCIE_MCH# 1 2 CLK_PCIE_MCH# CLK_PCIE_MCH#RP47 1 2 49.9X2
VDD_SRC0 SRC2# CLK_PCIE_MCH# (7)
28 CLK_PCIE_MCH 3 4
VDD_SRC1
34 VDD_SRC2 SRC1 19
C12 C13 C14 C15 20
0.1U_4 0.1U_4 10U/10V/X5R SRC1#
0.1U_4
17 R_DREFSSCLK RP36 3 4 33X2 DREFSSCLK
27FIX/LCDCLK_T/SRC0 DREFSSCLK (5)
B 18 R_DREFSSCLK# 1 2 DREFSSCLK# B
27SS/LCDCLK_C/SRC0# DREFSSCLK# (5)
14 R_DREFCLK RP37 3 4 33X2 DREFCLK
DOT96 DREFCLK (5)
15 R_DREFCLK# 1 2 DREFCLK#
DOT96# DREFCLK# (5)
5 PCICLK3
*SEL_SRC0/PCICLK3
R40 475/F IREF 39 4 R_PCLK_7420 R42 33_4 PCLK_7420
IREF *SEL_SATA/PCICLK2 PCLK_7420 (14)
3 R_PCLK_LAN R41 33_4 PCLK_LAN
PCICLK1 PCLK_LAN (19)
PCICLK0 56 R_PCLK_MP R38 33_4 PCLK_MP
PCLK_MP (17) --> For layout change
9 R_PCLK_ICH6 R43 33_4 PCLK_ICH6
GND PCLK_ICH6 (11)
GND
GND
GND
GND
GND
*SEL_LCD(27#)/PCIF0 R_PCLK_551 R452 33_4 PCLK_551
ITP_EN/PCICLK4 8 PCLK_551 (20)
R15 10K_4
13
51
29
45
* Internal pull up to VDD
2
6
**Internal pull down to GND
R_PCLK_7420 R44 *10K_4 For layout change
PCICLK3 R4 10K_4
R44:(Pin 26,27)
1: Clock from SARA PLL
0: Clock from RC PLL
R4:(Pin 17,18)
1: SRCCLK0 pair
C 0: 17,18 pin is set by R6 C
R6:(Pin 17,18)
1: LCDCLK pair
0: 27MHZSS/27MHZSS# pair
96MHz SST Table :
S3 S2 S1 S0 Spread Type
0 0 0 0 0.8
0 0 0 1 1
ICS 954227 : Include SST
FSC FSB FSA 0 0 1 0 1.25
BSEL0 BSEL1 BSEL2 CPU SRC PCI REF USB DOT ICS 954227 Function:
0 0 1 1 1.5
Down
Pin 53 : REF1
0 0 0 266.66 100 33.33 14.318 48 96 Pin 17,18: 96MHz_SST 0 1 0 0 1.75
* 0 0 1 133.33 100 33.33 14.318 48 96 0 1 0 1 2
0 1 0 200.00 100 33.33 14.318 48 96 ITP_EN Function(Pin 8) 0 1 1 0 2.5
0 1 1 166.66 100 33.33 14.318 48 96 0 : SRC_7 Pair (Pin 35,36) 0 1 1 1 3
1 0 0 333.33 100 33.33 14.318 48 96 1 : CPU_2_ITP Pair (Pin 35,36) 1 0 0 0 +/-0.3
* 1 0 1 100.00 100 33.33 14.318 48 96 1 0 0 1 +/-0.4
D 1 1 0 400.00 100 33.33 14.318 48 96 1 0 1 0 +/-0.5 D
Center
1 1 1 RESERVE 14.318 48 96 1 0 1 1 +/-0.6
3
1 1 0 0 +/-0.8 QUANTA
IREF (Pin 39) : SOT23
1 1 0 1 +/-1.0 COMPUTER
475_1% : Sets the IREF current to 2.32mA 1 1 1 0 +/-1.25 Title
2 1 CLOCK GENERATOR
2N7002 1 1 1 1 +/-1.5
Size Document Number Rev
Custom RD1 Main Board 1A
1.This part should not contain any substances which are specified in SS-00259-1
2.Purchase ink, paint, wire rods and molding resins only from the business partners that Sony approves as Green Partners. Date: Thursday, June 30, 2005 Sheet 2 of 32
1 2 3 4 5 6 7 8
A B C D E
U2A
H_D#[0..63]
H_D#[0..63] (5)
3
H_A#[3..31]
(5) H_A#[3..31]
H_A#3 P4 A19 H_D#0
H_A#4 A3# D0# H_D#1 TDI R55 150/F_4
H_A#5
H_A#6
U4
V3
A4#
A5#
Dothan D1#
D2#
A25
A22 H_D#2
H_D#3 TMS R56 39.2/F
VCCP
R3 A6# D3# B21
H_A#7 V2 A24 H_D#4
A7# D4#
H_A#8
H_A#9
W1
T4
A8# 1 OF 3 D5# B26
A21
H_D#5
H_D#6
TCK R57 27.4/F_4
H_A#10 A9# D6# H_D#7 -TRST R58 680_4
ADDR GROUP 0
4 W2 B20 4
DATA GROUP0
H_A#11 A10# D7# H_D#8
Y4 A11# D8# C20
H_A#12 Y1 A12# D9# B24 H_D#9 Without ITP Debug Port
H_A#13 U1 D24 H_D#10
H_A#14 A13# D10# H_D#11
AA3 A14# D11# E24
H_A#15 Y3 C26 H_D#12
H_A#16 A15# D12# H_D#13
AA2 A16# D13# B23
U3 E23 H_D#14
(5) H_ADSTB#0 ADSTB0# D14#
C25 H_D#15
D15#
(5) H_REQ#0 R2 REQ0# DSTBN0# C23 H_DSTBN#0 (5)
(5) H_REQ#1 P3 REQ1# DSTBP0# C22 H_DSTBP#0 (5)
(5) H_REQ#2 T2 REQ2# DINV0# D25 H_DINV#0 (5)
(5) H_REQ#3 P1 REQ3#
(5) H_REQ#4 T1 REQ4#
H23 H_D#16
H_A#17 AF4 D16# H_D#17
A17# D17# G25
H_A#18 AC4 L23 H_D#18
H_A#19 AC7 A18# D18# H_D#19
A19# D19# M26
H_A#20 AC3 H24 H_D#20
DATA GROUP1
H_A#21 AD3 A20# D20# H_D#21
A21# D21# F25
H_A#22 AE4 H_D#22
ADDR GROUP 1
A22# D22# G24
H_A#23 AD2 J23 H_D#23
H_A#24 AB4 A23# D23# H_D#24
A24# D24# M23
H_A#25 AC6 J25 H_D#25
H_A#26 AD5 A25# D25# H_D#26
A26# D26# L26
H_A#27 AE2 N24 H_D#27
H_A#28 AD6 A27# D27# H_D#28 VCC3
A28# D28# M25
H_A#29 AF3 H26 H_D#29
H_A#30 AE1 A29# D29# H_D#30
A30# D30# N25
3 H_A#31 AF1 K25 H_D#31 VCCP -SHDN 3
A31# D31# 3VSUS
(5) H_ADSTB#1 AE5 ADSTB1# DSTBN1# K24 H_DSTBN#1 (5)
L24 R59
DSTBP1# H_DSTBP#1 (5)
3
J26 470_4
DINV1# H_DINV#1 (5)
5
Q3
R60 2 2N7002E
Y26 H_D#32 56_4 U3 4 R61 200K 2
ERROR D32# H_D#33
(5) H_ADS# N2 ADS# D33# AA24 R62 3 1 TC7SH08FU