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Inter-Office Memorandum

To Distribution Date July 7, 1977


From Jarvis Location Palo Alto


Subject OIS Processor/Peripheral Organi7ation SOD
Controller Interface Guidelines

)(ERO)( XEROX SDD ARCHIVES
1 have read and unJ.a~stood
Pages_____To, , - - - - -
Filed on: # of Pages Ref ..1 1S})})- 02/'h ,

This 'memo proposes guidelines to use when designing the interface between an OIS
processor executing the Mesa instruction set, hereafter called the emul:1ter, anc! a peripheral
device controller, hereafter callcd the controller. This memo also outlines the style of Pilot
i/o transactions.



The Controller Status Block

The processor architecture allows as many as sixteen controllers att8cheu to a single system
element. The architecture assigns each controller a block of sixteen registers in the i/o page,
virtual memory page zero. This register block, the conlroller status block, proviz1es status
information for the emulator. The controller in turn periodically polls the CSB for
commands from the emulator. For some periphc-rals, polling th,.= CSB is an inappropriate
method to initiate action. In that case, the emulator can lise the OUTPUT instruction to
initiJte action directly. The emulator reserves the first CSB, virtu:tl mcmory locations 0