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5 4 3 2 1
CPU FSB (133MHz)
ZA3 PCB STACK UP
SCH FSB (133MHz)
LAYER 1 : TOP
ZA3(11.6") Block Diagram SCH PCIE (100MHz)
SCH DA (96MHz) CLOCK GEN CK505
D LAYER 2 : GND SCH DB (100MHz)
(SLG8SP513VTR D
Intel@Atom(Silverthorne) ,ICS9LPRS365BKLFT)
LAYER 3 : IN1 SCH CLK14 (14.31818MHz)
Z520/Z530
LAYER 4 : IN2 14 x 13 mm 441 Balls WLAN CLK(100MHz)
LAYER 5 : VCC LAN CLK(100MHz)
Page 4~6
LAYER 6 : BOT CR CLK(48MHz) Page 3
FSB 400/533MHz
LVDS
(1366 x 768) PCIE-1 10/100 LAN
11.6" LED Panel
(RTL8103EL)
Page 15 Page 17
C C
PCIE-2
SDVO
RGB (1280 x 1024) WLAN/WMAX
CRT PORT CH7317A SDVO to RGB Intel@ System Controller Hub USB MODULE
Page 14 Page 14
(Poulsbo) Page 19
22 x 22 mm FCBGA 1249 Balls
DDR2 400/533MHz 1GB (Max 2GB)
DDR2 SO-DIMM IDE/PATA INTERFACE PATA TO SATA CHIP SATA
2.5"HDD&SSD
(JMH330 OR 8040)
Page 13
Page 18 Page 18
USB X 3 USB 2.0 * (port0~7)
(PORT0,1,2) HD AUDIO CODEC MIC(PINK)
B Page 20 (ALC272) Page 16 B
Page 16
Page 7~12
CCD MODULE
HP(GREEN)
(PORT3)
Page 16
Page 15
LPC
BT MODULE Int. MIC
(PORT4) Page 16
Page 21 WPCE775C/FLASH
Page 22
Audio AMP
4 IN 1 CardReader Int SPK
(G1453L)
(PORT6) Page 16
Page 16
Page 20
A 3G MODULE A
SIM Card
(PORT7) K/B Con. Touch Pad/B Con. SPI Flash
Page 19 Page 19 Page 21 Page 21 Page 22
Quanta Computer Inc.
PROJECT : ZA3
Size Document Number Rev
1A
BLOCK DIAGRAM
Date: Sunday, March 08, 2009 Sheet 1 of 34
5 4 3 2 1
5 4 3 2 1
ZA3 Power On Sequence
From AC,Battery VIN BOM naming rule
D
+5VPCU +3VPCU D
Items Function Name Description
From PWM SYS_HWPG(PCU)
1 PATA TO SATA BRIDGE 8040@ Marvell 88SE8040
From Power Button NBSWON#
2 PATA TO SATA BRIDGE 330@ Jmicron JMH330
From EC S5_ON
3 3G Module 3G@
+3V_S5
4 FAN Module FAN_PWM@ PWM FAN
+5V_S5
5
From EC RSMRST#
SUSON
6
From EC SUSON
+3VSUS +1.8VSUS +SMDDR_VREF >5ms
+SMDDR_VTERM
From PWM
HWPG_1.8V (SUS)
C C
From SCH RSTRDY#(H Level)
From SCH SLPMODE(L Level)
From SCH SLPRDY#(H Level)
>5ms
From EC MAINON Poulsbo SCH SMBUS Table
MAINON
+5V +3V +2.5V +1.8V +1.5V +1.05V
CLK GEN RAM Mini Card (WLAN/WMAX) Mini Card (3G)
From PWM HWPG_1.5V HWPG_1.05V
(SMB_DATA) / (SMB_CLK) (+3V) V V V V
From EC VRON Power Plane +3V +3V +3V +3VSUS
VRON
From PWM +VCC_CORE
MOS CKT Reserve Reserve Reserve Reserve
CPU_COREPG
HWPG
>5ms EC SMBUS Table
B From EC ECPWROK B
From SCH STPCPU# Battery CPU thermal Sensor EC EEPROM
From SCH STPCLK# EC775 SDA1 / SCL1 (+3VPCU) V
EC775 SDA2 / SCL2 (+3VPCU) V V
From SCH CPUSLP#
Power Plane +3VPCU +3V +3VPCU
From SCH DPSLP# MOS CKT X Stuff X
From SCH DPRSTP#
From SCH DPRSLPVR
From EC RSTWARN
20us
100us
From EC PLTRST#
From SCH CPU_PWRGD
A A
2ms
From SCH CPURST#
Quanta Computer Inc.
PROJECT : ZA3
Size Document Number Rev
1A
Power Sequence/ BOM Rule
Date: Sunday, March 08, 2009 Sheet 2 of 34
5 4 3 2 1
5 4 3 2 1
Clock Generator(CLK) Clock Gen I2C +3V
+1.05V_VDD
PBY160808T-301Y-N/2A/300ohm_6
+3V C19 L3 +1.05V
L2 0.1u/10V_4 PBY160808T-301Y-N/2A/300ohm_6 R28
C38 C26 C25 C36 C27 C20 C29 C39 C31 Q3 *10K_4
2
0.1u/10V_4 *2N7002E
C30 10u/10V_8 10u/10V_8 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4
10u/10V_8 3 1 SMBDT1
9,19 PDAT_SMB SMBDT1 13
D
C37 U2 D
0.1u/10V_4 9 55
C45 VDD_PCI IO_VOUT
16 VDD_48
0.1u/10V_4 23 7 SMBCK1
C47 VDD_CK_VDD_REF VDD_PLL3 SCLK SMBDT1 R39 *Short_4
4 VDD_REF SDA 6
0.1u/10V_4 CK505
C41 46 45 PCI_STOP#
VDD_SRC SRC5/PCI_STOP# T1 +3V
0.1u/10V_4 62 44 PM_STPCPU# PM_STPCPU# 9
VDD_CPU SRC5#/CPU_STOP#
+1.05V_VDD
C24 19 61
VDD_96_IO CPU0 HCLK_CPU 4
27 VDD_PLL3_IO CPU0# 60 HCLK_CPU# 4 To CPU FSB CLK
10u/10V_8 33 VDD_SRC_IO_1 R35
52 VDD_SRC_IO_3 CPU1 58 HCLK_MCH 7
43 57 To SCH FSB CLK Q4 *10K_4
VDD_SRC_IO_2 CPU1# HCLK_MCH# 7
2
56 *2N7002E
VDD_CPU_IO
SRC8/ITP 54 T7
53 3 1 SMBCK1
SRC8#/ITP# T6 9,19 PCLK_SMB SMBCK1 13
T8 8 41
PCI0/CR#_A SRC10 PECLK_MCH 8
SRC10# 42 PECLK_MCH# 8 To SCH PCIE CLK
C43 33p/50V_4 CG_XIN T9 10 PCI1/CR#_B NB_CLKREQ0#_R R11 475/F_4 NB_CLKREQ0# R36 *Short_4
SRC11/CR#_H 40 NB_CLKREQ0# 9 SCH PCIE CLKREQ
2
Y2 PCI2 11 39 CLKREQ_WLAN#_R R12 475/F_4 CLKREQ_WLAN# CLKREQ_WLAN# 19 WLAN PCIE CLKREQ
PCI2/TME SRC11#/CR#_G
14.318MHZ 12 37 Modify R39 R36
PCI3 SRC9 WLAN_PE2CLK+ 19
38 WLAN_PE2CLK- 19 To Mini Card 1 (WLAN/WMAX) footprint from
1
C SRC9# C
CG_XOUT PCI4 13 RC0402 to SHORT0402
C42 33p/50V_4 PCI4/SRC5_EN
SRC7/CR#_F 51 T4 for 0 ohm cost down
PCIF5 14 50
PCIF5/ITP_EN SRC7#/CR#_E T5 rev.c 20090301
CG_XIN 3 48
XTAL_IN SRC6 T3
To Card Reader CLK SRC6# 47 T2
CG_XOUT 2 XTAL_OUT
EMI
SRC4 34 LAN_PE1CLK+ 17
FSA 17 35 To LAN
USB_48/FSA SRC4# LAN_PE1CLK- 17
FSB 64 31
FSB/TEST/MODE SRC3/CR#_C T11
FSC R40 10K_4 32 CLKREQ_LAN#_R R14 475/F_4 CLKREQ_LAN# 17 LAN CLKREQ FSC_R C46 *33p/50V_4
R38 33_4 FSC_R SRC3#/CR#_D
9 14M_SCH 5 REF0/FSC/TESTSEL
65 VSS_BODY SRC2/SATA 28 T13
To SCH Oscillator CLK 15 29 FSA C40 *33p/50V_4
VSS_PCI SRC2#/SATA# T12
18 VSS_48
22 VSS_IO SRC1/SE1 24 DREFCLK_SS 9
26 VSS_PLL3 SRC1#/SE2 25 DREFCLK_SS# 9 To SCH Display PLLB CLK
59 VSS_CPU
30 VSS_SRC1 SRC0/DOT96 20 DREFCLK 9
36 VSS_SRC2 SRC0#/DOT96# 21 DREFCLK# 9 To SCH Display PLLA CLK
49 VSS_SRC3
1 63 VR_PWRGD_CK410
VSS_REF CKPWRGD/PWRDWN#
SLG8SP513VTR +3V
B B
SLG8SP513VTR ,ICS9LPRS365BKLFT +3V R34 10K_4 PCI2
R33 *10K_4 NB_CLKREQ0# R10 *10K_4
PCI_STOP# R16 10K_4
SLG8SP513VTR ICS9LPRS365 PM_STPCPU# R17 10K_4
(AL8SP513000) (ALPRS365000) PULL HIGH PULL DOWN CLKREQ_WLAN# R13 10K_4
+3V R32 *10K_4 PCI4
Pin 11 PCI2/TME PCI2/TME NO OVERCLOCKING (default) NORMAL RUN R31 10K_4
+3V R30 *10K_4 PCIF5 CLK GEN & PWR
Pin 13 PCI4/ PCI_4/ PIN 24/25 IS 27MHz PIN 24/25
27_Select SEL_LCDCLK# IS SRC/DOT (default) R29 10K_4
25 VR_PWRGD_CK410#
2
Q2
Pin 14 PCIF-5/ITP_EN PCIF-5/ITP_EN PIN 53/54 IS CPUITP PIN 53/54 IS SRC8 2N7002E R24 100K_4
(default) FSA R26 10K_4 1 3
+3V +3V
FSB R25 10K_4
: SLG8SP513VTR(AL8SP513000) VR_PWRGD_CK410
: ICS9LPRS365BKLFT(ALPRS365000) FSC R45 0_4
SCH_BSEL2 7
R44 0_4 CPU_BSEL2 5
A A
SEL2 SEL1 SEL0 Frequence select R43 *10K_4
FSC FSB FSA CPU SRC PCI States
R46 *10K_4 Change R43 P/N
1 0 1 100 100 33
+1.05V
from Quanta Computer Inc.
CS00002JB38 to
0 0 1 133 100 33 Default CS31002JB28 PROJECT : ZA3
rev.c 20090301 Size Document Number Rev
1A
CLOCK GEN(CK505)
Date: Sunday, March 08, 2009 Sheet 3 of 34
5 4 3 2 1
5 4 3 2 1
Silverthorne(CPU) CPU Thermal monitor(THM)
+3V
Layout Note:Routing 10:10 mils and away
U14A from noise source with ground gard
E22 C26 Q5
7 HA#3 A[3]# ADS# H_ADS# 7
2
A22 H25 2N7002E +3V
7 HA#4 A[4]# BNR# H_BNR# 7
0
ADDR GROUP
7 HA#5 D21 A[5]# BPRI# G24 H_BPRI# 7
7 HA#6 E24 A[6]# 22 2ND_MBCLK 3 1
B17 B27 +3V
7 HA#7 A[7]# DEFER# H_DEFER# 7
7 HA#8 A18 A[8]# DRDY# W28 H_DRDY# 7
B23 D29 R77 *0_4 C104
D 7 HA#9 A[9]# DBSY# H_DBSY# 7 D
7 HA#10 A16 A[10]#
E18 C28 R66 R80
7 HA#11 A[11]# BR0# H_BREQ#0 7 +3V
D15 10K_4 10K_4 0.1u/10V_4
CONTROL
7 HA#12 A[12]#
B19 H1 H_IERR#
7 HA#13 A[13]# IERR#
A20 F31 U6
7 HA#14 A[14]# INIT# H_INIT# 7
D17 Q6 H_THERMDA
7 HA#15 A[15]#
2
B15 D25 2N7002E 8 1
7 HA#16 A[16]# LOCK# H_LOCK# 7 SCLK VCC
7 HADSTB0# D19 ADSTB[0]# T55
M5 22 2ND_MBDATA 3 1 7 2 C103
RESET# H_CPURST# 7 SDA DXP
7 HREQ#0 B25 REQ[0]# RS[0]# D27 H_RS#0 7
7 HREQ#1 D23 E28 THERM_ALERT#_R 6 3 2200p/50V_4
REQ[1]# RS[1]# H_RS#1 7 ALERT# DXN
7 HREQ#2 E20 E26 R78 *0_4
REQ[2]# RS[2]# H_RS#2 7
7 HREQ#3 A24 F25 THER_OVERT# 4 5 H_THERMDC
REQ[3]# TRDY# H_TRDY# 7 OVERT# GND
7 HREQ#4 B21 REQ[4]#
E30 +3V R68 10K_4
HIT# H_HIT# 7
B5 F29 9 THERM_ALERT# R67 *0_4 G780P81U
7 HA#17 A[17]# HITM# H_HITM# 7
7 HA#18 A12 A[18]# ADDRESS: 4C
D5 F1 XDP_OBSDATA_A3
7 HA#19 A[19]# BPM[0]# T17
ADDR GROUP 1
E12 E2 XDP_OBSDATA_A2 +3V R69 10K_4
7 HA#20 A[20]# BPM[1]# T19
B9 F5 XDP_OBSDATA_A1
7 HA#21 A[21]# BPM[2]# T20
XDP_OBSDATA_A0
7 HA#22 A6
B13
A[22]# BPM[3]# D3
E4 XDP_OBSFN_A1
T18 XDP/ITP Debug
7 HA#23 A[23]# PRDY# T24
XDP_OBSFN_A0
XDP/ITP SIGNALS
7 HA#24 E14
A10
A[24]# PREQ# F7
L2 TCK_CPU
T31 Test Points
7 HA#25 A[25]# TCK
B7 N2 TDI
7 HA#26 A[26]# TDI
D13 M1 TDO
7
7
HA#27
HA#28 A8
C4
A[27]#
A[28]#
TDO
TMS P1
J4
TMS
TRST#
TMS 9 FAN(THM) +3V
7 HA#29 A[29]# TRST# TRST# 9
7 HA#30 A14 A[30]# RSVD14 G26
C
7 HA#31 B11 A[31]#