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ZZZ2




X76

Part Number = X76264BOL81
1 1
[email protected]



ZZZ




Compal Confidential
X76

Part Number = X76264BOL82
[email protected]



ZZZ3




X76

Part Number = X76264BOL55
[email protected]
2 2



ZZZ5
P7YE5/S5 Schematics Document
X76

Part Number = X76264BOL60
AMD Sabine
[email protected]



ZZZ4
APU Llano / Hudson M2 / Vancouver Whistler_Seymour
X76
DIS only / UMA only / PX Muxless with BACO
Part Number = X76264BOL61
[email protected]


3 3
ZZZ6




X76
ZZZ1
Part Number = X76264BOL62
[email protected] 2011-02-18
PCB
Part Number = DA80000NI00
LA-6991P REV: 0.2


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Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/12/30 Deciphered Date 2012/01/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A6991
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BN
Date: Thursday, February 24, 2011 Sheet 1 of 50
A B C D E
A B C D E




Compal Confidential

1
Model Name : P5WS5 VRAM 1G/2G
64M16/128M16 x 8
page 18, 19
Sabine 1


DDR3
Thermal Sensor ATI GFX x 16 Gen2
ADM1032 Vancuver Whistler/ Seymour
page 14
uFCBGA-962 GFX x 4 (Group 1~4)
AMD FS1 APU Memory BUS(DDR3)
Page 13~17 204pin DDRIII-SO-DIMM X2
APU HDMI Dual Channel
VGA VGA VGA (UMA / Muxless) Llano BANK 0, 1, 2, 3 Page 11,12
1.5V DDRIII 800~1600MHz
HDMI LVDS(eDP) CRT DP x1 (DP0 TXP/N0)
uPGA-722 Package
HDMI Conn.
page 23
DP x2 Page 6~10
LVDS LVDS (DP0 TXP/N 0~1)
LVDS Conn. Translator P_GPP x 3 DP x 4
page 21
Reserve eDP GEN2 (DP1 TXP/N 0~4) UMI
2
page 22
USB20 USB20/B USB30/B CMOS Bluetooth Mini Mini 2
UAM eDP
M/B*1 *2 *1 Camera Conn.
Card 1 Card 2
page 34 page 35 page 35 page 22 page 35 page 33 page 33

CRT Conn. FCH CRT (VGA DAC) Port 0 Port 1 Port 3 Port5 FSD0 Port 8 Port 9
page 24 FCH USB
Port 2
3.3V 48MHz

GPP3 GPP2 GPP1 GPP0
Hudson-M2/M3
HD Audio 3.3V 24.576MHz/48Mhz
uFCBGA-656
Card Reader MINI Card 2 MINI Card 1 LAN(GbE) S-ATA Gen2
RT5138 Option WLAN AR8151 Page 25~29
page 33 page 33 page 33 page 31
GPP x 2 LPC BUS port 0 port 1 port 2
GEN2
SATA HDD1 SATA HDD1 ODD HDA Codec
RJ45
3
page 32 Conn. Conn. Conn. ALC271X page 3

page 30 page 30 page 30 38

LED
page 37 ENE KB930/9012
page 36
RTC CKT.
External board USB30 USB30
page 25
On SUB/B On M/B Touch Pad Int.KBD
GLAN - LAN/B page 35 page 34 page 37
page 37 page 37
Power On/Off CKT.
page 37
LID SW - Power/B EC I/O Buffer
page 37
Fan Control
page 30
USB20/B
BIOS ROM
DC/DC -USB20 x2 page 35
4 4

Interface CKT. SYS BIOS (2M)
page 39 page 27
USB30/B
Power Circuit -USB20 x1+ USB30 x1 EC BIOS (128K)
page 40~48 page 35 page 37
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/12/30 Deciphered Date 2012/01/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A6991
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BN
Date: Thursday, February 24, 2011 Sheet 2 of 50
A B C D E
5 4 3 2 1




CLOCK DISTRIBUTION DISPLAY DISTRIBUTION
: LVDS PATH
, : eDP PATH
: APU HDMI PATH
LVDS CONN
B_SODIMM




D A_SODIMM D
: VGA HDMI PATH
TXOUT[0:2]+/- TXOUT[1:2]+/-
TXCLK+/- I2CC_SCL/DA
TZOUT[0:2]+/-
TZCLK+/-
I2CC_SCL/DA TXOUT[1:2]+/-
AMD R
I2CC_SCL/DA
TXOUT[0:2]+/- TZOUT[0:2]+/-
ATI VGA TXCLK+/- TZCLK+/-
I2CC_SCL/DA
MEM_MB_CLK7_P/N
MEM_MB_CLK1_P/N




MEM_MA_CLK7_P/N
MEM_MA_CLK1_P/N
1066~1600MHz




1066~1600MHz




Whistler/Seymour/Granville

APU_TXOUT[0:2]+/-
C
APU_TXOUT[1:2]+/-
R R
APU_TXOUT_CLK+/-
APU_TZOUT[0:2]+/- APU_LVDS_CLK/DATA
CLK_PEG_VGAP/N
APU_TZOUT_CLK+/-
100MHz APU_LVDS_CLK/DATA
Place near
the pin
C
APU_DISP_CLKP/N
C
AMD 100MHz AMD LVDS_OUT C


RTD2132 DP0_TXP/N[0:1]_R VGA_TXOUT[1:2]+/-
CPU FS1 SOCKET
FCH DP_IN
DP0_AUXP/N_R VGA_LCD_CLK/DATA
APU_CLKP/N Hudson-M2/M3 VGA_TXOUT[0:2]+/- VGA_TZOUT[0:2]+/-
VGA_TXCLK+/- VGA_TZCLK+/-
100MHz Internal CLK GEN R
VGA_LCD_CLK/DATA
Place near
the pin

DP0_AUX GPP_CLK
100MHz

LVDS Transtator 32.768KHz 25MHz
R
C


DP0_TXP/N[0:1]
DP0_AUXP/N

B B
GPP4 GPP3 GPP2 GPP1 GPP0 DP0 DPE DPF
R
USB30 M/B USB30 SUS/B WLAN WLAN GbE LAN APU VGA
OPT PCI Socket Mini PCI Socket PCIE_GFX[0:4] C PCIE_GFX[0:15]
DP1 PCIE_GFX[5:15] C DAC1 DPA

25MHz
GPP5

CardReader
FCH

R R
R R
A A


CRT CONN HDMI CONN


Security Classification Compal Secret Data
Issued Date 2010/12/30 Deciphered Date 2012/01/01 Title
SCHEMATIC MB A6991
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019BN A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 24, 2011 Sheet 3 of 50
5 4 3 2 1
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Voltage Rails PROJECT ID Table
SIGNAL Board ID PCB Revision
Power Plane Description S1 S3 S5 STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
0
VIN Adapter power supply (19V) N/A N/A N/A Full ON HIGH HIGH HIGH HIGH ON ON ON ON 1
B+ AC or battery power rail for power circuit. N/A N/A N/A 2
S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
+CPU_CORE Core voltage for CPU ON OFF OFF 3
1
+CPU_CORE_1 Core voltage for CPU (0.7-1.2V) ON OFF OFF S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF 4 1

+CPU_CORE_NB Voltage for On-die VGA of APU ON OFF OFF 5
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
+VGA_CORE 0.95-1.2V switched power rail ON OFF OFF 6
+0.75VS 0.75V switched power rail for DDR terminator ON ON OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF 7
+1.0VSG 1.0V switched power rail for VGA ON OFF OFF
+1.1ALW 1.1V switched power rail for FCH ON ON ON* Board ID / SKU ID Table for AD channel
+1.1VS 1.1V switched power rail for FCH ON OFF OFF Vcc 3.3V +/- 5%
+1.2VS 1.2V switched power rail for APU ON OFF OFF Ra/Rc/Re 100K +/- 5% BOARD ID Table
+1.5V 1.5V power rail for CPU VDDIO and DDR ON ON OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max Board ID PCB Revision
+1.5VS 1.5V switched power rail ON OFF OFF 0 0 0 V 0 V 0 V 0
+1.8VSG 1.8V switched power rail ON OFF OFF 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V 1 0.1(EVT)
+2.5VS 2.5V for CPU_VDDA ON OFF OFF 2 18K +/- 5% 0.436 V 0.503 V 0.538 V 2 0.2(DVT)
+3VALW 3.3V always on power rail ON ON ON* 3 33K +/- 5% 0.712 V 0.819 V 0.875 V 3
+3V_LAN 3.3V power rail for LAN ON ON ON 4 56K +/- 5% 1.036 V 1.185 V 1.264 V 4
+3VS 3.3V switched power rail ON OFF OFF 5 100K +/- 5% 1.453 V 1.650 V 1.759 V 5
+5VALW 5V always on power rail ON ON ON* 6 200K +/- 5% 1.935 V 2.200 V 2.341 V 6
2
+5VS 5V switched power rail ON OFF OFF 7 NC 2.500 V 3.300 V 3.300 V 7 2

+VSB VSB always on power rail ON ON ON*
+RTCVCC RTC power ON ON ON
BTO Option Table BOM Config
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
BOM Structure BTO Item EVT
[email protected] Display from UMA (PX4.0 or UMA only)
UMA only:
[email protected] Have VGA chip (Discrete only or PX4.0)
[email protected], [email protected], [email protected], [email protected], [email protected], [email protected], [email protected]
[email protected] Display from VGA (Discrete only)
[email protected] Use Seymour (Discrete only and PX4.0) DISO only:
[email protected] Use Whistler (Discrete only and PX4.0) [email protected], [email protected], [email protected], [email protected] or [email protected], [email protected], [email protected](With [email protected]), [email protected], [email protected],
[email protected] Use Granville (Discrete only and PX4.0) [email protected], [email protected], [email protected]
[email protected] Use Vancouver VGA (Discrete only and PX4.0) PX
[email protected] Use translator RTD2136S [email protected], [email protected], [email protected], [email protected] or [email protected], [email protected], [email protected](With [email protected]), [email protected], [email protected], [email protected],
[email protected] Use translator ANX3110 [email protected], [email protected], [email protected], [email protected], [email protected]
External PCI Devices
[email protected] Use Hudson-M2
Device IDSEL# REQ#/GNT# Interrupts [email protected] Use Hudson-M3
[email protected] Use KB930
3 3
[email protected] Use KB9012
[email protected] Use VRAM channel A
[email protected] PX4.0
[email protected] Use BACO
[email protected] No use BACO
[email protected] UMA LVDS path
EC SM Bus1 address EC SM Bus2 address
[email protected] UMA eDP path
Device Address HEX Device Address HEX [email protected] VGA LVDS path
Smart Battery 0001 011X b 16H SB-TSI 1001 100X b 98H [email protected] VGA eDP path
GMT G781-1 (GPU) 1001 101X b 9AH [email protected] eDP path
CAT24C64WI (RTD2136S) 1010 100X b A8H [email protected] ACER
VGA-TSI 1000 001X b 82H [email protected] PB and GW
[email protected] No Use Granville


FCH FCH
4 SM Bus 0 address SM Bus 1 address 4


Device Address HEX Device Address HEX
DDR DIMM1 1001 000Xb 90
DDR DIMM2 1001 010Xb 94
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/12/30 Deciphered Date 2012/01/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC MB A6991
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BN
Date: Thursday, February 24, 2011 Sheet 4 of 50
A B C D E
5 4 3 2 1




AMD APU FS1
BATTERY BATT+ PU3 PU13
12.6V CHARGER ISL6267HRZ-T +CPU_CORE +CPU_CORE 0.7~1.475V VDD CORE 54A
ISL6251AHAZ-T +CPU_CORE_NB +CPU_CORE_NB 0.7~1.475V VDDNB 27.5A
+2.5VS +2.5VS +2.5VS VDDA 500mA
+1.5V
+1.5V +1.5V VDDIO 4.6A
PU6
AC ADAPTOR VIN +1.2VS +1.2VS VDDR 6.7A
D G5603RU1U PU9 D
19V 90W
APL5508
RAM DDRIII SODIMMX2
PU10 +1.2VS +1.5V VDD_MEM 4A
G5603RU1U
B+ +0.75VS VTT_MEM 0.5A
PU2 +0.75VS +0.75VS
UP7711U8
VGA ATI
Whistler/Seymour/Granville
PU11 +VGA_CORE +VGA_CORE
TPS51218DSCR 0.85~1.1V VDDC 47A

+VDDCI 0.9~1.0V VDDCI 4.6A

DPLL_VDDC: 125 mA
PU12 PU8 +1.0VSG +1.0VSG SPV10: 120 mA
G5603RU1U +VDDCI G9731G11U +1.0VSG PCIE_VDDC: 2000 mA
DP[A:E]_VDD10: 680 mA
VRAM 512/1GB/2GB
U34 +1.5VSG +1.5VSG
+1.5VSG VDDR1: 3400 mA 64M / 128Mx16 * 4 / 8
AO4430L
PU5 +1.1VALW
G5603RU1U PLL_PVDD: 75 mA +1.5VSG 2.4 A
TSVDD: 20 mA
AVDD: 70 mA
C VDD1DI: 100 mA C
VDD2DI: 50 mA
A2VDDQ: 1.5 mA
PU4 +3VALW
PU7 +1.8VSG +1.8VSG VDD_CT: 110 mA
RT8205EGQW U33 +1.8VSG VDDR4: 170 mA
+5VALW SY8033BDBC
SI4800 PCIE_PVDD: 40 mA
MPV18: 150 mA