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A B C D E F G H

P162, NV34, 8Mx16DDR, 128bit, 128MB, DVI, TV OUT, VGA

1
Page Overview P162-A00 History: 1

1-Added P162 specific features:
1 Overview - SW PS,TMDS LinkA, Backdrive, new slim VGA, Fan Cntl.
- Added Current sharing, TMDS IO and PLL linear regulators.
2 AGP Interface 2-Added TH parts in PS section as ALT.
3-Added SST serial support.
3 NV34 Frame Buffer 4-Changed AGP_PLL_VDD, FB_PLLVDD, DAC_A/B_VDD and PLL_VDD to A3V3.
5-Added 10 caps as part of P160 sync up.
4 Frame Buffer 0..31 6-Added PU resitors on Jtag TMS and TDI
7-Incorporated recommendations from PS Vendor.
5 Frame Buffer 32..63 8-Added extra X elements near connectors to bridge CGND and GND cut.
9-Added an option to use a single dual FET for low end bd.
6 Frame Buffer 64..95 10-Fixed error on 6529 power good and current supplement.
11-Changed C302 to 0603 (too big pkg for .1uf in 0805)
2 7 Frame Buffer 96..127 12-Deleted C296 and C293 (shared them with C313, C324)
2

13-Changed C329 and C324 to 0603 pkg.
8 DAC A,B, DAC B MUX, PLL, Video OUT 14-Removed alternate Semtech SW (could not route).

9 DAC A,B RGB filter Changes after the design review:
1-Remove C301 and R137-left over from Semtech PS circuit.
2-Remove sync buffer bypass resistors.
10 Power Supply A3V3, FBVDD/FBVDDQ, Mechanicals. 3-Remove R122 and R123 from Intersil power rails.
4-Add snubber circuit for NVVDD PS.
11 BIOS and Strapping 5-Add PD res on TP_XTALOUTBUF to terminate the signal.
6-Fan controler PU to 3V3 from A3V3.
12 DVO,GPIOs and Xtal. 7-Cleaned up Unnamed nets.
13 TMDS LinkA and its power supplies, Backdrive. ============================

14 NVVDD SW. 8-Split CGND into 2 nets (added CGND1 to J6.25 and J2. 16).
9-Added PD resistor on FAN_ON.
3 15 Current Supplement and Fan control. 10-Added 8 caps for DQS/DQM routings that break plane reference.
3

16 Net Rules.
X-RELEASE.

P160 HISTORY: P162-A01 History:
Merged net IFPBIOVDD with IFPAIOVDD.
Merged Q4 and Q5 into one package.
X00 INITIAL VERSION
Implemented TV signal return scheme thru zero Ohm resistors.
X01 Cleaned up schematics - changes from initial design review meeting

X02 Imported board file #65 and synchronized with latest version of schematics.

X03 Nov 18/02 - Replaced LB502 with an 805 bead, changed PLLVDD rail to 3V3
P162-A02 History:
4 instead of A3V3, and removed AGPVDDQ deoupling caps C130, C257, and C570. The main changes for this revision is to improve routing for DAC B and 4
add 100ps inter-pair skew to pass EMC as modeled on A01 board. See 149- document for detail.
X04 Nov 21/02 - C75 is changed to decouple 3V3 to GND.

X05 Nov 22/02 - VIP interface rail changed to 3V3 instead of A3V3 due to
short between VIPVDDQ and VDD33.
P162-A03 History:
X06 Nov 25/02 - FRWR_VAUXP rail changed to 3V3. Merged CGND and GND to become GND net to pass EMI at 16x12. This modificaiton was tested on P162-A02

X07 Nov 26/02 - Changed DACB_LOAD_TEST GPIO assignment for NV34.

X08 Dec 02/02 - AGP_PLL_VDD and FB_DLLVDD are supplied from A3V3 rail.

5 5

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A B C D E F G H
A B C D E F G H

AGP BUS NET_SPACING_TYPE
NV18/NV3X AGP SECTION AND AGP CONNECTOR NV_VREF 12MIL_TRACE 10MIL OUT
AGPST0 15MIL
OUT
PCIAD<31..0> 20MIL
OUT
AGP_VREFGC 12MIL_TRACE 10MIL OUT
AGPST1 15MIL
OUT
PCICBE<3..0> 20MIL
OUT
AGP_VREFCG 12MIL_TRACE 10MIL OUT
AGPST2 15MIL
OUT
AGPSTOP 10MIL OUT
PCIDEVSEL* 10MIL
OUT
AGPMBDET 10MIL OUT
PCIPAR 10MIL
OUT
PCICLK 20MIL
OUT
SBA<7..0> 20MIL BI
PCIRST* 10MIL
OUT
SBSTB 25MIL PCIINTA* 10MIL
OUT OUT
SBSTB* 25MIL PCIINTB* 10MIL PCIREQ* 10MIL
OUT OUT OUT
AGPSTB0 25MIL PCIGNT* 10MIL
OUT OUT
AGPSTB0* 25MIL AGPRBF* 10MIL
OUT OUT
AGPSTB1 25MIL AGPWBF* 10MIL PCIFRAME* 10MIL
OUT OUT OUT
1 AGPSTB1* 25MIL
OUT
AGPDBI_HI 20MIL
OUT
PCIIRDY* 10MIL
OUT 1
AGPDBI_LO 20MIL PCITRDY* 10MIL
OUT OUT
NO STUFF U8 PCISTOP* 10MIL
OUT
12V NV34_DKTP_V_A1
CN501 BGA701
CON_AGP PCIAD<31..0> COMMONCHG

AGP2x4x AGP8x AGP2x4x 1/11 PCI/AGP
AD11 AGPVDDQ
AGPVDDQ
TP_P12V A1
+12V AD<0>
A65
B65
0
1
0
1
AJ28
AK28
PCIAD<0> AGPVDDQ
AE11
AD14
AGPVDDQ Decoupling
C147 C148 AD<1> PCIAD<1> AGPVDDQ
AD<2> A63 2 2 AH27 PCIAD<2> AGPVDDQ AE14
.022UF .047UF B63 3 3 AK27 AD17 C501 C502 C504 C266 C267
25V 16V AD<3> PCIAD<3> AGPVDDQ .022UF .022UF .022UF .022UF .1UF
AD<4> A62 4 4 AJ27 PCIAD<4>
10% 10%
B62 5 5 AH26 AE17 25V 25V 25V 25V 10V 10%
X7R X7R AD<5> PCIAD<5> AGPVDDQ 10% 10% 10% 10% X7R
3V3 0402 0402
AD<6> A60 6 6 AJ26 PCIAD<6> AGPVDDQ AD20 X7R X7R X7R X7R 0402
COMMON COMMON
AD<7> B60 7 7 AH25 PCIAD<7> AGPVDDQ AE20 0402 0402 0402 0402 COMMON
B57 8 Split plane decoupling 8 AH23 PCIAD<8> AD23 COMMON COMMON COMMON COMMON
AD<8> A56 AJ23 AGPVDDQ AE23
GND GND AD<9> 9 place top, near AGP connector 9 PCIAD<9> AGPVDDQ
C75 5V B56 10 10 AH22
.022UF AD<10> AGPVDDQ PCIAD<10>
A54 11 11 AJ22 PCIAD<11>
25V 10% AD<11> B54 C102 AJ21
12 12 PCIAD<12>
X7R AD<12> A53 .022UF AK21 L11
0402 13 13 PCIAD<13>
B2
AD<13> B53 25V AH20 VDD N11
COMMON
+5V AD<14> 14
10% 14 PCIAD<14> VDD NVVDD
B3 A51 15 X7R 15 AJ20 PCIAD<15> P11
+5V AD<15> VDD
C35
4.7UF
C34
.022UF AD<16>
A39
B38
16
17
3V3 0402
COMMON
16
17
AG26
AE24
PCIAD<16> VDD
U11
V11
NVVDD Decoupling
6.3V 25V AD<17> C516 PCIAD<17> VDD
GND A38 18 18 AG25 PCIAD<18> Y11
10% 10% AD<18> B36 .022UF AG24 VDD L13 C520 C517 C509 C512 C524
X5R X7R 19 19 PCIAD<19>
AD<19> A36 25V AF24
VDD
Y13 100PF 470PF 1000PF 4700PF 1UF
0805 0402 20