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ZZZ4 LS-4764P



PCB
1 1
DA80000CG00




Compal Confidential
2
KIU10 LS-4764P 2




Schematics Document

Menlow-Silverthorne with Poulsbo
3 3




REV:1.0
2008/12/02




4 4




Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/07/15 Deciphered Date 2011/07/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom KIU10 LS-4764P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Sheet 1 of 20
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A B C D E




Compal Confidential CPU-Silverthrone CPU Regulator +1.8V
1.33G/1.6G Clock Gen.
Model Name : KIU10
9UMS9610
File Name : LS-4764P H_A#(3..35)
FSB
H_D#(0..63) 533MHz
+1.05VS
1 1




DDR2-533 DDR2 64MX16X8pcs
K4T1G164QD
SCH- Poulsbo SingleChannel
+0.9VS


+1.5VS



1 SDIO I/F LVDS I/F SDVO I/F PCIE PCIE LPC BUS ATA100 USB2.0 AZALIA

2 2


200Pin Golden-Finger


PCIE PCIE LPC BUS ATA100 USB2.0 AZALIA Audio Jack
LVDS I/F SDVO I/F Audio Codec
ALC 269 Mono-Speaker
Port 5
LVDS SDVO to HDMI LAN RTL8102EL WLAN/WiMAX EC Camera DCIN/CHARGER
Connector Sil1392 ENE KB926
page33
Port 0,1,3
USB Conn X 3
3 3
SPI
BIOS
HDMI Port 6 USB Card Reader BATT Conn/OTP
Connector TP PS/2 RTS5158
SD/MMC/MS
+3VALW
Int.KBD Port 4 SIM
3G-Module
LS-4764P Connector
+5VALW
Main-Board Port 2 BlueTooth


Port 7
4
SATA HDD TV Turner 4


GL831

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/07/15 Deciphered Date 2011/07/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom KIU10 LS-4764P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, December 02, 2008 Sheet 2 of 20
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A




Voltage Rails O MEANS ON X MEANS OFF SKU ID Table
Vcc 3.3V +/- 5%
Ra 100K +/- 5%
+5VS Board ID Rb V AD_BID min V AD_BID typ V AD_BID max
power
+3VS
plane * 0 0 0 V 0 V 0 V
+1.8VS 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+VBAT
+1.5VS 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+5VALW +1.8V
+CPU_CORE CLOCK 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+3VALW +0.9V
+VCCP 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
State
5 100K +/- 5% 1.453 V 1.650 V 1.759 V
6 200K +/- 5% 1.935 V 2.200 V 2.341 V
7 NC 2.500 V 3.300 V 3.300 V


S0 O O O O O SKU ID MB ID(H) MB ID(L)
0
S3 * 1 IEL10
O O O X X 2 IDL11 IDL01
S5 S4/AC
3 HDL10 HDL00 TBD
O O X X X 4 HDL20
S5 S4/ Battery only
5 IDL12 HDL30
O X X X X 6
S5 S4/AC & Battery
7
don't exist X X X X X
MB ID
H 15"
L 14"

O MEANS ON S3 : STR
X MEANS OFF S4 : STD
S5 : SOFT OFF
1
BOM Structure USB PORT LIST 1




MARK FUNCTION
@ NC FOR ALL PORT DEVICE
0 2A POWER USB
1 USB (right)
2 BT
3 USB(lEFT)
Address
4 3G, GPS
5 Camera
6 Card reader
EC SM Bus1 address EC SM Bus2 address 7 TV Turner
Device Address Device Address
ADM1032 1001 100X b
EEPROM(24C16/02) 1010 000X b




Poulsbo SM Bus address
Device Address
Clock Generator
( ICS954226) 1101 001Xb




Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/07/15 Deciphered Date 2011/07/15 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom KIU10 LS-4764P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, December 02, 2008 Sheet 3 of 20
A
5 4 3 2 1




Silverthrone Host Data Interface Silverthrone Host Data Interface
U2 +1.05VS_C6
6 H_D#[0..15] H_D#[32..47] 6
U2B
H_D#0 Y27 AE8 H_D#32
H_D#1 D[0]# D[32]# H_D#33
AH27 D[1]# D[33]# AD7
H_D#2 Y31 AH15 H_D#34 Intel CRB1_5 +1.05VS_C6
H_D#3 D[2]# D[34]# H_D#35
AC30 AF9 R1 1 2 H_PBE#
D[3]# D[35]#




DATA GRP 0
DATA GRP 0
H_D#4 AE30 AH9 H_D#36 120_0402_5%
H_D#5 D[4]# D[36]# H_D#37
AF29 D[5]# D[37]# AE10 [email protected] R2 1 2 H_A20M#
H_D#6 AA26 AJ16 H_D#38 SA00002M42L 1K_0402_1% H_INIT# 1 2 1K_0402_1%
H_D#7 D[6]# D[38]# H_D#39
AB31 AF13 R4 1 2 H_IGNNE# R3




DATA GRP 2
D H_D#8 D[7]# D[39]# H_D#40 1K_0402_5% D
W30 D[8]# D[40]# AF7
H_D#9 AC28 AF15 H_D#41
H_D#10 D[9]# D[41]# H_D#42
AD31 D[10]# D[42]# AH13
H_D#11 AF27 AJ14 H_D#43
H_D#12 D[11]# D[43]# H_D#44 6 H_A#[3..16]
AD27 AJ12 U2A
H_D#13 D[12]# D[44]# H_D#45 H_A#3 H_ADS#
AG28 D[13]# D[45]# AH7 E22 A[3]# ADS# C26 H_ADS# 6
H_D#14 AB25 AJ8 H_D#46 H_A#4 A22 H25 H_BNR#
D[14]# D[46]# A[4]# BNR# H_BNR# 6




0
ADDR GROUP
H_D#15 AC26 AJ10 H_D#47 H_A#5 D21 G24 H_BPRI#
H_DSTBN#0 D[15]# D[47]# H_DSTBN#2 H_A#6 A[5]# BPRI# H_BPRI# 6
6 H_DSTBN#0 AA28 DSTBN[0]# DSTBN[2]# AH11 H_DSTBN#2 6 E24 A[6]#
H_DSTBP#0 AA30 AF11 H_DSTBP#2 H_A#7 B17 B27 H_DEFER#
6 H_DSTBP#0 H_DINV#0 DSTBP[0]# DSTBP[2]# H_DINV#2 H_DSTBP#2 6 H_A#8 A[7]# DEFER# H_DRDY# H_DEFER# 6
6 H_DINV#0 AE28 DINV[0]# DINV[2]# AE12 H_DINV#2 6 A18 A[8]# DRDY# W28 H_DRDY# 6
H_A#9 B23 D29 H_DBSY#
6 H_D#[16..31] H_D#[48..63] 6 H_A#10 A[9]# DBSY# H_DBSY# 6
A16 A[10]#
H_D#16 AE24 AH5 H_D#48 H_A#11 E18 C28 H_BR0#
H_D#17 D[16]# D[48]# H_D#49 H_A#12 A[11]# BR0# H_BR0# 6
AC24 AB5 D15 R5




CONTROL
H_D#18 D[17]# D[49]# H_D#50 H_A#13 A[12]# H_IERR#
AJ20 AJ6 B19 H1 2 1
H_D#19 D[18]# D[50]# H_D#51 H_A#14 A[13]# IERR# H_INIT# 56_0402_5% +1.05VS
AE20 D[19]# D[51]# Y1 A20 A[14]# INIT# F31 H_INIT# 6,13
H_D#20 AJ22 AF5 H_D#52 H_A#15 D17
D[20]# D[52]# A[15]#



DATA GRP 1
DATA GRP 1
H_D#21 AF25 AG4 H_D#53 H_A#16 B15 D25 H_LOCK#
H_D#22 D[21]# D[53]# H_D#54 H_ADSTB#0 A[16]# LOCK# H_LOCK# 6
AH25 AF3 6 H_ADSTB#0 D19
H_D#23 D[22]# D[54]# H_D#55 ADSTB[0]# H_RESET#
AH23 AC6 M5 H_RESET# 6
D[23]# D[55]# RESET#


DATA GRP 3
H_D#24 AH19 AE6 H_D#56 H_REQ#0 B25 D27 H_RS#0
H_D#25 D[24]# D[56]# H_D#57 6 H_REQ#0 H_REQ#1 REQ[0]# RS[0]# H_RS#1 H_RS#0 6
AF23 D[25]# D[57]# AE4 6 H_REQ#1 D23 REQ[1]# RS[1]# E28 H_RS#1 6
H_D#26 AE18 W4 H_D#58 H_REQ#2 E20 E26 H_RS#2
H_D#27 D[26]# D[58]# H_D#59 6 H_REQ#2 H_REQ#3 REQ[2]# RS[2]# H_TRDY# H_RS#2 6
AH17 AC2 6 H_REQ#3 A24 F25 H_TRDY# 6
H_D#28 D[27]# D[59]# H_D#60 H_REQ#4 REQ[3]# TRDY#
AD19 D[28]# D[60]# AE2 6 H_REQ#4 B21 REQ[4]#
H_D#29 AJ24 AD1 H_D#61 E30 H_HIT#
H_D#30 D[29]# D[61]# H_D#62 6 H_A#[17..31] H_A#17 HIT# H_HITM# H_HIT# 6
AJ18 AA2 B5 F29 H_HITM# 6
H_D#31 D[30]# D[62]# H_D#63 H_A#18 A[17]# HITM#
AF19 D[31]# D[63]# AC4 A12 A[18]#
H_DSTBN#1 AF21 AB1 H_DSTBN#3 H_A#19 D5 F1 XDP_BPM#0
6 H_DSTBN#1 DSTBN[1]# DSTBN[3]# H_DSTBN#3 6 A[19]# BPM[0]#




ADDR GROUP 1
ADDR GROUP 1
H_DSTBP#1 AH21 AA4 H_DSTBP#3 H_A#20 E12 E2 XDP_BPM#1
6 H_DSTBP#1 H_DINV#1 DSTBP[1]# DSTBP[3]# H_DINV#3 H_DSTBP#3 6 H_A#21 A[20]# BPM[1]# XDP_BPM#2
6 H_DINV#1 AE22 Y5 H_DINV#3 6 B9 F5
C DINV[1]# DINV[3]# H_A#22 A[21]# BPM[2]# XDP_BPM#3 C
A6 A[22]# BPM[3]# D3
+CPU_GTLREF AJ26 AE14 COMP0 R11 1 2 27.4_0402_1% H_A#23 B13 E4 XDP_BPM#4
GTLREF COMP[0] COMP1 R15 54.9_0402_1% H_A#24 A[23]# PRDY# XDP_BPM#5
MISC COMP[1]
AD13 1 2 E14
A[24]# PREQ#
F7




XDP/ITP SIGNALS
E16 COMP2 R13 1 2 27.4_0402_1% H_A#25 A10 L2 XDP_TCK
COMP[2] COMP3 R14 54.9_0402_1% H_A#26 A[25]# TCK XDP_TDI
COMP[3] F15 1 2 B7 A[26]# TDI N2
P31 H_A#27 D13 M1 XDP_TDO R12
TEST1 H_DPRSTP# H_A#28 A[27]# TDO XDP_TMS
T31 TEST2 DPRSTP# G2 H_DPRSTP# 6,18 A8 A[28]# TMS P1 2 1
H_DPSLP# H_A#29 XDP_TRST# 56_0402_5% +1.05VS
G6 H_DPSLP# 6 C4 J4
DPSLP# H_DPWR# H_A#30 A[29]# TRST#
DPWR# V31 H_DPWR# 6 A14 A[30]# RSVD14 G26
R30 G4 H_PWRGOOD H_A#31 B11 T1 TPC12
BSEL[0] PWRGOOD H_CPUSLP# H_PWRGOOD 6 H_ADSTB#1 A[31]#
M31 BSEL[1] SLP# J2 H_CPUSLP# 6 6 H_ADSTB#1 D11 ADSTB[1]# PROCHOT# H5 PROCHOT# 8,18
CPU_BSEL2 U28 K27 T5 H_THERMDA




THERM
6,14 CPU_BSEL2 BSEL[2] RSVD12 THRMDA
H_A20M# G30 U4 H_THERMDC H_THERMDA, H_THERMDC routing together,
13 H_A20M# H_PBE# A20M# THRMDC
SILVERTHORNE_FCBGA8-441 J28
6 H_PBE# H_IGNNE# FERR# Trace width / Spacing = 10 / 10 mil
H27 T1
IGNNE# THERMTRIP# H_THERMTRIP#
H_THERMTRIP# 6
H_STPCLK# K1
6 H_STPCLK# STPCLK#
layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs H_INTR H31
6 H_INTR LINT0
H_NMI L28 P29
6 H_NMI H_SMI# LINT1 BCLK[0] CLK_CPU_BCLK 14




H CLK
6 H_SMI# J26 SMI# BCLK[1] R28 CLK_CPU_BCLK# 14
CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0 Resistor pla