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1 2 3 4 5 6 7 8
PCB STACK UP
8L
QL8(15.4W) BLOCK DIAGRAM 01
CPU CPU THERMAL
LAYER 1 : TOP SENSOR
Penryn 14.318MHz
A LAYER 2 : SGND PAGE 5 A
478P (uPGA)/35W
LAYER 3 : IN1 PAGE 3,4 CLK_CPU_BCLK,CLK_CPU_BCLK#
CLOCK GEN
LAYER 4 : SGND1 CLK_MCH_BCLK,CLK_MCH_BCLK#
DREFCLK,DREFCLK# ALPRS355B MLF64PIN
LAYER 5 : SVCC FSB 667/800/1066
DREFSSCLK,DREFSSCLK#
PAGE 2
LAYER 6 : IN2
LAYER 7 : SGND2 PS8101
LAYER 8 : BOT PAGE 20 27MHz
NORTH BRIDGE
DDRII 667/800 MHz HDMI CON
DDRII-SODIMM1
NVIDIA PAGE 20
PAGE 10 Cantiga PCI-Express
16X NB9M-64bit or
NB9P-GE2 128bit CRT
Docking DDRII-SODIMM2 DDRII 667/800 MHz
B
CRT PAGE 20
B
LAN/RJ-45 PAGE 10 PAGE 5~9 PAGE 12~18
Headphone Jack 969p Dual Link
LCD CONN Mini PCI-E(WLAN) 10
USB Port Mini PCI-E(WWAN) 11
Express Card x1 7
DMI LINK 32.768KHz PAGE 19 Docking x1 4
NBSRCCLK, NBSRCCLK# E-SATA x1 0
PAGE 34
SATA - HDD
SATA0 150MB USB2.0
PAGE 30 1,2 8 9 12MHz 6
SYSTEM CHARGER(ISL6251AHAZ-T) USB2.0 Ports BlueTooth Webcam
SOUTH BRIDGE
PAGE 35 SATA1 150MB X2 PAGE 26 PAGE 26 PAGE 19
SATA - CD-ROM
RTS5158E
PAGE 30 PAGE 25
SYSTEM POWER ISL6237IRZ-T
ICH9-M
PAGE 36
E-SATA
SATA5 150MB PCI-E
PAGE 31 X2 X1 X1
C VCCP +1.5V AND GMCH Azalia C
1.05V(RT8204) Mini PCI-E Express
PAGE 37
PAGE 21,22,23,24 LAN
Card Realtek Card
Analog (Wireless PCIE-LAN
CPU CORE ISL6266A RTL8102E/8111C
LAN/WWAN) (NEW CARD)
PAGE 38 32.768KHz LPC Azalia ALC268 (10/100/GagaLAN)
MDC CONN PAGE 33
PAGE 28,29
PAGE 30
PAGE 27 PAGE 26
VGACORE(1.025V)Oz8118
PAGE 39
ENE KBC 25MHz
AUDIO
DDR II SMDDR_VTERM Keyboard Amplifier
1.8V/1.8VSUS(TPS51116REGR) KB3926 C0 SPI RJ45
PAGE 40 Touch Pad PAGE 32 TPA6017A2
PAGE 28
PAGE 22
PAGE 27
PAGE 32
D
microphone Audio Jacks Jack to D
[email protected]
(Phone/ MIC) Speaker
PAGE 19 PAGE 26 PAGE 27
SPI
G995
PROJECT : QL8
FAN PAGE 32 Quanta Computer Inc.
PAGE 34
Size Document Number Rev
Custom
NB5 Block Diagram 3A
Date: Wednesday, April 02, 2008 Sheet 1 of 45
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
[4,6,9,10,11,12,14,15,19,20,21,22,23,24,26,27,28,30,31,32,33,34,38,41] +3V
02
[3,4,5,6,8,9,21,24,31,37,38] +1.05V
+3V
L52
1 2 +3V_CK_MAIN
HCB1608KF-181T15_6 U14
C800
C518 C803 C804 C496 C802 +3V_CK_MAIN 23 61
VDDPLL3 CPUCLKT0 CLK_CPU_BCLK [3]
10U/6.3V_8 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 16 60
A VDD48 CPUCLKC0 CLK_CPU_BCLK# [3] A
SRC8 RP48 4 3 *4P2R-S-0
9
4
VDDPCI
VDDREF
CK505 CPUCLKT1 58 CLK_MCH_BCLK [5]
SRC8# 2 1
CLK_CPU_ITP [3]
CLK_CPU_ITP# [3]
L35 46 57
VDDSRC CPUCLKC1 CLK_MCH_BCLK# [5]
1 2 +3V_CK_CPU +3V_CK_CPU 62
HCB1608KF-181T15_6 VDDCPU SRC8
CPUT2_ITP/SRCT8 54
C479 +3V_CK_MAIN2 19 53 SRC8#
C490 VDD96I/O CPUC2_ITP/SRCC8
27 VDDPLL3I/O
10U/6.3V_8 .1U/10V_4 33 20 SRC0
VDDSRCI/O DOTT_96/SRCT0 SRC0#
43 VDDSRCI/O DOTC_96/SRCC0 21
52 VDDSRCI/O
24 SRC1 SRC0 RP59 4 3 *4P2R-S-0
27MHz_Nonss/SRCCLK1/SE1 DREFCLK [6]
L39 56 25 SRC1# SRC0# 2 1
VDDCPU_IO 27Mhz_ss/SRCCLC1/SE2 DREFCLK# [6]
1 2 +3V_CK_MAIN2 55
HCB1608KF-181T15_6 NC
SRCCLKT2/SATACL 28 CLK_PCIE_NEW [30]
29 RP47 2 1 4P2R-S-0
SRCCLKC2/SATACL CLK_PCIE_NEW# [30] CLK_PCIE_VGA [12]
C519 C505 C517 C492 C516 C498 C811 CG_XIN 3 4 3
X1 CLK_PCIE_VGA# [12]
10U/6.3V_8 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 CG_XOUT 2 31
X2 SRCCLKT3/CR#_C TP46
SRCCLKC3/CR#_D 32 TP51
*100K/F_4 R225 34
SRCCLKT4 CLK_PCIE_3GPLL [6]
SRCCLKC4 35 CLK_PCIE_3GPLL# [6] int
SRC1 RP49 2 1 *4P2R-S-0 DREFSSCLK [6]
63 45 SRC1# 4 3
[23] CK_PWG CK_PWRGD/PD# PCI_STOP# PM_STPPCI# [23] DREFSSCLK# [6]
+3V CPU_BSEL1 R219 2.2K_4 FSB 64 44
+3V FSLB/TEST_MODE CPU_STOP# PM_STPCPU# [23]
48 RP60 4 3 4P2R-S-33
SRCCLKT6 CLK_PCIE_ICH [22] 27M_NONSS [14]
SRCCLKC6 47 CLK_PCIE_ICH# [22] 2 1 27M_SS [14]
2
7 SCLK SRCCLKT7/CR#_F 51 CLK_PCIE_WLAN [33] des
Q7 R215 R214 [10,11,30,33] CGCLK_SMB 6 50
SDATA SRCCLKC7/CR#_E CLK_PCIE_WLAN# [33]
2
B R204 10K/F_4 10K/F_4 [10,11,30,33] CGDAT_SMB B
10K/F_4 2N7002 37
SRCCLKT9 CLK_PCIE_LAN [28]
3 1 CGDAT_SMB 22 38
[23] PDAT_SMB CLK_PCIE_LAN# [28]
1
GND SRCCLKC9
26 GND
TME 18 41
GND48 SRCCLKT10 CLK_PCIE_SATA [21]
59 GNDCPU SRCCLKC10 42 CLK_PCIE_SATA# [21]
15 GNDPCI
+3V 1 40
GNDREF SRCCLKT11/CR#_H CLK_PCIE_WWAN [33]
30 GNDSRC SRCCLKC11/CR#_G 39 CLK_PCIE_WWAN# [33]
Q8 36 GNDSRC
2
49 GNDSRC
2N7002 8 R_CLK_NEWCARD_OE# R213 475/F_4
PCICLK0/CR#_A CLK_NEWCARD_OE# [30]
3 1 CGCLK_SMB 10 R_CLK_MCH_OE# R205 475/F_4
[23] PCLK_SMB PCICLK1/CR#_B CLK_MCH_OE# [6]
11 TME R210 33_4
PCICLK2/TME PCLK_DEBUG [33]
12 R_PCLK_KBC R208 33_4
PCICLK3 PCLK_KBC [32]
13 27M_SEL
PCICLK4/27_SELECT
0=overclocking
65 ITP_EN R206 33_4
of CPU and Y3 EPAD PCLK_ICH [22]
SRC Allowed CG_XIN 1 2 CG_XOUT 14 R220 22_4
PCI_F5/ITP_EN CLK_48M_USB [23]
R218 22_4
CLK_48M_CR [25]
1 = overclocking 17 FSA R226 2.2K_4 CPU_BSEL0
14.318MHZ USB_48MHZ/FSLA R207 10K/F_4 CPU_BSEL2
of CPU and SRC C471 C475 5 FSLC R216 33_4
FSLC/TST_SL/REF CLK_14M_ICH [23]
not Allowed 27P/50V_4 27P/50V_4
ICS9LPRS355BKLF MLF64
+3V
Change to 33p
C C
CK505 QFN64
2
des R211 ICS ICS9LPRS355BKLF ALPRS355000 +3V
10K/F_4 27M_SEL
PIN20 PIN21 PIN24 PIN25 Silego SLG8SP513VTR AL8SP513000
1
27M_SEL PIN13 CLK_MCH_OE# R506 2 1 10K/F_4
Realtek RTM875N-606-VD-GR AL000875000
2
0=UMA DOT96T DOT96C SRCT1/LCDT_100 SRCT1/LCDT_100 CLK_NEWCARD_OE# R212 2 1 10K/F_4
int R217
*10K/F_4
1 = External
1
VGA SRCT0 SRCC0 27Mout-NSS 27Mout-SS
0=UMA
1 = External VGA C472 *33P/50V_4 PCLK_KBC
FSC FSB FSA CPU SRC PCI C798 *27P/50V_4 PCLK_ICH
CPU Clock select
+3V C476 *33P/50V_4 PCLK_DEBUG
CPU_BSEL0 R532 0_4
1 0 1 100 100 33
[3] CPU_BSEL0 MCH_BSEL0 [6]
0 0 1 133 100 33 C801 22P/50V_4 CLK_48M_USB
2
0 1 1 166 100 33 C474 22P/50V_4 CLK_48M_CR
*10K/F_4 R530 *1K/F_4
R508 0 1 0 200 100 33 C473 *33P/50V_4 CLK_14M_ICH
R_PCLK_KBC CPU_BSEL1 R518 0_4
[3] CPU_BSEL1 MCH_BSEL1 [6]
1
D D
0 0 0 266 100 33 for EMI
ITP_EN
1 0 0 333 100 33
2
2
+1.05V R529 *1K/F_4
R512 1 1 0 400 100 33
10K/F_4 *10K/F_4 CPU_BSEL2 R203 0_4
PROJECT : QL8
[3] CPU_BSEL2 MCH_BSEL2 [6]
R209 1 1 1 RSVD 100 33
1K to NB only when
Quanta Computer Inc.
1
1
XDP is implement.No
+1.05V R202 *1K/F_4 XDP can use 0 ohm
Enable ITP CLK
Size Document Number Rev
Custom
NB5 Clock Generator 3A
Date: Tuesday, April 08, 2008 Sheet 2 of 45
1 2 3 4 5 6 7 8
5 4 3 2 1
[2,4,5,6,8,9,21,24,31,37,38] +1.05V
[5] H_A#[35:3]
H_A#3
H_A#4
J4
U25A
A[3]# ADS# H1 H_ADS# [5] [5] H_D#[63:0]
U25B H_D#[63:0]
03
L5 A[4]# BNR# E2 H_BNR# [5]
ADDR GROUP 0
H_A#5 L4 G5 H_D#0 E22 Y22 H_D#32
A[5]# BPRI# H_BPRI# [5] D[0]# D[32]#
H_A#6 K5 H_D#1 F24 AB24 H_D#33
H_A#7 A[6]# H_D#2 D[1]# D[33]# H_D#34
M3 A[7]# DEFER# H5 H_DEFER# [5] E26 D[2]# D[34]# V24
H_A#8 N2 F21 H_D#3 G22 V26 H_D#35
A[8]# DRDY# H_DRDY# [5] D[3]# D[35]#
H_A#9 J1 E1 H_D#4 F23 V23 H_D#36
D A[9]# DBSY# H_DBSY# [5] D[4]# D[36]# D
H_A#10 N3 H_D#5 G25 T22 H_D#37
H_A#11 A[10]# H_D#6 D[5]# D[37]# H_D#38
P5 A[11]# BR0# F1 HBREQ#0 [5] E25 D[6]# D[38]# U25
DATA GRP 0
DATA GRP 2
DATA GRP 2
H_A#12 P2 H_D#7 E23 U23 H_D#39
A[12]# D[7]# D[39]#
CONTROL
H_A#13 L2 D20 H_IERR# R84 56.2/F_4 +1.05V H_D#8 K24 Y25 H_D#40
H_A#14 A[13]# IERR# H_D#9 D[8]# D[40]# H_D#41
P4 A[14]# INIT# B3 H_INIT# [21] G24 D[9]# D[41]# W22
H_A#15 P1 H_D#10 J24 Y23 H_D#42
H_A#16 A[15]# H_D#11 D[10]# D[42]# H_D#43
R1 A[16]# LOCK# H4 H_LOCK# [5] J23 D[11]# D[43]# W24
M1