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8 7 6 5 4 3 2 1
Last Schematic Update Date:
10/29/2001
D Cover Sheet 1 D
MS-6558 VERSION:100
Block Diagram
MAIN CLOCK GEN
2
3
SIS 645/650 CHIPSET
DDR CLOCK BUFFER 4
Willamette/Northwood 478pin mPGA-B Processor Schematics
mPGA478-B INTEL CPU Sockets 5-6
SIS 645/650 NORTH BRIDGE 7- 10
CPU: DDR SLOT 11-12
Willamette/Northwood mPGA-478B Processor DDR TERMINATOR 12
SIS 961A SOUTH BRIDGE 13-16
System Brookdale Chipset: AGP SLOT 17
C SIS 645/650 (North Bridge) C
+961A (South Bridge) PCI SLOTS 18-19
On Board Chipset: LAN CONTROLLER 20
RJ45 CONNECTOR 21
LPC Super I/O -- W83697HF
IDE CONNECTOR 22
Expansion Slots: USB CONNECTOR 23
AGP2.0 SLOT * 1
KB/MS CONNECTOR 24
PCI2.2 SLOT* 3 AC'97 CODEC 25
CNR SLOT * 1
AUDIO CONNECTOR 26
CNR CONNECTOR 27
B
LPC I/O(W83697HF) 28 B
HARDWARE MONITOR 29
PARALLEL PORT 30
SERIAL PORT 31
FLASH MEMORY 32
VRM 9.X 33
VOLTAGE REGULATOR 34-35
ATX POWER CON & VGA CON 36
FRONT PANEL 37
A
Decoupling Capacitor 38 A
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
System Block Diagram
D D
SOCKET-478
Host Bus
Support Dual Monitor
SSTL-2 Termination
VGA
D-SUB
VGA SLOT DDR SDRAM (Only for DDR)
SIS645/650
DIMM 1 DIMM 2 Rtt
C VGA Connector VGA CONNECTOR VGA C
HyperZip Analog In
S u pport Max to six-PCI Devices
512 MB
AC'97
Audio Codec
Lan PCI SLOT 3 PCI SLOT 2 PCI SLOT 1 Analog Out
SiS961 CNR
IDE 1 IDE 2
KEYBOARD PS/2
/MOUSE
B USB 0 USB 3 B
USB 1 USB 4
LPC Bus
FAN FAN FAN CONTROL VOLTAGE MONITOR
1 2
TEMPERATURE MONITOR
LPC Super I/O
Legacy FAN CONTROL
ROM
A GPIOs IR/CIR GAME/MIDI SERIAL PARALLEL FLOPPY
A
M I C R O - S T A R I N T ' L CO.,LTD.
Title
S y s t e m B l o c k Diagram
Size D o c u m e n t Number Rev
B MS-6558 1.0
Date: M o n d a y , N o v e m b e r 0 5 , 2001 Sheet 2 of 38
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
VCC3
Main Clock Generator
(3 OPTIONS)
1: (ICS)
CB242 CB243 CB244 2: (Cypress)
L48 CP24 3. (Hitachi)
0.01u 0.01u 0.01u
X_80-0805 X_COPPER By-Pass Capacitors
P l ace near to the Clock Outputs
U15
D 952001AF
CPUCLK0 R215 49.9 D
1 CPUCLK-0 R216 49.9
11 VDDREF Damping Resistors
13 VDDZ Place near to the CPUCLK1 R213 49.9
19 VDDPCI Clock Outputs CPUCLK-1 R214 49.9
28 VDDPCI
CE7 CB178 CB177 CB196 CB180 CB197 CB179 CB182 CB198 29 VDD48
42 VDDAGP SDCLK C110 10p
X _ 1 0 u/16V ECSMD 48 VDDCPU 40 R237 33 CPUCLK0
0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u VDDSD CPUCLK0 39 R238 CPUCLK0 5
33 CPUCLK-0 CPUCLK-0 5
12 CPUCLK#0 AGPCLK0 C111 X_10p
45 PCI_STOP# 44 R235 33 CPUCLK1
CPU_STOP# CPUCLK1 43 R236 33 CPUCLK1 7
CPUCLK-1 CPUCLK-1 7 AGPCLK1 C112 X_10p
CPUCLK#1
5 47 R234 22 SDCLK SDCLK 8
8 VSSREF SDCLK ZCLK0 C163 X_10p
VSSZ R239 AGPCLK0
18 31 22 AGPCLK0 7
24 VSSPCI AGPCLK0 30 R240 22 AGPCLK1 ZCLK1 C164 X_10p
25 VSSPCI AGPCLK1 AGPCLK1 17
32 VSS48 9 R289 22 ZCLK0
41 VSSAGP ZCLK0 10 R290 ZCLK0 9
22 ZCLK1 ZCLK1 13
46 VSSCPU ZCLK1 CN18 10p
VSSSD 14 FS3 RN76 7 8 33 96XPCLK PCICLK2 1 2
VCC3 VCC3 PCICLK_F0/FS3 15 96XPCLK 13
FS4 5 6 SIOPCLK SIOPCLK 28 PCICLK1 3 4
PCICLK_F1/FS4 16 3 4 PCICLK1 SIOPCLK 5 6
PCICLK0 17 1 2 PCICLK1 18
PCICLK2 PCICLK2 19 96XPCLK 7 8
PCICLK1 20 RN77 33
R219 R218 PCICLK2 21 7 8 PCICLK3
10K 10K PCICLK3 22 5 6 PCICLK3 19
PCICLK4 CN19 1 2 10p
C PCICLK4
PCICLK5
23 3
1
4
2
PCICLK5
PCICLK4
PCICLK5
19
20 PCICLK5
PCICLK4
3
5
4
6
C
33 2 FS0 PCICLK3 7 8
VCCP PD#/VTT_PWRGD REF0/FS0 3 FS1 R283 33 REFCLK0
R207 REF1/FS1 4 REFCLK0 9
FS2 R285 33 REFCLK1 REFCLK1 14
Q27 Q26 R217 38 REF2/FS2 R286 APICCLK APICCLK C161 10p
475 IREF 33 APICCLK 14
27 R287 X_33 REFCLK2 REFCLK2 25
10K N P N - 3 9 0 4 L T 1-S-SOT23 48M 26
N P N - 3 9 0 4 L T1-S-SOT23 24_48M/MULTISEL R241 22 UCLK48M REFCLK0 C153 10p
UCLK48M 15
MULTISEL R242 22 SIO48M SIO48M 28
CP26 X_COPPER REFCLK1 C160 10p
35
VCC3 SCLK REFCLK2 C162 10p
34
SDATA
L49 SMBCLK
36 SMBCLK 4,11,14,27
SMBDAT SMBDAT 4,11,14,27 UCLK48M C113 10p
X_80-0805 VDDA
SIO48M C114 10p
CB194 CB187 CB181
0.1u 0.1u 100P
37
VSSA
VCC3 Frequency Selection
XOUT
XIN
B R291 2.7K FS0 B
6
7
VCC3 R292 X_2.7K FS1
Y1 R288 X_2.7K FS2
R271 X_2.7K FS3
R276 X_2.7K FS4
1 4 M - 1 6 p f -HC49S-D
CE11
CB195 CB184 C143 C134
X _ 1 0 u/16V ECSMD 18p 18p
0.1u 100P MULTISEL R220 X_0
R243 X_4.7K
VCC3
SIS650 CLOCK SIS650 CLOCK
FS4 FS3 FS2 FS1 FS0 CPU SDRAM ZCLK AGPCLK PCI FS4 FS3 FS2 FS1 FS0 CPU SDRAM ZCLK AGPCLK PCI
(MHz) (MHz) (MHz) (MHz) (MHz) (MHz) (MHz) (MHz) (MHz) (MHz)
0 0 0 0 0 1 0 0 0 0
0 0 0 0 1 1 0 0 0 1
0 0 0 1 0 1 0 0 1 0
0 0 0 1 1 1 0 0 1 1
0 0 1 0 0 1 0 1 0 0
0 0 1 0 1 1 0 1 0 1
0 0 1 1 0 1 0 1 1 0
A 0
0
0
1
1
0
1
0
1
0
1
1
0
1
1
0
1
0
1
0
A
0 1 0 0 1 1 1 0 0 1
0 1 0 1 0 1 1 0 1 0
0 1 0 1 1 1 1 0 1 1 M I C R O - S T A R I N T ' L CO.,LTD.
0 1 1 0 0 1 1 1 0 0
0 1 1 0 1 1 1 1 0 1
0 1 1 1 0 1 1 1 1 0 Title
0 1 1 1 1 1 1 1 1 1 M A I N CLOCK GEN
Size D o c u m e n t Number Rev
B MS-6558 1.0
Date: M o n d a y , N o v e m b e r 0 5 , 2001 Sheet 3 of 38
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Clock Buffer (DDR)
D (OPTIONS) D
1: (ICS-93705)
CP11 X_COPPER
VCC2.5V
L28
CBVDD
X_80-0805
CB87 CB110 CB111 By-Pass Capacitors
0.1u 0.1u 0.1u P l ace near to the Clock Buffer
CE5 + CB126 CB127
0.01u
X_22u 0.1u DDRCLK0 C58 X_10p
DDRCLK1 C59 X_10p
D D RCLK[0..8] D D RCLK[0..8] 11
DDRCLK2 C62 X_10p
D D R CLK-[0..8]
D D R CLK-[0..8] 11
DDRCLK3 C64 X_10P
SMBCLK SMBCLK 3,11,14,27
SMBDAT SMBDAT 3,11,14,27
FWDSDCLKO
FWDSDCLKO 8
DDRCLK8 C39 X_10P
C DDRCLK7 C42 X_10P
C
U7
ICS93722
CP14 X_COPPER CBVDD 3
12 VDD 2 R111 DDRCLK0 DDRCLK-0 C57 X_10P
0
23 VDD CLK0 4 R112 0 DDRCLK1
VDD CLK1 13 R115 0 DDRCLK2 DDRCLK-1 C60 X_10P
L32 CLK2 17 R118 DDRCLK3
CLK3 0
10 24 R82 0 DDRCLK8 DDRCLK-2 C61 X_10P
VCC2.5V AVDD CLK4 26 R85 DDRCLK7