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Revisions Approvals
REV ECN NO. Description Of Change DATE DFTG. ENGR. REL.
TABLE OF CONTENTS
PAGE PAGE
4 - CLOCK GENERATOR 33- KEYBOARD CONNECTOR & TOUCH PAD
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5-7 - BANIAS PROCESSOR 34 - LID SWITCH/LEDS
8-12 - MONTARA-GM 35 - CARDBUS CONTROLLER
13-16 - DDR 36 - PCMCIA CARD
37- PC CARD CONNECTOR
17 - TV ENCODER
38 - MINI PCI
18 - CRT
39 - AC97 CODEC
19 - LVDS
40 - VR & MIC JACK
21-23- ICH4-M
41 - AMP
24 - HDD CONNECTOR 42- MDC I/F
25 - CD-ROM CONNECTOR 43 - THERMAL SENSOR & FAN CONTROLLER
26 - USB PORT 44 - DECOUPLING CAPS
27 - LAN CONTROLLER 45 - DRILL HOLE
28 - LAN POWER 46 - HIGH SPEED
29- RJ45 CONN 47 - PULL UPS
30- CHIVAS II 48-56 - POWER
31 - FLASH ROM & IR
32- 1394 CONTROLLER Digitally signed by dd
DN: cn=dd, o=dd, ou=dd,
[email protected],
c=US
Engineer
Engr_Name
Drawn by
Drawer_Name
INVENTEC
Date: 2009.11.20 20:45:11
R&D CHK Size
TITLE
A3
Cricket 2.0
DOC CTRL CHK
MFG ENGR CHK
Changed by
EE1
Date Changed
Friday, July 11, 2003
Time Changed
8:13:36 pm +07'00'
QA CHK VER
A03
Model Number
FC8496
Sheet 1 of 56
CPU
ITP BANIAS
(Micro_FCPGA)
mPGA478
CLK GEN
ICS950810
P.5-7
PSB P.4
CRT
North Bridge DDR 200/266 2.5V
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TV-Encoder DDR_SODIMM0
MONTARA-GM
CH7011A 732 BGA
P.8-12 DDR_SODIMM1
P.13-16
LCM Hub Interface
LAN INTERFACE FOR 10/100 Mbps ( 82562-EZ )
1 st
HDD
PWR Board P.24
South Bridge PCI Bus
Batt Charger CD-ROM 2 nd ICH4-M
421 BGA
P.25
P.21-23
USB2.0 x 3 1394
LPC 3.3V 33MHZ CardBus LOM
P.26 Controller TI / TSB43AB21 Mini PCI Controller
MAIN BATT Type III INTEL 82540-EM/
ENE CB720 INTEL 82562EZ
BIOS P.32
SUPER I/O & KBC P.35 P.38 P.27
P.31 CHIVAS-II
LPC 47N253 PC CARD SD SLOT 1394 CONN X 1 802.11b RJ45
P.30
TWO SLOTS CONN
P.37
TOUCH PAD P.32
2 PICK BUTTON/ P.36 P.29
1 SCROLL BUTTON
ANT ANT
P.33
2 nd AC97
MDC
1 st AC97
IR Audio on Board EARPHONE RJ11 CNTR
P.31 P.41 P.42
P.39
EXTERNAL
KB
Codec MIC Engineer
AD1981B
P.33
P.40
Engr_Name
Drawn by
Drawer_Name
INVENTEC
AMP R&D CHK
TITLE
Size
A3
Speaker
NS LM4873
DOC CTRL CHK
MFG ENGR CHK
Cricket 2.0
P.41
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 2 of 56
EE1 Friday, July 11, 2003 8:14:04 pm A03 FC8496
+VBAT
PMOS
+VCC_CORE
MAX1987
+ADAPTOR +VCC_CORE
PMOS PMOS PWR_GOOD_3 ON_+VCC_CORE
CHARGE
MCH_GOOD H_PWRGD
+VCCP
MAX1845
+VCCP +V1.2S_MCH
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BQ24701
PWR_GOOD_3 ON_+VCCP
+V1.2 +V5S
ON_+V1.2 +V2.5
+V2.5A
MCH_GOOD +V2.5
MAX1845
SLP_S4_3R +V2.5S
ON
+V2.5 +V1.8S
+V2.5S
SLP_S3#_3R
+V1.5A ON
+V1.5AON ON +V1.8S
+V1.5A
+V3AON PGOOD
PACK1 MAX6308
+V1.5ON
+V3
+V3
SLP_S4#_3R PMOS
+V3 ON
MAX1999 +V3S
PMOS
+V3A
SLP_S3#_3R +V3S
+V5ON +V5_a ON
ON5
PMOS +V5_a
ON3
+V1.25 +V5A
+V2.5 2VREF REF SLP_S3#_3R +V5
LP2996 ON
+V5S
PMOS
SLP_S3#_3R +V5S
ON
+VGAVCC
(1.5V / 1.25V)
+v2.5S +V2.5
SM_VREF
+V1.5S
NMOS
Engineer
SLP_S3_4R
+V1.5S
Engr_Name
Drawn by
Drawer_Name
INVENTEC
ON R&D CHK Size
TITLE
A3
DOC CTRL CHK
MFG ENGR CHK
Cricket 2.0
BLOCK DIAGRAM
Changed by Date Changed Time Changed QA CHK VER Model Number Sheet 3 of 56
EE1 Friday, July 11, 2003 8:14:28 pm A03 FC8496
+V3S_CLK L21 +V3S
NFM40P12C223
1 2
4 3
C350
1 C365 1 C367 1 C351 1 C366 1 C348 1 C363 1 C364 1 C349 1
2 2 2 2 2 2 2 2
22UF_6.3V
0.01UF_16V 0.01UF_16V 0.01UF_16V 0.01UF_16V 0.01UF_16V 0.01UF_16V 0.01UF_16V 0.01UF_16V
(10/5) (10/5)
1 L22 2
BLM11A221S
1 C352 C353
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1
U14 2 0.01UF_16V 22UF_6.3V
1 VDD VDDA 26
8 VDD
Place crystal within 500
14 VDD VSSA 27 1 2
+V3S mils of CLK_TITAN 19 VDD R220 49.9_1%
R1896
+V3 32 VDD CPU2 45 CLK_CPU_BCLK_3 1 2 33_5% 46-,5-
CLK_CPU_BCLK
NO_STUFF_10PF 37 VDD CLK_CPU_BCLK#_3 R197 2 33_5%
C394 OPEN
46 VDD CPU2# 44 1 46-,5-
CLK_CPU_BCLK#
U1062 1 50 VDD
1 2
SLP_S1#_3R 22- 1 5 1 2 R194 49.9_1% R224 49.9_1%
4 X3 2 XTAL_IN CLK_MCH_BCLK_3 R230 2 33_5% 1 2
4- PM_SLP_S1# 1 1 CPU1 49 1 46-,10-
CLK_MCH_BCLK
SLP_S3#_3R 21SF
56-,55-,53-,52-,49-,22-
R226 14.31818MHZ
C400 OPEN R228
3 TC7SET08F R262
2
3 XTAL_OUT CPU1# 48 CLK_MCH_BCLK#_3 1 2 33_5% 46-,10-
CLK_MCH_BCLK#
OPEN 1K_5% 1 2 1 2
NO_STUFF_10PF R222 49.9_1%
2 2 R231 33_5% R223 49.9_1%
1 R195 2 40 SEL2 CPU0 52 CLK_ITP_3 1 2 1 2
46-
1K_5% CLK_ITP#_3 1 33_5% 2 CLK_ITP
CPU0# 51
55 SEL1 R232 R221 49.9_1%
66INPUT 24
1 2 46-
CLK_ITP#
54 SEL0 66BUF2 23
25 PWRDWN# CLK_MCH66_3 R200 33_5% 46-,9-
PM_SLP_S1# 4- 66BUF1 22 CLK_MCH66
1 2
1 1
34 PCI_STOP# CLK_ICHHUB_3 R202 33_5%
PCISTOP#_3 22- 66BUF0 21 1 2 46-,21- CLK_ICHHUB
R227
R263 OPEN R225
53 CPU_STOP# CLK_ICHPCI_3 R237 33_5%
1K_5% CPUSTOP#_3 51-,22- 1 2 PCIF2 7 1 2 46-,21- CLK_ICHPCI_3R
2 2 0_5%
28 VTT_PWRGD# PCIF1 6
+V3S R191 1 2 43 MULT0 PCIF0 5
10K_5%
29 SDATA CLK_CBPCI_3 R233
ICH_SMDAT_3 47-,21-,13-,4- PCI6 18 1 2 33_5% 46-,35- CLK_CBPCI_3R
ICH_SMCLK_3 47-,21-,13-,4- 30 SCLOCK PCI5 17
33 DRCG0 PCI4 16 CLK_MINIPCI_3 1 R236 2 33_5% 46-,38- CLK_MINIPCI_3R
R677 35 DRCG1_VCH
1 2 PCI3 13
33_5% CLK_LANPCI_3 R234
42 IREF PCI2 12 1 2 33_5% 27- CLK_LANPCI_3R
PCI1 11 CLK_1394PCI_3 1 R235 2 33_5% 46-,32-
R199 1 CLK_1394PCI_3R
CLK_EN# 51- 1 2 41 VSSIREF
OPEN R193 R238
475_1% 4 PCI0 10 CLK_KBCPCI_3 1 2 33_5% 46-,30-
VSS CLK_KBCPCI_3R
2 9 VSS R192
15 USB 39 CLK_ICH48_3 1 2 33_5% 46-,22- CLK_ICH48_3R
VSS
20 VSS R685
VR_PWRGD_CK# 31 VSS DOT 38 1 2 33_5% 9- DREFCLK
36 VSS
47 REF 56 CLK_SIO14_3 1 R264 2 33_5% 46-,22-
VSS CLK_ICH14_3R
TBD 1 R265 2 33_5% 46-,30- CLK_KBC14_3R
Maybe can be option +V3S ICS_950810_TSSOP_56P 1
R196 2 33_5% 39-
+V3S CLK_AD14_3R +V3S +V1.5S
1 R684 2 1
R1930 2 33_5% 17- CLK_DVO14_3R
1 10K_5%
U657 4- PM_SLP_S1#
R198 1 CLKIN C5516 15PF
10K_5% PD# 8 R679
2 VDD SCLK 7 1 2 9- LCLKCTLA 1 2
3 GND R681
2 SDATA 6 1 2
OPEN 47-,21-,13-,4- ICH_SMCLK_3
1 C5327 1 C5326 4 CLKOUT 48MHZ 5 (For EMI)
0_5% 1 R682 2
Q20 3 2 1UF_10V
2 0.1UF_16V 9- LCLKCTLB
ICS_ICS91718_SOIC_8P 1 R683 2 47-,21-,13-,4- Place C5516 close to CLK_ICHHUB
R177 D OPEN ICH_SMDAT_3
VGATE_U 51-,22- 1 2 2G 0_5%
0_5% S
NDS7002A 1
9- 2 R678 1
DREFSSCLK
33_5%
1
R680
10K_5%
Engr_Name
Drawer_Name
INVENTEC
2
A3
Cricket 2.0
CLK GENERATOR
4 56
A03 FC8496
H_A#(3:16) 46-,10- CN508
H_A#(3) P4 N2 46-,10-
A3# ADS# L1 H_ADS# +VCCP
H_A#(4) U4 A4# BNR# 46-,10- H_BNR#
H_A#(5) V3 J3 46-,10-
A5# BPRI# H_BPRI#
H_A#(6) R3 A6# 1
L4
ADDR GROUP 0
H_A#(7) V2 A7# DEFER# 46-,10- H_DEFER#
H_A#(8) W1 H2 46-,10- R544
A8# DRDY# M2 H_DRDY# 56_5%
H_A#(9) T4 A9# DBSY# 46-,10- H_DBSY#
H_A#(10) W2 A10#