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5 4 3 2 1
FILE LIST
01_BLOCK DIAGRAM
CLOCK GEN 02_POWER DIAGRAM
A6G ICS 950815
Page 23
POWER
(IMVP4)
03_CPU-BANIAS(HOST)
04_CPU-BANIAS(PWR)
05_THERMAL SENSOR
D
BLOCK THERMAL CPU
Page 43,44,45,46,47,48,49,50
06_NB-MCHM(DDR)
07_NB-MCHM(HOST)
08_NB-MCHM(VGA)
D
DIAGRAM SENSOR
Page 5
BANIAS
24.5W VGA POWER
09_NB-MCHM(PWR)
10_DUAL DDR SODIMM
Page 3,4
11_DDR TREMINATION
Page 51 12_ATI M11-P(AGP,LVDS)
13_ATI M11-P(MEMORY IF)
VRAM *4 14_ATI M11-P(PWR)
Page 15,16 15_VRAM(A CHANNEL)
LCD DDR TERMINATION
16_VRAM(B CHANNEL)
Page 17
NORTH Page 11
17_LVDS & BACKLIGHT
VGA BRIDGE 18_CRT & TV-OUT
CRT DUAL DDR SO-DIMM 19_ICH4-M(HUB_PCI)
Page 18 ATI M11-P 20_ICH4-M(H_U_IDE_PM)
Intel 855GME Page 10
C
Page 12,13,14 3.8W 21_ICH4-M(PWR) C
TV-OUT 22_ICH4-M(PULLUP)
Page 18 Page 6,7,8,9 23_CLOCK-ICS950815
24_LAN-RTL8100CL
25_MINIPCI
26_CB1394-R5C593 (1)
AUDIO AMP & MIC AC'97 CODEC 27_CB1394-R5C593 (2)
Page 36,37 Realtek ALC650
PRIMARY IDE 28_PCMCIA SOCKET
Page 29 29_IDE-HDD
Page 35
SOUTH 30_IDE-ODD
MDC BRIDGE SECONDARY IDE
31_KBC-M38857
32_SIO-ITE8705 & FWH
Page 36 Page 30
33_LPT PORT & IR
Intel ICH4-M 34_DISCHARGE CIRCUIT
2.9W
35_CODEC-ALC650
B
36_AUDIO AMP B
Page 19,20,21,22
37_MIC
38_MDC & RJ45 & RJ11
39_USB
CARDBUS/1394 LAN MINIPCI KBC SIO 40_FAN & AUDIO DJ
SIR
RICOH R5C593 Realtek RTL8100CL M38857 ITE8705 Page 33
41_FUNCTION KEY
Page 26,27 Page 24 Page 25 Page 31 Page 32
42_PWR & RESET SEQ
43_VCORE
44_1.25V&1.8V
45_2.5V&1.5V&1.2V&1.05V
1394 PCMCIA LAN & Modem Jack USB CCD USB CON *4 PRINTER PORT 46_SYSTEM
Page 26 Page 28 Page 38 Page 33 47_LOAD SWITCH
Page 17 Page 39
48_CHARGER
Card Reader 49_PIC16C54
Page 27 50_BATLOW/SD#
51_VGACORE
A Audio DJ Screw Hole Discharge Circuit 52_SCREW HOLE & EMI CAP
A
Page 40 Page 52 Page 34 53_M/B SETTING
54_REVISION HISTORY
DC FAN EMI Cap. Function Key Title : BLOCK DIAGRAM
ASUSTek COMPUTER INC. NB1 Engineer: John Hung
Page 40 Page 52 Page 41 Size Project Name Rev
Custom A6G 1.1
Date: Friday, October 15, 2004 Sheet 1 of 54
5 4 3 2 1
5 4 3 2 1
System work voltage +V1.25S : JP4,5 page 39
+V2.5 : JP6 page 40
Adapter in : 19.5 ~18.5 V +V1.2S : JP7 page 40
Battery in : 16.8 ~ 11.6V VR_VID0-VR_VID5 +VCCP : JP9 page 40
PM_STPCPU#.,PM_DPRSLPVR.,PCI#.,MCH_OK.,CLK_EN# +V5S : JP13 page 42
CPU_VRON +V5 : JP14 page 42
+VCORE (25A) +V1.5SUS : JP15 page 39
D
+V1.8 : JP16,19 page 39 D
AC_BAT_SYS
MAX1987 +V1.8S : JP17 page42
VRM_PWRGD
+V12 : JP18 page 42
+V1.5S : JP22 page 40
SUSC#. (3V_ON) +V5A : JP24 page 40
+5VO (5A) SUSB# +V5S
+V3.3A : JP26 or 27 page 39
LTC3728 SUSB# +V3S
+V3.3SUS (5A) +V3.3S : JP28 page 42
(Regulator) +V5
+V3.3 : JP29 page 42
+12VO (0.15A) SUSC# +V3
78L12
SUSB# +V12S
+V12
+1.5VO (2A) +V1.5S
SUSB#
+2.5VO (5A) +V2.5 SUSB# +V1.5S
SUSC#
TPS5130
+5VAO +1.2VO (2A) +V1.2S
C SUSB# C
A/D_VIN SHUT_DOWN#
SWITCH
Power
+1.05VO (1A) +VCCP
SUSB# BAT_S Signal BAT_IN#_OC
Circuit
SUSB# TS# ACIN_OC
+V2.5 CM8562 +V1.25S (2A) AC_APR_UC
(Regulator)
SUSC#
+2.5VO MIC37101-1.8 +1.8VO (1A) +V1.8
LDO
SUSB# +V1.8S
TS#
SUSB# CHG EN#
PIC + TL494 BAT AC_APR_UC PIC16C54C CHG LED_UP
(Charge) SMC_BAT PWR LED_UP
B B
SMD_BAT BAT_LLOW
FDS6679
+5VO (20mA)
A/D_VIN 78L05 SWITCH
FD6JK3TP +5VLCM
(Regulator) +5VCHG (100mA) (F02JK2E)
MIC5223MB +3VALWAYS_M +V3.3A LM4040BIM +2.5VREF
(Regulator) (Regulator) (500uA)
+V3.3SUS CM2855 +V1.5SUS
A
(LDO) A
+5VAO +5VALWAYS
Title : POWER DIAGRAM
ASUSTek COMPUTER INC. NB1 Engineer: Adams Lin
Size Project Name Rev
Custom A6G 1.1
Date: Friday, October 15, 2004 Sheet 2 of 54
5 4 3 2 1
5 4 3 2 1
H_D#[63:0] 7
U31B U31A
7 H_A#[16:3]
H_A#16 AA2 N2 H_D#15 C25 Y25 H_D#47
A[16]# ADS# H_ADS# 7 D[15]# D[47]#
H_A#15 Y3 A10 H_PRDY# H_D#14 E23 AA26 H_D#46
H_A#14 A[15]# PRDY# H_PREQ# H_D#13 D[14]# D[46]# H_D#45
AA3 A[14]# PREQ# B10 B23 D[13]# D[45]# Y23
ADDR GROUP 0 -> L1 H_A#13 U1 COMMON CLOCK -> L4 H_D#12 C26 V26 H_D#44 DATA GROUP 0,2 -> L1
H_A#12 A[13]# H_D#11 D[12]# D[44]# H_D#43
Y1 L1 H_BNR# 7 E24 U25
ADDR GROUP 1 -> L4 H_A#11 Y4
A[12]# BNR#
J3 WIDTH: 4.5 mils H_D#10 D24
D[11]# D[43]#
V24 H_D#42 DATA GROUP 1,3 -> L4
H_BPRI# 7
ADDRESS GROUP 0
A[11]# BPRI# D[10]# D[42]#
DATA GROUP 0
SPACE >= 1:2 H_A#10 SPACE >= 1:2 H_D#9 H_D#41 SPACE >= 1:2
2
W2 A[10]# B24 D[9]# D[41]# U26
H_A#9 T4 H_D#8 C20 AA23 H_D#40
STROBE SPACE >= 1:2 GROUP SPACE >= 20 mils GROUP SPACE >=20 mils
DATA GROUP
H_A#8 A[9]# T107 TPC28t H_D#7 D[8]# D[40]# H_D#39
D W1 A[8]# DBR# A7 1 B20 D[7]# D[39]# R23 D
GROUP SPACE >= 20 mils H_A#7 V2 A[7]#
LENGTH: 2.2" - 6.5" H_D#6 A21 D[6]# D[38]# R26 H_D#38 LENGTH: 0.5" - 5.5"
H_A#6 R3 H_D#5 B26 R24 H_D#37
LENGTH: 0.5" - 6.5" H_A#5 V3
A[6]# H_D#4 A24
D[5]# D[37]#
V23 H_D#36
H_A#4 A[5]# H_D#3 D[4]# D[36]# H_D#35
U4 A[4]# DEFER# L4 H_DEFER# 7 B21 D[3]# D[35]# U23
H_A#3 P4 H2 H_D#2 A22 T25 H_D#34
A[3]# DRDY# H_DRDY# 7 D[2]# D[34]#
U3 M2 H_D#1 A25 AA24 H_D#33
7 H_ADSTB#0 ADSTB[0]# DBSY# H_DBSY# 7 D[1]# D[33]#
H_REQ#4 T1 H_D#0 A19 Y26 H_D#32
H_REQ#3 REQ[4]# D[0]# D[32]#
P1 REQ[3]# 7 H_DINV#0 D25 DINV[0]# DINV[2]# T24 H_DINV#2 7
H_REQ#2 T2 C23 W25
REQ[2]# 7 H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 7
H_REQ#1 P3 C22 W24
REQ[1]# 7 H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 7
H_REQ#0 R2 REQ[0]# H_BR0# H_D#31 H_D#63
7 H_REQ#[4:0] N4 H_BR0# 7 K25 AF26
CONTROL
BR0# +VCCP H_D#30 D[31]# D[63]# H_D#62
N25 D[30]# D[62]# AF22
H_D#29 H26 AF25 H_D#61
H_IERR# H_D#28 D[29]# D[61]# H_D#60
IERR# A4 2 1 M25 D[28]# D[60]# AD21
0.5"-12" R271 56Ohm H_D#27 N24 AE21 H_D#59
7 H_A#[31:17] D[27]# D[59]#
H_A#31 AF1 H_D#26 L26 AF20 H_D#58
3
A[31]# D[26]# D[58]#
DATA GROUP 1
H_A#30 AE1 B5 <=10" H_D#25 J25 AD24 H_D#57
A[30]# INIT# H_INIT# 20,32 D[25]# D[57]#
H_A#29 H_D#24 H_D#56
DATA GROUP
AF3 A[29]# M23 D[24]# D[56]# AF23
H_A#28 AD6 H_D#23 J23 AE22 H_D#55
ADDRESS GROUP 1
H_A#27 A[28]# H_D#22 D[23]# D[55]# H_D#54
AE2 A[27]# LOCK# J2 <=10" H_LOCK# 7 G24 D[22]# D[54]# AD23
H_A#26 AD5 H_D#21 F25 AC25 H_D#53
H_A#25 A[26]# H_D#20 D[21]# D[53]# H_D#52
AC6 A[25]# H24 D[20]# D[52]# AC22
H_A#24 AB4 H_D#19 M26 AC20 H_D#51
H_A#23 A[24]# H_D#18 D[19]# D[51]# H_D#50
AD2 A[23]# L23 D[18]# D[50]# AB24
H_A#22 AE4 H_D#17 G25 AC23 H_D#49
H_A#21 A[22]# H_D#16 D[17]# D[49]# H_D#48
AD3 A[21]# RESET# B11 <=3" H_CPURST# 7 H23 D[16]# D[48]# AB25
H_A#20 AC3 L2 H_RS#2 J26 AD20
A[20]# RS[2]# 7 H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 7
H_A#19 AC7 K1 H_RS#1 K24 AE24
A[19]# RS[1]# 7 H_DSTBN#1 DSTBN[1]# DSTBN[3]# H_DSTBN#3 7
H_A#18 AC4 H1 H_RS#0 L24 AE25
C A[18]# RS[0]# 7 H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 7 C
H_A#17 AF4 A[17]# H_RS#[2:0] 7
AE5 M3 SOCKET479P
7 H_ADSTB#1 ADSTB[1]# TRDY# H_TRDY# 7
HIT# K3 H_HIT# 7
8 H_DPWR# 1"-6.5" C19 DPWR# HITM# K4 H_HITM# 7
TOPOLOGY 1B: TOPOLOGY 2A:
SOCKET479P +VCCP +VCCP
CPU-ICH-R R-CPU-ICH Y-FORK +VCCP
H_VID5 CPU-ICH: 0.5" - 12" CPU-ICH: 0.5" - 12"
VR_VID5 43 H_GTLREF0: Close to
1
1
H_VID4
VR_VID4 43 ICH-R <= 3" R - CPU <= 3" LENGTH <=0.5" Pin AD26
1
H_VID3
H_VID2 VR_VID3 43
VR_VID2 43
R239 R73 WIDTH = 5.5 mils of CPU
T92 TPC28t 1_CLK_CPU_BCLK H_VID1 56Ohm 332Ohm R224
T95 TPC28t 1_CLK_CPU_BCLK# H_VID0 VR_VID1 43 SPACE >= 25 mils 1KOhm
CPU PLL CIRCUITS VR_VID0 43 H_THRMTRIP_S# H_PWRGD
2
2
1.71V - 1.89V(+/- 5%) H_GTLREF0
2
U31C
S0-S1M: 0.3A
1
23 _CLK_CPU_BCLK 2"-8" B15 BCLK[0] Same Side
2"-8" B14 TOPOLOGY 1B: TOPOLOGY 2B:
HOSTCLK
R223 w/ CPU
23 _CLK_CPU_BCLK# BCLK[1] CPU_COMP3
+V1.8S_PROC T94 TPC28t 1 A16 AB1 +VCCP
T96 TPC28t 1 A15
ITP_CLK[0] COMP[3]
AB2 CPU_COMP2 CPU-ICH-R MCH-CPU-ICH4 2KOhm
+V1.8S_F26 ITP_CLK[1] COMP[2] CPU_COMP1
COMP[1] P26 CPU-ICH: 0.5" - 12" MCH-CPU:0.5"-6.5"
1
<=10" CPU_COMP0
2