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WD33C95AIWD33C96A

TABLE OF CONTENTS
Section Title Page

1.0 INTRODUCTION 24-1
1.1 Document Scope 24-1
1.2 Reference Documents 24-1
1.3 Features 24-1
1.4 General Description 24-1

2.0 ARCHITECTURE 24-2
2.1 Performance 24-2
2.2 Flexibility 24-2
2.3 Microprocessor Interface 24-2
2.4 DMA Interface 24-2
2.5 Dual Port Registers 24-2
2.6 Differential Driver Control 24-2
2.7 Power Management 24-2
2.8 Testability 24-4

..
2.9 Compatibility with WD33C93 Family 24-4

3.0 SIGNAL DESCRIPTION 24-5

A.O GLOSSARY AND CONVENTIONS