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5 4 3 2 1


HOST 133/166MHz

CLK-GEN PCIE 100MHz

ICS954310 VGA 96MHz

USB 48MHz CPU BD1 BLOCK DIAGRAM
PCI 33MHz
Intel Yonah
REF 14MHz uFCPGA 478
D Page 2 D


Page 3, 4
+3VPCU

3V / 5V +5VPCU FSB
533/667
+3V_S5 LVDS
ChannelA
+5V_S5
DDR2 SO-DIMM0 NB RGB LVDS LCD Panel
+3VSUS Page 9 DDR2 533/667
PCIE x16 Ext. VGA TV
17" WXGA/WSXGA+
+5VSUS
Calistoga NVIDIA / ATI
TMDS
Page 14

Page 13
+3V ChannelB XM/PM/GM RGB
DDR2 SO-DIMM1 FCBGA 1466
LVDS SWITCH CRT Page 14
+5V
Page 9 DDR2 533/667 CIRCUIT
RGB
+12VOUT
Page 24 TV TV S-VIDEO Page 14
+1.8VSUS
1.8V / SDVO
C SMDDR_VTERM DVI Encoder TMDS C

1.05V +1.05V Page 5, 6, 7, 8 CH7307 Page 13 Page 14
TMDS DVI Page 14
Page 26
DMI
+2.5V
2.5V Page 27 SATA
HDD Page 19 PCI PCMCIA Card Slot
+1.5V PATA SB PCIE x1 ANT
TI PCI7412
1.5V Page 28 ODD Page 19
REQ0#, GNT0# 1394
USB2.0 ICH7-M USB2.0
MINI CARD AD20
INTB#, INTC#,
CPU +VCC_CORE ANT USB PORT x4 Intel Golan INTD#
Page 18 PCIE1 Page 18 Page 15, 16 5-in-1 Slot
BGA 652
CORE Page 25 USB2.0
Bluetooth 2.0 PCIE x1
Page 18
BATTERY USB2.0 USB2.0
NEW CARD
VIN Fingerprint Power
CHARGER Sensor Page 18 PCIE2 Page 18 Switch
Page 29
B B
IO BASE ADDRESS
PCIE x1 LAN Transformer EC 0x002E
Power State Table Intel 82573L RJ45 TPM 0x004E
Page 17
Power Control Power MIC IN PCIE0 Page 17 SIO1000 0x162E
Name Signal State AMC Azalia DEBUG 0x164E
CONEXANT
+3VPCU N/A ALWAYS LINE IN CX20551 LCI LAN MB ID Definition
+3V_S5 S5_ON S0 - S5 Intel 82562GZ MBID2 MBID1 MBID0
+3VSUS SUSON S0 - S3 Page 20
Page 10, 11, 12 Page 17 0 : 100 LAN
+3V MAINON S0 1 : GIGA Reserved Reserved
LPC LAN
+5VPCU N/A ALWAYS HP OUT
+5V_S5 S5_ON S0 - S5 SPDIF
AUDIO Value Prefix List :
[email protected] : Components For External VGA
+5VSUS SUSON S0 - S3 AMP [email protected] : Components For Internal VGA
+5V MAINON S0
Speaker
MAX9750 TPM SIO EC BIOS [email protected] : Components For Gigabit Ethernet
Page 20 [email protected] : Components For Fast Ethernet
+12VOUT MAINON S0 SMSC
SIO1000 NS PC87541 [email protected] : Components For CIR
[email protected] : Components For ExpressCard
+1.8VSUS SUSON S0 - S3 Page 21 Page 21 K/B
A
SMDDR_VTERM MAINON S0
DAA [email protected] : Components For FingerPrint
[email protected] : Components For DVI Function
A


CONEXANT [email protected] : Components For Internal VGA DVI Fucntion
+1.05V MAINON S0 RJ11
CX20493 Value show with Prefix " * " means unstuff parts
Page 20 CIR Page 22 Touch Pad
+1.5V MAINON S0
PROJECT :BD1
+2.5V MAINON S0 Quanta Computer Inc.
+VCC_CORE VRON S0 Size Document Number Rev
BLOCK DIAGRAM 3B
Date: Monday, December 12, 2005 Sheet 1 of 32
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5 4 3 2 1

HCLK_CPU R118 49.9/F_4
U7 ICS954310 HCLK_CPU# R119 49.9/F_4
VRM_CLKEN# 10 52 HCLK_CPU_R 1 2 RP15 HCLK_CPU
(11,25) VRM_CLKEN# PM_STPCPU# VTT_PWRGD//PD CPUCLKT0 HCLK_CPU# HCLK_CPU (3) HCLK_MCH
62 51 HCLK_CPU_R# 3 4 33_4P2R_4 R120 49.9/F_4
(11) PM_STPCPU# PM_STPPCI# CPU_STOP CPUCLKC0 HCLK_CPU# (3) HCLK_MCH#
63 R121 49.9/F_4
(11) PM_STPPCI# PCI_PCIE_STOP HCLK_MCH
49 HCLK_MCH_R 1 2 RP16
NEW_CLKREQ# CPUCLKT1 HCLK_MCH# HCLK_MCH (5) PECLK_VGA
32 48 HCLK_MCH_R# 3 4 33_4P2R_4 R122 [email protected]/F_4
(18) NEW_CLKREQ# MINI_CLKREQ# PEREQ3 CPUCLKC1 HCLK_MCH# (5) PECLK_VGA#
33 R123 [email protected]/F_4
(18) MINI_CLKREQ# PEREQ4
CPUCLKT2_ITP//PCIEXT8 44
CGDAT_SMB 55 43 PECLK_LAN R124 [email protected]/F_4
CGCLK_SMB SDATA CPUCLKC2_ITP//PCIEXC8 PECLK_LAN# R125 [email protected]/F_4
54 SCLK
D
PEREQ2//PCIEXC7 40 D
34 41 PECLK_NEW R192 [email protected]/F_4
T103 PWRSAVE PEREQ1//PCIEXT7 PECLK_NEW# R193 [email protected]/F_4
R402 475/F_6 CG_IREF 47 39 PECLK_VGA_R 1 2 RP17 PECLK_VGA
IREF PCIEXT6 PECLK_VGA# PECLK_VGA (13) PECLK_SATA R190
38 PECLK_VGA_R# 3 4 [email protected]_4P2R_4 49.9/F_4
VDD_SRC_CPU PCIEXC6 PECLK_VGA# (13) PECLK_SATA# R191
L41 HB-1T2012-121JT 50 49.9/F_4
+3V VDDCPU PECLK_LAN
21 36 PECLK_LAN_R 1 2 RP18
VDDPCIE1 PCIEXT5 PECLK_LAN# PECLK_LAN (17) PECLK_MINI
C468 C473 C488 C475 C487 28 35 PECLK_LAN_R# 3 4 [email protected]_4P2R_4 R188 49.9/F_4
VDDPCIE2 PCIEXC5 PECLK_LAN# (17) PECLK_MINI#
42 R189 49.9/F_4
10U/10V_8 .1U_4 .1U_4 .1U_4 .1U_4 VDDPCIE3 PECLK_NEW_R PECLK_NEW
PCIEXT4 30 3 4 RP51 PECLK_NEW (18)
31 PECLK_NEW_R# 1 2 [email protected]_4P2R_4 PECLK_NEW# PECLK_ICH R186 49.9/F_4
PCIEXC4 PECLK_NEW# (18) PECLK_ICH# R187 49.9/F_4
R393 2.2_6 VDDA_CK 45 26 PECLK_SATA_R 3 4 RP50 PECLK_SATA
VDDA SATACLKT PECLK_SATA# PECLK_SATA (10) PECLK_MCH
27 PECLK_SATA_R# 1 2 33_4P2R_4 R426 49.9/F_4
SATACLKC PECLK_SATA# (10) PECLK_MCH# R425
C467 C474 49.9/F_4
24 PECLK_MINI_R 3 4 RP49 PECLK_MINI
PCIEXT3 PECLK_MINI# PECLK_MINI (18) DREFCLK_SS R184
10U/10V_8 .1U_4 25 PECLK_MINI_R# 1 2 33_4P2R_4 [email protected]/F_4
PCIEXC3 PECLK_MINI# (18) DREFCLK_SS# R185 [email protected]/F_4
1 22 PECLK_ICH_R 3 4 RP48 PECLK_ICH
VDD_PCI VDDPCI1 PCIEXT2 PECLK_ICH# PECLK_ICH (10) DREFCLK
L43 HB-1T2012-121JT 7 23 PECLK_ICH_R# 1 2 33_4P2R_4 R182 49.9/F_4
+3V VDDPCI2 PCIEXC2 PECLK_ICH# (10) DREFCLK# R183 49.9/F_4
C492 C490 C491 19 PECLK_MCH_R 1 2 RP71 PECLK_MCH
PCIEXT1 PECLK_MCH# PECLK_MCH (5)
20 PECLK_MCH_R# 3 4 33_4P2R_4
PCIEXC1 PECLK_MCH# (5)
10U/10V_8 .1U_4 .1U_4
17 DREFCLK_SS_R 3 4 RP47 DREFCLK_SS
C 27FIX//LCD_SSCGT//PCIEX0T DREFCLK_SS# DREFCLK_SS (5) PCLK_TPM C
18 DREFCLK_SS_R# 1 2 [email protected]_4P2R_4 C219 *10P_4
VDD_48M 27SS//LCD_SSCGC//PCIEX0C DREFCLK_SS# (5) PCLK_PCM
R422 2.2_6 11 C187 *10P_4
VDD48 DREFCLK_R DREFCLK PCLK_SIO
DOTT_96M 14 3 4 RP52 DREFCLK (5)
C108 *10P_4
C496 C489 15 DREFCLK_R# 1 2 33_4P2R_4 DREFCLK# PCLK_EC C221 *10P_4
DOTC_96M DREFCLK# (5) PCLK_ICH C220 *10P_4
10U/10V_8 .1U_4 14M_ICH C110 *10P_4
5 SELPCIE0 R420 *33_4 PCLK_DEBUG 14M_SIO C109 *10P_4
SELPCIEX0//PCICLK5 PCLK_TPM_R PCLK_TPM PCLK_DEBUG (18) 48M_USB
11/30 Add C647~C653 4 R173 *33_4 C222 *10P_4
VDDREF_CK PCICLK4 PCLK_PCM PCLK_TPM (21)
R392 1_6 56 3 PCLK_PCM_R R172 33_4
Reserved, no need to stuff VDDREF PCICLK3 PCLK_SIO_R R135 33_4 PCLK_SIO PCLK_PCM (15)
PCICLK2//REQ_SEL 64 PCLK_SIO (21)
C469 C476 9 PCLK_EC_R R175 33_4 PCLK_EC
VIN +1.05V SELLCD_27//PCICLK_F1 PCLK_ICH PCLK_EC (22)
8 PCLK_ICH_R R174 33_4
ITP_EN//PCICLK_F0 PCLK_ICH (11)
10U/10V_8 .1U_4 2 GND1 +3V
6 GND2
C647 *.1U_4 C648 *.1U_4 13 60 14M_REF0 R138 33_4 14M_ICH
+3V GND3 REF0 14M_ICH (11) MINI_CLKREQ# R540
29 10K_4
GND4
37 GND5
53 61 FSB_SELC R137 33_4 14M_SIO NEW_CLKREQ# R177 10K_4
GND6 REF1//FSC//TEST_SEL FSB_SELB 14M_SIO (21)
C651 *.1U_4 59 16
C649 C650 C652 C653 GND7 FSB//TEST_MODE FSB_SELA R176 33_4 48M_USB R423 10K_4
46 12
X1




X2
GNDA FSA//USB_48M 48M_USB (11)
*.1U_4 *.1U_4 *.1U_4 *.1U_4
PCLK_EC_R R415 *10K_4
58




57
Y2 DREFCLK_SS_R R414 *33_4 27M_VGA
+1.5V 27MSS_VGA 27M_VGA (13) SELPCIE0
14.318MHz DREFCLK_SS_R# R413 *33_4 R416 10K_4
27MSS_VGA (13)
B CL = 20pF B
PCLK_ICH_R R181 10K_4

Q14 2N7002E C138 C168
3 1 CGCLK_SMB
(11,17,18) PCLK_SMB CGCLK_SMB (9)
33P_4 33P_4
R115 10K_4
PEREQ Control Pair
2




+3V +3V
PEREQ1 PECLK Pair0, 6
2




R134 10K_4 FSC FSB FSA CPU SRC PCI FSC FSB FSA CPU SRC PCI
PEREQ2 PECLK Pair1, 8
3 1 CGDAT_SMB
(11,17,18) PDAT_SMB CGDAT_SMB (9)
PEREQ3 PECLK Pair2, 4 1 0 1 100 100 33 0 1 0 200 100 33
Q15 2N7002E
PEREQ4 PECLK Pair3, 5, 7 0 0 1 133 100 33 0 0 0 266 100 33
0 1 1 166 100 33 1 0 0 333 100 33
+1.05V +1.05V +1.05V 1 1 1 200 100 33 1 1 0 400 100 33

R434 R429 R390

*56.2/F_4 *1K_4 *1K_4
A A

R432 0_4 R431 4.7K_4 FSB_SELA R427 0_4 FSB_SELB R136 0_4 R388 4.7K_4 FSB_SELC
(3) CPU_BSEL0 (3) CPU_BSEL1 (3) CPU_BSEL2
R435 1K_4 R430 1K_4 R389 1K_4
(5) MCH_BSEL0 (5) MCH_BSEL1 (5) MCH_BSEL2 PROJECT :BD1
R433 R428 R116
Quanta Computer Inc.
*1K_4 *0_4 *0_4
Size Document Number Rev
CLOCK GENERATOR 3B
Date: Monday, December 12, 2005 Sheet 2 of 32
5 4 3 2 1
5 4 3 2 1



U21A
HA#3 J4 H1 H_ADS#
(5) HA#3 HA#4 A[3]# ADS# H_BNR# H_ADS# (5)
(5) HA#4 L4 A[4]# BNR# E2 H_BNR# (5) (5) HD#[15..0] HD#[47..32] (5)
HA#5 M3 G5 H_BPRI# U21B
(5) HA#5 HA#6 A[5]# BPRI# H_BPRI# (5) HD#0 HD#32
(5) HA#6 K5 A[6]# E22 D[0]# D[32]# AA23
HA#7 M1 H5 H_DEFER# HD#1 F24 AB24 HD#33
(5) HA#7 A[7]# DEFER# H_DEFER# (5) D[1]# D[33]#




ADDR GROUP 0
HA#8 N2 F21 H_DRDY# HD#2 E26 V24 HD#34
(5) HA#8 HA#9 A[8]# DRDY# H_DRDY# (5) D[2]# D[34]#
(5) HA#9 J1 A[9]# DBSY# E1 H_DBSY# H_DBSY# (5)
HD#3 H22 D[3]# D[35]# V26 HD#35




DATA GRP 0
HA#10 HD#4 HD#36




CONTROL
N3 F23 W25




DATA GRP 2
(5) HA#10 HA#11 A[10]# H_BREQ#0 HD#5 D[4]# D[36]#
P5 F1 G25 U23 HD#37
(5) HA#11 HA#12 A[11]# BR0# H_BREQ#0 (5) HD#6 D[5]# D[37]# HD#38
(5) HA#12 P2 A[12]# E25 D[6]# D[38]# U25
HA#13 L1 D20 H_IERR# HD#7 E23 U22 HD#39
(5) HA#13 HA#14 A[13]# IERR# D[7]# D[39]#
D
(5) HA#14 P4 A[14]# INIT# B3 H_INIT# H_INIT# (10)
HD#8 K24 D[8]# D[40]# AB25 HD#40 D
HA#15 P1 HD#9 G24 W22 HD#41
(5) HA#15 HA#16 A[15]# H_LOCK# D[9]# D[41]# HD#42
R1 H4 HD#10 J24 Y23
(5) HA#16 HADSTB0# A[16]# LOCK# H_LOCK# (5) HD#11 D[10 D[42]# HD#43
(5) HADSTB0# L2 ADSTB[0]# J23 D[11]# D[43]# AA26
B1 H_CPURST# HD#12 H26 Y26 HD#44
HREQ#0