Text preview for : saa5281.pdf part of Philips SAA5281 Integrated video input processor & teletext decoder
Back to : saa5281.pdf | Home
INTEGRATED CIRCUITS
DATA SHEET
SAA5281 Integrated Video input processor and Teletext decoder (IVT1.8*)
Preliminary specification Supersedes data of June 1994 File under Integrated Circuits, IC02 1996 Nov 04
Philips Semiconductors
Preliminary specification
Integrated Video input processor and Teletext decoder (IVT1.8*)
FEATURES · Complete Teletext and VPS decoding in a single package · Built-in 8K × 8 memory for up to 8 page storage · Enhanced mode allows 7 Fastext pages and 8 pages of TOP to be captured · Ability to request only subtitle pages · Acquisition and decoding of VPS data · Data valid output available to indicate reception of error-free VPS or packet 8/30/2 data · Software and hardware compatible with SAA5246 and SAA5248 · Meshing display within boxes · Separate data checking algorithms and pointers for each acquisition channel · 24 : 18 Hamming checker · Automatic packet 26 extension character processing · Indication of Line 23 for external use · 13.5 MHz clock output to drive external microcontroller · Detection of Spanish transmissions to disable flicker-stopper · Compatible with Philips' one-chip TV IC (TDA836X) for scan-locking applications. QUICK REFERENCE DATA SYMBOL VDD IDD Vsync Vvid(p-p) fxtal Tamb supply voltage supply current sync voltage amplitude video input voltage amplitude (peak-to-peak value) crystal frequency operating ambient temperature PARAMETER 4.5 - 0.1 0.7 - -20 MIN. 5.0 75 0.3 1.0 27 - TYP. DESCRIPTION
SAA5281
The IVT1.8* is a single-chip Teletext decoder IC for decoding 625-line based World System Teletext transmissions. The device is based on IVT1.0VPS and has reception facilities for the 5 MHz biphase VPS signal. It is intended for use in video recorders, in particular to implement the VPT facility (VCR programming via Teletext). With suitable software both VPT standards (EBU PDC System A and System B) can be accommodated to allow operation from any European VPT transmission. Automatic processing of packet 26 transmissions is also possible. No external memory is required as an 8K × 8 DRAM is included on-chip for up to 8 page storage. An enhanced mode allows 7 Fastext pages to be stored, with one chapter used to store extension packets.
MAX. 5.5 150 0.6 1.4 - +70 V
UNIT mA V V MHz °C
ORDERING INFORMATION PACKAGE TYPE NUMBER NAME SAA5281P SAA5281ZP SAA5281GP DIP48 SDIP52 QFP64 DESCRIPTION plastic shrink dual in-line package; 32 leads (400 mil) plastic shrink dual in-line package; 52 leads (600 mil) plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 × 20 × 2.8 mm VERSION SOT240-1 SOT247-1 SOT319-2
1996 Nov 04
2
Philips Semiconductors
Preliminary specification
Integrated Video input processor and Teletext decoder (IVT1.8*)
BLOCK DIAGRAM
SAA5281
handbook, full pagewidth
V DD1
VDD2
Y
BLAN RGBREF COR R 22 19 20 18 15
G 16
B 17 DRAM REFRESH AND TIMING
1
10
POWER-ON RESET
DISPLAY
8K x 8 DRAM
ODD/EVEN (or DV)
21
24 TO 18 HAMMING DECODER
PACKET 26 PROCESSING ENGINE
MEMORY INTERFACE
TELETEXT AQUISITION AND DECODING VPS ACQUISITION AND DECODING
24 I 2 C-BUS INTERFACE 23
SDA SCL
SERIAL-TO -PARALLEL CONVERTER
44
SAA5281
TIMING CHAIN
LINE 23
DATA SLICER AND CLOCK REGENERATOR
TELETEXT OR VPS CONTROL
DISPLAY CLOCK PHASE-LOCKED LOOP
13 11
VCR/FFB
REF
6 37 9 ANALOG REFERENCE GENERATOR ANALOG TO DIGITAL CONVERTER 25 8 CVBS INPUT CLAMP AND SYNC SEPARATOR 7 BLACK ANALOG OUTPUT BUFFER 27 MHz CLOCK GENERATOR 4
POL CLK O/P
IREF
OSCGND
5
14
12 STTV/LFB
36
2
3
MBD783
V SS1 VSS2
V SS3
CLK EN OSCIN OSCOUT
Fig.1 Block diagram; pin numbers for DIP48 (SOT240-1).
1996 Nov 04
3
Philips Semiconductors
Preliminary specification
Integrated Video input processor and Teletext decoder (IVT1.8*)
PINNING PIN SYMBOL SOT240-1 SOT247-1 SOT319-2 VDD1 OSCOUT OSCIN OSCGND VSS1 REF+ BLACK CVBS IREF VDD2 POL STTV/LFB VCR/FFB VSS2 R G B RGBREF BLAN COR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 52 1 2 3 4 and 5 6 8 9 10 11 12 13 14 15 16 17 18 19 20 21 11 13 14 15 16 18 19 20 21 22 23 24 27 28 30 32 33 34 35 36 +5 V supply 1 27 MHz crystal oscillator output 27 MHz crystal oscillator input 0 V crystal oscillator ground 0 V ground DESCRIPTION
SAA5281
positive reference voltage for ADC; this pin should be connected to ground via a 100 nF capacitor video black level storage input/output; this pin should be connected to ground via a 100 nF capacitor composite video input; a positive-going 1 V (peak-to-peak) input is required, connected via a 100 nF capacitor reference current input, connected to ground via a 27 k resistor +5 V supply 2 STTV/LFB/FFB polarity selection input sync to TV output line flyback input; function controlled by an internal register bit (scan sync mode) PLL time constant switch/field input; function controlled by an internal register bit (scan sync mode) 0 V ground; connected to VSS1 for normal operation dot rate character output of the RED colour information dot rate character output of the GREEN colour information dot rate character output of the BLUE colour information input DC voltage to define the output high level on the RGB pins dot rate fast blanking output programmable output to provide contrast reduction of the TV picture for mixed text and picture displays or when viewing newsflash/subtitle pages; open-drain output in ODD/EVEN mode a 25 Hz output synchronized with the CVBS input field sync pulses to produce a non-interlaced display by adjustment of the vertical deflection currents; in DV mode a VPT data valid signal is used to indicate reception of error-free VPS or 8/30 format 2 data dot rate character output of teletext foreground colour information; open-drain output serial clock input for I2C-bus; it can still be driven HIGH during power-down of the device serial data port for the I2C-bus, open-drain output; it can still be driven HIGH during power-down of the device 0 V ground
ODD/EVEN (or DV)
21
22
37
Y SCL SDA VSS3
22 23 24 25
23 24 25 26
38 39 40 44
1996 Nov 04
4
Philips Semiconductors
Preliminary specification
Integrated Video input processor and Teletext decoder (IVT1.8*)
PIN SYMBOL SOT240-1 SOT247-1 SOT319-2 i.c. 26 to 35, 38 to 43, 45 to 48 27 to 32, 35 to 38, 41 to 46, 48 to 51 39 40 47 7, 33, 34 1 to 3, 5 to 8, 45 to 53, 55, 61, 63 to 64 56 59 4 internally connected; normally open-circuit DESCRIPTION
SAA5281
CLK EN CLK O/P LINE 23 n.c.
36 37 44 -
clock enable input to enable the clock output (CLP O/P pin 37); internal pull-down normally disables clock 13.5 MHz clock output to drive an external microcontroller output for indication of Line 23 for use with external circuitry
9, 10, 12, not connected; normally open-circuit 17, 25, 26, 29, 31, 41 to 43, 54, 57, 58, 60, 62
1996 Nov 04
5
Philips Semiconductors
Preliminary specification
Integrated Video input processor and Teletext decoder (IVT1.8*)
SAA5281
handbook, halfpage
OSCOUT
handbook, halfpage
1 2 3 4 5 6 7 8 9 10 11 12 SAA5281 13 14 15 16
52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
MBD785
V DD1 i.c. i.c. i.c. i.c. LINE 23 i.c. i.c. i.c. i.c. i.c. i.c. CLK O/P CLK EN i.c. i.c. i.c. i.c. n.c. n.c. i.c. i.c. i.c. i.c. i.c. i.c.
VDD1
1 2 3 4 5 6 7 8 9 10 11 12 SAA5281 13 14 15 16 17 18 19 20 21 22 23 24
MBD784
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
i.c. i.c. i.c. i.c. LINE 23 i.c. i.c. i.c. i.c. i.c. i.c. CLK O/P CLK EN i.c. i.c. i.c. i.c. i.c. i.c. i.c. i.c. i.c. i.c. V SS3
OSCIN OSCGND V SS1 V SS1 REF+ n.c. BLACK CVBS IREF V DD2 POL STTV/LFB VCR/FFB V SS2 R
OSCOUT OSCIN OSCGND V SS1 REF+ BLACK CVBS IREF V DD2 POL STTV/LFB VCR/FFB V SS2 R G B RGBREF BLAN COR ODD/EVEN (or DV) Y SCL SDA
G 17 B 18 RGBREF BLAN COR ODD/EVEN (or DV) Y SCL SDA 19 20 21 22 23 24 25
V SS3 26
Fig.2 Pin configuration; SOT240-1 (DIP48).
Fig.3 Pin configuration; SOT247-1 (SDIP52).
1996 Nov 04
6
Philips Semiconductors
Preliminary specification
Integrated Video input processor and Teletext decoder (IVT1.8*)
SAA5281
56 CLK EN
handbook, full pagewidth
59 CLK O/P
62 n.c.
60 n.c.
58 n.c.
57 n.c.
54 n.c.
64 i.c.
63 i.c.
61 i.c.
55 i.c.
53 i.c.
i.c. i.c. i.c. LINE 23 i.c. i.c. i.c. i.c. n.c.
1 2 3 4 5 6 7 8 9
52 i.c. 51 i.c. 50 i.c. 49 i.c. 48 i.c. 47 i.c. 46 i.c. 45 i.c. 44 VSS3 43 n.c. 42 n.c. 41 n.c. 40 SDA 39 SCL 38 Y 37 ODD/EVEN (or DV) 36 COR 35 BLAN 34 RGBREF 33 B G 32
MBH665
n.c. 10 VDD1 11 n.c. 12 OSCOUT 13 OSCIN 14 OSCGND 15 VSS1 16 n.c. 17 REF+ 18 BLACK 19 CVBS 20 IREF 21 VDD2 22 POL 23 STTV/LFB 24
SAA5281
n.c. 25
n.c. 26
VCR/FFB 27
VSS2 28
n.c. 29
R 30
Fig.4 Pin configuration; SOT319-2 (QFP64).
1996 Nov 04
7
n.c. 31
Philips Semiconductors
Preliminary specification
Integrated Video input processor and Teletext decoder (IVT1.8*)
QUALITY AND RELIABILITY
SAA5281
This device will meet Philips Semiconductors General Quality Specification for Business group "Consumer Integrated Circuits SNW-FQ-611-Part E". The principal requirements are shown in Tables 1 to 4. Group A Table 1 Acceptance tests per lot TEST Mechanical Electrical Group B Table 2 Processability tests (by package family) TEST Solderability Mechanical Solder heat resistance Group C Table 3 Reliability tests (by process family) TEST Operational life Humidity life CONDITIONS 168 hours at Tj = 150 °C temperature, humidity, bias 1000 hours, 85 °C, 85% RH (or equivalent test) Tstg(min) to Tstg(max) REQUIREMENTS(1) <1500 FPM; equivalent to <100 FITS at Tj = 70 °C <2000 FPM <7% LTPD <15% LTPD <15% LTPD REQUIREMENTS(1) cumulative target: <100 ppm cumulative target: <100 ppm REQUIREMENTS(1)
Temperature cycling performance Table 4
<2000 FPM
Reliability tests (by device type) TEST CONDITIONS ESD Human body model 2000 V, 100 pF, 1.5 k ESD Machine model 200 V, 200 pF, 0 latch-up 100 mA, 1.5 × VDD (absolute maximum) REQUIREMENTS(1) <15% LTPD <15% LTPD <15% LTPD
ESD and latch-up
Notes to Tables 1 to 4 1. ppm = fraction of defective devices, in parts per million. LTPD = Lot Tolerance Percent Defective. FPM = fraction of devices failing at test condition, in Failures Per Million. FITS = Failures In Time Standard.
1996 Nov 04
8
Philips Semiconductors
Preliminary specification
Integrated Video input processor and Teletext decoder (IVT1.8*)
LIMITING VALUES In accordance with Absolute Maximum Rating System (IEC 134). SYMBOL VDD VI VO IO IIOK Tamb PARAMETER supply voltage (all supplies) input voltage (any input) output voltage (any output) output current (each output) DC input or output diode current operating ambient temperature -0.3 -0.3 -0.3 - - -20 MIN. +6.5 VDD + 0.5 VDD + 0.5 ±10 ±20 +70 MAX.
SAA5281
UNIT V V V mA mA °C
CHARACTERISTICS VDD = 5 V ±10%; Tamb = -20 to +70 °C; pin numbers refer DIP48 package; unless otherwise specified. SYMBOL Supplies VDD IDDtot Inputs CVBS Vsync Vburst(p-p) td(sync) sync voltage amplitude colour burst amplitude (peak-to-peak value) delay from CVBS to TCS output from STTV buffer (nominal video, average of leading/trailing edge) change in sync delay between all black and all white video input at nominal levels video input voltage amplitude (peak-to-peak value) teletext data voltage amplitude display PLL capture range source impedance input switching voltage level of sync separator input impedance input capacitance 0.1 0.0 -150 0.3 0.3 0 0.6 4.0 +150 V V ns supply voltage total supply current 4.5 - 5.0 75 5.5 150 V mA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
td(sync)
0
-
25
ns
Vvid(p-p) Vdat(text) f/f Zsource VI ZI CI IREF Rgnd Vi
0.7 0.29 ±7 - 1.7 2.5 - - -
1.0 0.46 - - 2.0 5.0 - 27 0.5VDD
1.4 0.71 - 250 2.3 - 10 - -
V V % V k pF
resistor to ground input voltage
k V
1996 Nov 04
9
Philips Semiconductors
Preliminary specification
Integrated Video input processor and Teletext decoder (IVT1.8*)
SYMBOL POL VIL VIH ILI CI LFB VIL VIH ILI IImax tdLFB VCR/FFB VIL VIH ILI IImax RGBREF VIL ILI SCL VIL VIH ILI CI fclk tr tf LOW level input voltage HIGH level input voltage input leakage current input capacitance clock frequency input rise time input fall time VI = 0 to VDD -0.3 3.0 -10 - 0 between 10% and 90% - between 90% and 10% - - - - - - - - +1.5 +10 10 100 2 2 LOW level input voltage input leakage current VI = 0 to VDD -0.3 -10 - - VDD +10 LOW level input voltage HIGH level input voltage input leakage current maximum input current VI = 0 to VDD note 1 -0.3 2.0 -10 -1 - - - - +0.8 +10 +1 LOW level input voltage HIGH level input voltage input leakage current maximum input current delay between LFB front edge and input video line sync VI = 0 to VDD note 1 -0.3 tbf -10 -1 - - - - - 250 tbf +10 +1 - LOW level input voltage HIGH level input voltage input leakage current input capacitance VI = 0 to VDD -0.3 2.0 -10 - - - - - +0.8 +10 10 PARAMETER CONDITIONS MIN. TYP.
SAA5281
MAX.
UNIT
V µA pF
VDD + 0.5 V
V µA mA ns
VDD + 0.5 V
V µA mA
VDD + 0.5 V
V µA V µA pF kHz µs µs
VDD + 0.5 V
Inputs/outputs CRYSTAL OSCILLATOR (OSCIN; OSCOUT) Vosc(p-p) Gv Gm CI Cfb oscillator voltage amplitude (peak-to-peak value) small signal voltage gain mutual conductance input capacitance feedback capacitance - - 5.0 - - 1.0 1.0 - - 1 - - - 10 - mS pF pF V
1996 Nov 04
10
Philips Semiconductors
Preliminary specification
Integrated Video input processor and Teletext decoder (IVT1.8*)
SYMBOL BLACK Cblack Vblack ILI VIL VIH VOL ILI CI CL tr tf tf Outputs STTV Gsttv Vtcs Vtcs IO CL R, G AND B VOL VOH LOW level output voltage HIGH level output voltage IOL = 2 mA IOH = -1.6 mA; VRGBREF < VDD - 2 V; note 2 0 VRGBREF - 0.25 - - between 10% and 90% - between 90% and 10% - IOL = 1.6 mA IOH = - 0.2 mA IOH = 0 mA CL tr tf load capacitance output rise time output fall time 0 1.1 - - between 10% and 90% - between 90% and 10% - - VRGBREF 0.2 gain of STTV relative to video input TCS voltage amplitude DC shift between TCS output and nominal video output output drive current load capacitance 0.9 0.2 - - - 1.0 0.3 - - - 1.1 0.45 0.15 3.0 100 storage capacitor to ground black level voltage for nominal sync amplitude input leakage current VI = 0 to VDD - 1.8 -10 -0.3 3.0 IOL = 3 mA VI = 0 to VDD 0 -10 - - between 10% and 90% - between 90% and 10% - between 3 V and 1 V - 100 2.15 - - - - - - - - - - - 2.5 +10 PARAMETER CONDITIONS MIN. TYP.
SAA5281
MAX.
UNIT
nF V µA V V µA pF pF µs µs ns
SDA (OPEN-DRAIN INPUT/OUTPUT) LOW level input voltage HIGH level input voltage LOW level output voltage input leakage current input capacitance load capacitance input rise time input fall time output fall time +1.5 0.5 +10 10 400 2 2 200 VDD + 0.5 V
V V mA pF
V V
VRGBREF + 0.5 200 50 20 20
|Zo| CL tr tf BLAN VOL VOH
output impedance load capacitance output rise time output fall time
- - - - - - - - - -
pF ns ns
LOW level output voltage HIGH level output voltage
0.4 - 2.8 50 20 20
V V V pF ns ns
1996 Nov 04
11
Philips Semiconductors
Preliminary specification
Integrated Video input processor and Teletext decoder (IVT1.8*)
SYMBOL ODD/EVEN OR DV VOL VOH CL tr tf LOW level output voltage HIGH level output voltage load capacitance output rise time output fall time between 0.6 V and 2.2 V between 0.6 V and 2.2 V IOL = 1.6 mA IOH = -1.6 mA 0 VDD - 0.4 - - - - - - - - 0.4 VDD 120 50 50 PARAMETER CONDITIONS MIN. TYP.
SAA5281
MAX.
UNIT
V V pF ns ns
COR AND Y (OPEN-DRAIN OUTPUTS) VOH VOL CL tf HIGH level pull-up output voltage LOW level output voltage load capacitance output fall time load resistor of 1.2 k to VDD; measured between VDD - 0.5 V and 1.5 V VI = 0 to VDD IOL = 2 mA IOL = 5 mA - 0 0 - - - - - - - VDD 0.4 1.0 25 50 V V V pF ns
ILO tskew
output leakage current skew delay between display outputs R, G, B, COR, Y and BLAN
-10 -
- -
+10 20
µA ns
I2C-bus timing (see Fig.5) tLOW tHIGH tSU;DAT tHD;DAT tSU;STO tBUF tHD;STA tSU;STA Notes 1. This current is the maximum allowed into the inputs when line and field flyback signals are connected to these inputs. Series current limiting resistors must be used to limit the input currents to ±1 mA. 2. Voltage level VOH for R, G and B outputs is taken to be the mean value during the output HIGH time. If higher R, G and B voltage VOH levels are required RGBREF voltage level may be raised and a pull-up resistor used at each of these pins provided current specification (IOL) is not exceeded. SCL clock LOW time SCL clock HIGH time data set-up time data hold time set-up time from clock HIGH to STOP START set-up time following a STOP START hold time START set-up time following a clock LOW-to-HIGH transition 4.0 4.0 250 170 4.0 4.0 4.0 4.0 - - - - - - - - - - - - - - - - µs µs ns ns µs µs µs µs
1996 Nov 04
12
Philips Semiconductors
Preliminary specification
Integrated Video input processor and Teletext decoder (IVT1.8*)
SAA5281
handbook, full pagewidth
SDA
t BUF
t LOW
tf
SCL t HIGH t SU;DAT
t HD;STA
tr
t HD;DAT
SDA
MBC764
t SU;STA
t SU;STO
Fig.5 I2C-bus timing.
TIMING CHAIN
handbook, full pagewidth LSP
(TCS) 0 4.66 40 µs R, G, B, Y (1) 0 16.67 display period 56.67 µs 64 µs
lines 42 to 291 inclusive (and 355 to 604 inclusive interlaced) R, G, B, Y (1) 0 41 display period 312 291 line numbers
MLA662 - 1
(1) Also BLAN in character and box blanking.
Fig.6 Display output timing (a) line rate (b) field rate.
1996 Nov 04
13
LSP, EP and BP are combined to give TCS as shown. All timings are measured from falling edge of LSP. Line numbers placed in the middle of the line. Equivalent count numbers in brackets.
Preliminary specification
SAA5281
Fig.7 Composite sync waveforms.
handbook, full pagewidth
1996 Nov 04
64 µs 32 34.33 64 µs 27.33 32 59.33 64 µs
0
4.66
Philips Semiconductors
LSP (Line Sync Pulse)
0 2.33
EP (Equalizing Pulse)
0
BP (Broad Pulse)
Integrated Video input processor and Teletext decoder (IVT1.8*)
621 (308) 622 (309) 1 2 3 4 5
623 (310)
624 (311)
625 (312)
6
7
TCS interlaced
14
310 311 312 313 314 (1) 315 (2) 316 (3) 317 (4) 309 310 311 312 1 2 3 4 5
309
318 (5)
319 (6)
320 (7)
TCS interlaced
308
6
7
TCS non-interlaced
MLA037 - 2
FIRST FIELD START (EVEN)
623 (310) 1 7 2 3 4 5 6 624 (311) 625 (312)
Preliminary specification
SAA5281
Fig.8 ODD/EVEN timing.
handbook, full pagewidth
1996 Nov 04
2 µs 48 µs 30 µs (1)
621 (308)
622 (309)
Philips Semiconductors
TCS interlaced
ODD / EVEN output (normal sync mode)
ODD / EVEN output (normal sync mode when VCS to SCS mode active)
ODD / EVEN output (slave sync mode)
Integrated Video input processor and Teletext decoder (IVT1.8*)
SECOND FIELD START (ODD)
311 314 (1) 315 (2) 316 (3) 317 (4) 312 313 318 (5) 319 (6) 320 (7)
309
310
15
2 µs 16 µs 30 µs (1)
TCS interlaced
ODD / EVEN output (normal sync mode)
ODD / EVEN output (normal sync mode when VCS to SCS mode active)
ODD / EVEN output (slave sync mode)
MLA416 - 2
Line numbers placed in the middle of the line. Equivalent count numbers in brackets. (1) Or 62 µs if Register 1 D2.D1.D0 equals 1 1 1.
Philips Semiconductors
Preliminary specification
Integrated Video input processor and Teletext decoder (IVT1.8*)
ON-CHIP MEMORY Page memory organization
SAA5281
The organization of the page memory is illustrated by Fig.9. The IVT1.8* provides an additional row as compared with first generation decoders; this brings the display format up to 40 characters by 25 rows. Rows 0 to 23 form the teletext page; row 24 is the extra row available for software generated status messages and FLOF/FASTEXT prompt information.
handbook, full pagewidth
7 characters for status 7 1
fixed character written by IVT hardware: alphanumerics white for normal; alphanumerics green when looking for display page 24 24 characters from page header rolling when display page looked for
8 characters always rolling (time) 8
ROW 0 1 2 3 4
MAIN PAGE DISPLAY AREA
5 to 20
PACKET X / 22 PACKET X / 23 PACKET X / 24 STORED HERE IF R0D7 = 1 10 14 if enabled 14 bytes reserved in 10 bytes for chapter 5 for VPS data received page information
MBD789
21 22 23 24 25
Fig.9 Basic page memory organization.
REMARK TO Fig.9
Row 25
The first 10 bytes of row 25 contain control data relating to the received page as shown in Table 5. The remaining 14 bytes are free for use by the microcomputer.
Row 0
Row 0 is for the page header. The first seven characters (0 to 6) are free for status messages. Character 8 is an alphanumeric white or green control character, written automatically by IVT1.8* to give a green rolling header when a page is being looked for. The last eight characters are for rolling time.
1996 Nov 04
16
Philips Semiconductors
Preliminary specification
Integrated Video input processor and Teletext decoder (IVT1.8*)
Table 5 Row 25 received control data format ROW 25 D0 D1 D2 D3 D4 D5 D6 D7 Column Table 6 PU0 PU1 PU2 PU3 0 0 0 0 PT0 PT1 PT2 PT3 0 0 0 1 MU0 MU1 MU2 MU3 0 0 0 2 MT0 MT1 MT2 C4 0 0 0 3 HU0 HU1 HU2 HU3 0 0 0 4 HT0 HT1 C5 C6 0 0 0 5 C7 C8 C9 C10 0 0 0 6 C11 C12 C13 C14 0 0 0 7
SAA5281
MAG0 MAG1 MAG2 0 0 0 0 8
0 0 0 0 0 PBLF 0 0 9
HAM.ER HAM.ER HAM.ER HAM.ER HAM.ER HAM.ER HAM.ER HAM.ER FOUND
Page number and sub-code for Table 5 DESCRIPTION
BIT NAME Page number MAG PU PT PBLF FOUND HAM.ER Page sub-code MU MT HU HT C4 to C14 magazine page units page tens
page being looked for LOW for page has been found Hamming error in corresponding byte
minutes units minutes tens hours units hours tens transmitted control bits
1996 Nov 04
17
Philips Semiconductors
Preliminary specification
Integrated Video input processor and Teletext decoder (IVT1.8*)
Extension packet memory organization
SAA5281
When in normal extension packet enabled mode the rows of information are organized as illustrated in Fig.10. Row 23 of the extension page, as shown in Fig.10, contains packet 8/30. Packet 8/30 is mapped into the IVT1.8* memory as follows: 8 / 30 / 0 and 8 / 30 / 1 to Chapter 4 Row 23 8 / 30 / 2 and 8 / 30 / 3 to Chapter 5 Row 23 8 / 30 / 4 to 8 / 30 / 15 to Chapter 6 Row 23.
ROW
handbook, full pagewidth
PACKETS X/26/0 to X/26/14
0 to 14
PACKET
X/28/2
15 16 17 18
PACKETS X/27/0 to X/27/1
PACKETS X/27/4 to X/27/5 PACKET X/24 IF R0D7 = 0 X/25 X/28/0 8/30 X/28/1
19 20 21 22 23 24 25
PACKET PACKET PACKET PACKET
RESERVED (1)
MBD791
(1) Row 25 reserved for VPS data in Chapter 5.
Fig.10 Organization of the extension memory.
1996 Nov 04
18
Philips Semiconductors
Preliminary specification
Integrated Video input processor and Teletext decoder (IVT1.8*)
ENHANCED MODE
SAA5281
In enhanced mode, the number of extension packets captured is reduced to the minimum required for FASTEXT operation. The first seven chapters can then be used for storage, using the system of pointers. The arrangement of extension packets is shown in Fig.11. When in enhanced mode and extension packets are disabled, normal 8-page mode is in operation, but the X/26 engine is enabled (unlike normal 8-page mode).
handbook, halfpage
ROW CHAPTER 0 PACKET 24 CHAPTER 0 PACKETS 27 / 0 CHAPTER 1 PACKET 24 CHAPTER 1 PACKETS 27 / 0 CHAPTER 2 PACKET 24 CHAPTER 2 PACKETS 27 / 0 CHAPTER 3 PACKET 24 CHAPTER 3 PACKETS 27 / 0 CHAPTER 4 PACKET 24 CHAPTER 4 PACKETS 27 / 0 CHAPTER 5 PACKET 24 CHAPTER 5 PACKETS 27 / 0 CHAPTER 6 PACKET 24 CHAPTER 6 PACKETS 27 / 0 not used not used PACKETS 8 / 30 / 0,1 PACKETS 8 / 30 / 2,3 PACKETS 8 / 30 / 4 to 15 not used
MBD788
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 to 24
Fig.11 Organization of the extension memory in enhanced mode.
1996 Nov 04
19
Philips Semiconductors
Preliminary specification
Integrated Video input processor and Teletext decoder (IVT1.8*)
VPT data memory organization To simplify the software for dual-standard VPT decoders, the VPS data from line 16 is stored in row 25 of Chapter 5 of the page memory, and is aligned to match the packet 8/30 format 2 data as far as possible. The 8/30 format 2 packet is Hamming coded and by setting the appropriate register control bit the data is stored after hardware Hamming correction. There are 4 data bits stored in each column address of memory with an additional Hamming error bit. The data equivalent to the VPS signal is found in columns 12 to 19. Although the VPS data is not Hamming protected, it is stored with 4 data bits per column address in the same way with an additional biphase error bit. The extra space in Row 25 is allocated to two more Line 16 words.
SAA5281
They are Word 15 (reserved) and Word 4 (Program Source Identification, ASCII sequential) which may be useful for future applications. Details of the memory organization are shown in Fig.12. The stored data can be read from memory via the I2C-bus in the normal way. Multiple reception/majority error correction of the VPS data is the responsibility of the control software, the device simply stores the data as transmitted after biphase decoding. As both VPS and 8/30/2 signals are stored in separate memory locations, it is possible to deal with future situations where both System A and System B transmissions may be present on the same TV channel, the defaults and level of service chosen by the control software.
handbook, full pagewidth
column 8/30/2 VPS
0 D
1
2
3
4
5
6
7
8
9
10
11 12
13 14
15 16
17 18
19
initial page
b13 b14 b15 b16 b17 b18 b19 b20 b21 b22 b23 b24 b25 B11 B12 B13 B14 B15
received page information
column 8/30/2 VPS
20
21 22
23 24
25 26
27 28
29 30
11 12
13 14
15 16
17 18
19
status display B4 B5
MBD787
Fig.12 Detailed memory organization.
1996 Nov 04
20
Register maps
1996 Nov 04 D6 FREE RUN PLL ACQ ON/OFF EXT PKT ENABLE ACQ CCT A1 - PRD4 - FREEZE HEADER ONLY TEXT OUT TEXT OUT SINGLE/ DOUBLE HEIGHT R3 C3 D3 TEXT IN TEXT IN BOX ON 24 A2 PRD3 PRD2 - PRD1 A1 ACQ CCT A0 0 SC2 SC1 DEW/ FULL FIELD TCS ON T1 T0 SC0 PRD0 A0 AUTO ODD/EVEN DISABLE HDR ROLL CBB SLAVE SYNC DISABLE ODD/EVEN VCR MODE R11/R11B SELECT D5 D4 D3 D2 D1 D0 BANK SELECT A2 - -
IVT1.8* mode registers R0 to R13 are shown in Table 7. R0 to R10, R12 and R13 are WRITE only; R11 is READ/WRITE, R11B is read only. Register map (R3), for page requests, is shown in detail in Table 11.
Table 7
Register map (notes 1 to 4)
REGISTER
Philips Semiconductors
D7
NAME
No.
Advanced control
0
X/24 POS
Mode
1
VCS TO SCS 7 + P/ 8-BIT
Page request address
2
HAM CHECK 27, 8/30
Page request data
3
-
Integrated Video input processor and Teletext decoder (IVT1.8*)
Display chapter
4
-
Display control (normal) BKGND IN CURSOR ON CONCEAL/ REVEAL ON - - R4 C4 D4 - C5 D5 D6 - - TOP/BTM HALF COR OUT COR IN
5
BKGND OUT
BKGND IN
COR OUT
COR IN
PON OUT PON OUT BOX ON 1 to 23 A1
PON IN PON IN BOX ON 0
21 VPS ENABLE CLEAR MEM A2 R2 C2 D2 ROM VER R4 ROM VER R3 ROM VER R2 ROM VER R1 H2 CURSOR FREEZE/ DEVICE IDENT H1 MESHING ENABLE H0 S3 VPS ENABLE POINTS ENABLE S2
Display control (newsflash /subtitle)
6
BKGND OUT
Display mode
7
STATUS BTM/TOP
Active chapter
8
-
A0 R1 C1 D1 ROM VER R0 TEXT SIGNAL QUALITY S1 HAM CHECK 24 : 18 DISABLE PKT X/26 R0 C0 D0 VCS SIGNAL QUALITY S0 AUTO DISPLAY PKT X/24
Cursor row
9
-
Cursor column
10
-
Cursor data
11
D7
Device status
11B 625/525 SYNC
Advanced control 2A
12
H3
Preliminary specification
SAA5281
Advanced control 2B
13
ENHANC MODE
Philips Semiconductors
Preliminary specification
Integrated Video input processor and Teletext decoder (IVT1.8*)
Notes to Table 7
SAA5281
1. The dash (-) indicates these bits are inactive and must be written to logic 0 for future compatibility. 2. Certain registers are auto-incremented following an I2C-bus transmission byte. These are Register R0 to R3, R4 to R7 and R8 to R12 or R13. 3. All bits in Registers R0 to R13 are cleared to logic 0 on power-up except bits D0 and D1 of Registers R1, R5 and R6 which are set to logic 1. 4. All memory is cleared to space (00100000) on power-up, except Row 0 Column 7 Chapter 0, which is alpha white (00000111) as the acquisition circuit is enabled but all pages are on hold. Table 8 Register description FUNCTION
REGISTER BIT D0 TO D7 R0 AVANCED CONTROL - auto-increments to Register 1 R11/R11B SELECT VCR MODE DISABLE ODD/EVEN CBB SLAVE SYNC DISABLE HDR ROLL AUTO ODD/EVEN FREE RUN PLL X/24 POS
Selects reading of R11 if LOW or R11B if HIGH. If logic 1 selects short time constant mode of PLL. Forces ODD/EVEN output LOW when logic 1 (see Table 9). When set will modify internal slave sync timing to allow connection to sandcastle of Philips one-chip TV IC (TDA8362). Stops the display update of rolling time and green rolling header during page requests when logic 1. Time updates on page reception only. If logic 1 then ODD/EVEN output only active when no TV picture displayed (see Table 9). Will force the display PLL to free run at 6 MHz when logic 1. Automatic display of FASTEXT prompt row when logic 1. Will also cause Row 24 data transmitted by packet 26 to be written to display, rather than extension memory.
R1 MODE - auto-increments to Register 2 T0, T1 TCS ON DEW/FULL FIELD EXT PKT ENABLE ACQ ON/OFF 7 + P/8-BIT VCS TO SCS Interlace/non-interlace 312/313 line control (see Table 10). Text composite sync or direct sync select (see Table 10 for FFB mode selection). Field-flyback or full-channel mode. Enables reception and storage of extension packets when logic 1. Acquisition circuits turned off when logic 1. 7 bits with parity checking or 8-bit mode. Connects VCS from video sync separator to display field sync detector to enable stable display of 60 Hz status messages when logic 1.
R2 PAGE REQUEST ADDRESS - auto-increments to Register 3 SC0 to SC2 0 ACQ CCT A0, A1 BANK SELECT A2 HAM CHECK 27, 8/30 Start column for page request data (see Table 11). Must be logic 0 for normal operation. Selects one of four acquisition circuits. Selects bank of four pages being addressed for acquisition. 8/4 Hamming check packet 27 and 8/30 data.
R3 PAGE REQUEST DATA - does not auto-increment PRD0 to PRD4 See Table 11.
1996 Nov 04
22
Philips Semiconductors
Preliminary specification
Integrated Video input processor and Teletext decoder (IVT1.8*)
REGISTER BIT D0 TO D7 R4 DISPLAY CHAPTER - auto-increments to Register 5 A0 to A2 FREEZE HEADER ONLY Selects one of 8 display chapters. FUNCTION
SAA5281
Freezes the rolling header, but (unlike R0D4) allows the time to roll.
R5 NORMAL DISPLAY CONTROL - auto-increments to Register 6 R6 NEWSFLASH/SUBTITLE DISPLAY CONTROL - auto-increments to Register 7; note 1 PON TEXT COR BKGND Picture on. Text on. Contrast reduction on. Background colour on.
R7 DISPLAY MODE - does not auto-increment BOX ON 0 BOX ON 1 to 23 BOX ON 24 SINGLE/DOUBLE HEIGHT TOP/BTM HALF CONCEAL/REVEAL ON CURSOR ON STATUS BTM/TOP Boxing function allowed on Row 0. Boxing function allowed on Rows1 to 23. Boxing function allowed on Row 24. To display double height text. To select bottom half of page when DOUBLE HEIGHT is logic 1. To reveal concealed text. To display cursor. Row 25 displayed above or below the main text. Active chapter for data written to or read from memory via the I2C-bus. When set to logic 1, clears the display memory. This bit is automatically reset. VPS acquisition enabled when logic 1. Active row for data written to or read from memory via the I2C-bus. Active column for data written to or read from memory via the I2C-bus. Data read from/written to memory via I2C-bus, at location pointed to by R9 and R10. This location automatically increments each time R11 is accessed.
R8 ACTIVE CHAPTER - auto-increments to Register 9 A0 to A2 CLEAR MEM VPS ENABLE
R9 CURSOR ROW - auto-increments to Register 10 R0 to R4
R10 CURSOR COLUMN - auto-increments to Register 11 or 11B C0 to C5
R11 CURSOR DATA - does not auto-increment D0 to D7
R11B DEVICE STATUS - does not auto-increment VCS SIGNAL QUALITY TEXT SIGNAL QUALITY ROM VER R0 to R4 625/525 SYNC Indicates that the video signal quality is good and PLL is phase-locked to input video when logic 1. If a good teletext signal is being received then logic 1. Indicated language/ROM variant. For Western European is logic 0. R3 and R4 are set HIGH if R13 D6 is logic 1. If the input video is a 525 line signal then logic 1.
R12 ADVANCED CONTROL 2A - does not auto-increment S0 to S3, H0 to H3 Each acquisition channel can be programmed to process its page in one of four ways as shown in Table 12. 23
1996 Nov 04
Philips Semiconductors
Preliminary specification
Integrated Video input processor and Teletext decoder (IVT1.8*)
REGISTER BIT D0 TO D7 R13 ADVANCED CONTROL 2B - does not auto-increment AUTO DISPLAY PKT X/24 DISABLE PKT X/26 HAM CHECK 24 : 18 POINTS ENABLE VPS ENABLE MESHING ENABLE CURSOR FREEZE/ DEVICE IDENT FUNCTION
SAA5281
Status row will show the contents of the row of the extension memory (packet 24) when logic 1. Output taken from processing engine written to the display memory when logic 0. Operates independent of the acquisition. When logic 1 all packet 26 data is stored in extension memory unchecked. Enable for acquisition pointers when logic 1. VPS acquisition enabled when logic 1. Enables meshing display function in box mode. When logic 1, cursor position not updated even if active row and column change. This bit will also cause R3 and R4 of the ROM code in Register R11B to be set HIGH. This allows software to identify the device as an IVT1.8*. An internal `1.8 mode' flag is also set, which enables the operation of R0D4, R4D4 and the subtitle bit in R3. When logic 1, extension packet data is mapped into the last chapter. Only packet 24, 27/0 and 8/30 are stored. Chapters 0 to 6 can then be used for page storage. If extension packets are not enabled, 8 pages are stored as normal, but X/26 engine is enabled.
ENHANC MODE
Note 1. These functions have IN and OUT referring to inside and outside the boxing function respectively. Table 9 ODD/EVEN selection DISABLE ODD/EVEN 0 1 1 1 ODD/EVEN output continuous ODD/EVEN statically LOW ODD/EVEN active only when no TV picture displayed DV output to indicate reception of error-free 8/30/format 2 packet or VPS line RESULT
AUTO ODD/EVEN 0 0 1 1
Table 10 Interlace/non-interlace 312/313 line control and ODD/EVEN field detection option TCS ON FFB MODE(1) X X X 0 1 Notes 1. X = don't care. 2. Reverts to interlaced mode if a newsflash or subtitle is being displayed. T1 0 0 1 1 1 T0 0 1 0 1 1 interlaced 312.5/312.5 lines non-interlaced 312/313 lines (note 2) non-interlaced 312/313 lines (note 2) SCS (scan composite sync) mode: FFB leading edge in first broad pulse of field SCS (scan composite sync) mode: FFB leading edge in second broad pulse of field RESULT
1996 Nov 04
24
Philips Semiconductors
Preliminary specification
Integrated Video input processor and Teletext decoder (IVT1.8*)
Table 11 Register map for page requests (R3); notes 1 to 6 START COLUMN 0 1 2 3 4 5 6 7 Notes PRD4 DO CARE Magazine DO CARE Page tens DO CARE Page units DO CARE Hours tens DO CARE Hours units DO CARE Minutes tens DO CARE Minutes units X MU3 X MU2 CH2 MU1 CH1 X MT2 MT1 HU3 HU2 HU1 SUBTITLE X HT1 PU3 PU2 PU1 PT3 PT2 PT1 HOLD MAG2 MAG1 PRD3 PRD2 PRD1
SAA5281
PRD0
MAG0 PT0 PU0 HT0 HU0 MT0 MU0 CH0
1. Abbreviations are as given in Table 6 except for DO CARE bits and CH = chapter address for acquisition chapter. 2. When the DO CARE bit is set to logic 1 this means the corresponding digit is to be taken into account for page requests. If the DO CARE bit is set to logic 0 the digit is ignored. This allows, for example, normal or timed page selection. 3. If HOLD is set LOW, the page is held and not updated. 4. Columns auto-increment on successive I2C-bus transmission bytes. 5. The SUBTITLE bit is only present when the device is in `1.8 mode' (i.e. R13D6 has been set HIGH). 6. X = don't care. Table 12 Acquisition channel programming H0 to H3(1) 0 0 1 1 Note 1. These register bits operate in conjunction with 7 + P/ 8-BIT (Register 1, Bit D6) which will over-ride the choice of data checker if set, setting all channels to 8-bit only. If this bit is not set H0 to H3 and S0 to S3 will determine the data checking (default to 7-bit + parity). S0 to S3(1) 0 1 0 1 CHECKING ALGORITHM FOR ACQUISITION CHANNEL X 7-bit + parity for whole page 8-bit for whole page 8/4 Hamming check for whole page mixed 8/4 Hamming (columns 0 to 7, 20 to 27) and 7-bit + parity (columns 8 to 19, 28 to 39)
1996 Nov 04
25
Philips Semiconductors
Preliminary specification
Integrated Video input processor and Teletext decoder (IVT1.8*)
CLOCK SYSTEMS Crystal oscillator The crystal is a conventional Colpitts 3-pin design operating at 27 MHz. The oscillator is sinusoidal and linear, with a controlled output amplitude. This reduces the radiated and conducted level of the 27 MHz fundamental
SAA5281
frequency, and reduces the power dissipation in the quartz crystal. It is capable of oscillating with both fundamental and third overtone mode crystals. External components should be used to suppress the fundamental output of the third overtone as illustrated in Fig.13. The crystal characteristics are given in Table 13.
handbook, full pagewidth
VDD1
1 (52)
SAA5281
OSCOUT 15 pF 8.2 pF 100 nF 1 nF 3.3 µH 27 MHz 3rd overtone OSCIN
2 (1) CRYSTAL OSCILLATOR 3 (2)
3.3 k
OSCGND
4 (3)
MBD786
Fig.13 Crystal oscillator application diagram for SOT240-1; pins in parenthesis are for SOT247-1.
Table 13 Crystal characteristics (see Fig.13) SYMBOL Crystal (27 MHz, 3rd overtone) C1 C0 CL Rr R1 Xa Xj Xd series capacitance parallel capacitance load capacitance resonance resistance series resistance ageing adjustment tolerance drift 1.7 5.2 20 - 20 - - - - - - 50 - ±5 × 10-6 ±25 × 10-6 ±25 × 10-6 pF pF pF year-1 PARAMETER TYP. MAX. UNIT
1996 Nov 04
26
Philips Semiconductors
Preliminary specification
Integrated Video input processor and Teletext decoder (IVT1.8*)
CHARACTER SETS The WST specification allows the selection of national character sets via the page header transmission bits, C12 to C14. The basic 96 character sets differ only in 13 national option characters as indicated in the Tables 21, 22 and 23 with reference to their table position in the basic character matrix illustrated in Table 20. The IVT1.8* automatically decodes transmission bits C12 to C14. Tables 14, 15 and 16 illustrate the character matrixes. Character bytes are listed as transmitted from b1 to b7. Meshing
SAA5281
This is an alternative method of displaying teletext subtitles, or similar boxed text superimposed on the TV picture and operates by showing reduced contrast TV pictures in place of the (black) background within the boxed area. The Meshing effect is produced by toggling the BLAN signal from IVT at pixel rate. By starting at the same point each field, and toggling the start position each line, a chequered pattern will result. This allows movement to be seen behind the text information. The MESH OFF/ON bit in Register 13 D5 controls this function. Normally at zero, compatibility with IVT1.0 is maintained.
MLA663 handbook, full pagewidth
alphanumerics and graphics 'space' character 0000010
alphanumerics character 1011010
alphanumerics or blast-through alphanumerics character 0001001
alphanumerics character 1111111
contiguous graphics character 0110111
separated graphics character 0110111 =
separated graphics character 1111111 background colour
contiguous graphics character 1111111 display = colour
Fig.14 Character format.
1996 Nov 04
27
Philips Semiconductors
Preliminary specification
Integrated Video input processor and Teletext decoder (IVT1.8*)
Table 14 SAA5281P/E character data input decoding, West European languages; notes 1 to 9 For character version number (11000) see Register 11B.
b8 B handbook, full pagewidth I T S b7 b6 b5 b 4 b 3 b2 b 1 r o w 0 0 0 0 0 column 0 0 0 0 0 1 graphics black graphics red graphics green 0 0 0 1 2 0 or 1 0 1 0 2a 0 0 1 1 3 0 or 1 0 1 1 3a 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 6a 7 0 1 1 1 7a 8 1 0 0 0 9 1 0 0 1 12 1 1 0 0 13 1 1
SAA5281
1 1 0 1 14 1 0
1 1 1 1 15
alpha numerics black alpha numerics red alpha numerics green alpha numerics yellow alpha numerics blue alpha numerics magenta alpha numerics cyan alpha numerics white flash
(2) (2)
0
0
0
1
1
0
0
1
0
2
0
0
1
1
3
graphics yellow
0
1
0
0
4
graphics blue graphics magenta
0
1
0
1
5
0
1
1
0
6
graphics cyan graphics white conceal display
(2)
0
1
1
1
7
1
0
0
0
8
1
0
0
1
9
steady
(2)
contiguous graphics separated graphics
(1)
1
0
1
0
10
end box
1
0
1
1
11
start box
(2)
ESC
(2)
1
1
0
0
12
normal height double height
(1)
black back ground
1
1
0
1
13
new back ground hold graphics
(1) (2)
1
1
1
0
14
SO
1
1
1
1
15
SI
release graphics
MBA429
1996 Nov 04
28
Philips Semiconductors
Preliminary specification
Integrated Video input processor and Teletext decoder (IVT1.8*)
Table 15 SAA5281P/H character data input decoding, East European languages; notes 1 to 9 For character version number (11001) see Register 11B.
handbook, full pagewidth B b8
I T S b7 b6 b5 b 4 b 3 b 2 b 1 r o w 0 0 0 0 0 column 0
SAA5281
0 0 0 0
0 0 0 1 1 graphics black graphics red graphics green
0 or 1 0 1 0 2
0 0 1 0 2a
0 or 1 0 1 1 3
0 0 1 1 3a
0 1 0 0 4
0 1 0 1 5
0 1 1 0 6 6a
0 1 1 1 7 7a
1 0 0 0 8
1 0 0 1 9
1 1 0 0 12
1 1 0 1 13
1 1 1 0 14
1 1 1 1 15
alpha numerics black alpha numerics red alpha numerics green alpha numerics yellow alpha numerics blue alpha numerics magenta alpha numerics cyan alpha numerics white flash
(2) (2)
0
0
0
1
1
0
0
1
0
2
0
0
1
1
3
graphics yellow
0
1
0
0
4
graphics blue graphics magenta
0
1
0
1
5
0
1
1
0
6
graphics cyan graphics white conceal display
(2)
0
1
1
1
7
1
0
0
0
8
1
0
0
1
9
steady
(2)
contiguous graphics separated graphics
(1)
1
0
1
0
10
end box
1
0
1
1
11
start box
(2)
ESC
(2)
1
1
0
0
12
normal height double height
(1)
black back ground
1
1
0
1
13
new back ground hold graphics
(1) (2)
1
1
1
0
14
SO
1
1
1
1
15
SI
release graphics
MLA961
1996 Nov 04
29
Philips Semiconductors
Preliminary specification
Integrated Video input processor and Teletext decoder (IVT1.8*)
SAA5281
Table 16 SAA5281P/T character data input decoding, West European and Turkish languages; notes 1 to 9 For character version number (11010) see Register 11B.
handbook, full pagewidth b8 B
I T S b7 b6 b5 b 4 b 3 b2 b 1 r o w 0 0 0 0 0 column 0 0 0 0 0 1 graphics black graphics red graphics green 0 0 0 1 2 0 or 1 0 1 0 2a 0 0 1 1 3 0 or 1 0 1 1 3a 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 6a 7 0 1 1 1 7a 8 1 0 0 0 9 1 0 0 1 12 1 1 0 0 13 1 1 0 1 14 1 1 1 0 15 1 1 1 1
alpha numerics black alpha numerics red alpha numerics green alpha numerics yellow alpha numerics blue alpha numerics magenta alpha numerics cyan alpha numerics white flash
(2) (2)
0
0
0
1
1
0
0
1
0
2
0
0
1
1
3
graphics yellow
0
1
0
0
4
graphics blue graphics magenta
0
1
0
1
5
0
1
1
0
6
graphics cyan graphics white conceal display
(2)
0
1
1
1
7
1
0
0
0
8
1
0
0
1
9
steady
(2)
contiguous graphics separated graphics
(1)
1
0
1
0
10
end box
1
0
1
1
11
start box
(2)
ESC
(2)
1
1
0
0
12
normal height double height
(1)
black back ground
1
1
0
1
13
new back ground hold graphics
(1) (2)
1
1
1
0
14
SO
1
1
1
1
15
SI
release graphics
MBA431
1996 Nov 04
30
Philips Semiconductors
Preliminary specification
Integrated Video input processor and Teletext decoder (IVT1.8*)
Table 17 SAA5281P/R character data input decoding, Baltic and Cyrillic languages; notes 1 to 9 For character version number (00101) see Register 11B.
B I T S b8 b7 b6 b5 b 4 b 3 b 2 b 1 r o w 0 0 0 0 0 column 0 0 0 0 0 1 graphics black graphics red graphics green graphics yellow 0 0 0 1 2 0 or 1 0 1 0 2a 0 0 1 1 3 0 or 1 0 1 1 3a 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 6a 7 0 1 1 1 7a 8 1 0 0 0 9 1 0 0 1 12 1 1 0 0 13 1 1 0
SAA5281
1 1 1 1 14 0
1 1 1 1 15
alpha numerics black alpha numerics red alpha numerics green alpha numerics yellow alpha numerics blue alpha numerics magenta alpha numerics cyan alpha numerics white flash
(2) (2)
0
0
0
1
1
0
0
1
0
2
0
0
1
1
3
0
1
0
0
4
graphics blue graphics magenta
0
1
0
1
5
handbook, full pagewidth 0 0 1 1
6
graphics cyan
0
1
1
1
7
graphics white conceal display
(2)
1
0
0
0
8
1
0
0
1
9
steady
(2)
contiguous graphics separated graphics
1
0
1
0
10
end box
1
0
1
1
11
start box
(2)
TWIST
(2)
1
1
0
0
12
normal height double height
(1)
black back ground
1
1
0
1
13
new back ground hold graphics
(1) (2)
1
1
1
0
14
SO
1
1
1
1
15
SI
release graphics
MBA648 - 1
1996 Nov 04
31
Philips Semiconductors
Preliminary specification
Integrated Video input processor and Teletext decoder (IVT1.8*)
Table 18 SAA5281P/L character data input decoding, Arabic and Hebrew languages; notes 1 to 9 For character version number (00100) see Register 11B.
B I T S b8 b7 b6 b5 b 4 b 3 b 2 b 1 r o w 0 0 0 0 0 column 0 0 0 0 0 1 graphics black graphics red graphics green 0 0 0 1 2 0 or 1 0 1 0 2a 0 0 1 0 3 0 or 1 0 1 1 3a 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 6a 0 or 1 1 1 0 7 0 1 1 1 7a 0 or 1 1 1 1 8 1 0 0 0 9 1 0 0 1 12 1 1 0 0 13 1 1 0
SAA5281
1 1 1 1 14 0
1 1 1 1 15
alpha numerics black alpha numerics red alpha numerics green alpha numerics yellow alpha numerics blue alpha numerics magenta alpha numerics cyan alpha numerics white flash
(2) (2)
0
0
0
1
1
0
0
1
0
2
0
0
1
1
3
graphics yellow
0
1
0
0
4
graphics blue graphics magenta
0
1
0
1
5
handbook, full 0 1 1 0 pagewidth
6
graphics cyan graphics white conceal display
(2)
0
1
1
1
7
1
0
0
0
8
1
0
0
1
9
steady
(2)
contiguous graphics separated graphics
1
0
1
0
10
end box
1
0
1
1
11
start box
(2)
TWIST
(2)
1
1
0
0
12
normal height double height
(1)
black back ground
1
1
0
1
13
new back ground hold graphics
(1) (2)
1
1
1
0
14
SO
1
1
1
1
15
SI
release graphics
MLA963 - 1
1996 Nov 04
32
Philips Semiconductors
Preliminary specification
Integrated Video input processor and Teletext decoder (IVT1.8*)
Table 19 SAA5281P/K character data input decoding, French and Arabic languages; notes 1 to 9 For character version number (00100) see Register 11B.
B I T S b8 b7 b6 b5 b 4 b 3 b 2 b 1 r o w 0 0 0 0 0 column 0 0 0 0 0 1 graphics black graphics red graphics green 0 0 0 1 2 0 or 1 0 1 0 2a 0 0 1 0 3 0 or 1 0 1 1 3a 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 6a 0 or 1 1 1 0 7 0 1 1 1 7a 0 or 1 1 1 1 8 1 0 0 0 9 1 0 0 1 12 1 1 0 0 13 1 1 0 1
SAA5281
1 1 1 0 14
1 1 1 1 15
alpha numerics black alpha numerics red alpha numerics green alpha numerics yellow alpha numerics blue alpha numerics magenta alpha numerics cyan alpha numerics white flash
(2) (2)
0
0
0
1
1
0
0
1
0
2
0
0
1
1
3
graphics yellow
0
1
0
0
4
graphics blue graphics magenta
0
1
0
1
5
0 1 1 handbook, full pagewidth0
6
graphics cyan graphics white conceal display
(2)
0
1
1
1
7
1
0
0
0
8
1
0
0
1
9
steady
(2)
contiguous graphics separated graphics
1
0
1
0
10
end box
1
0
1
1
11
start box
(2)
TWIST
(2)
1
1
0
0
12
normal height double height
(1)
black back ground
1
1
0
1
13
new back ground hold graphics
(1) (2)
1
1
1
0
14
SO
1
1
1
1
15
SI
release graphics
MLA972 - 1
1996 Nov 04
33
Philips Semiconductors
Preliminary specification
Integrated Video input processor and Teletext decoder (IVT1.8*)
Notes to Tables 14, 15, 16, 17, 18 and 19 1. These control characters are reserved for compatibility with other data codes. 2. These control characters are presumed before each row begins. 3. Control characters shown in Columns 0 and 1 are normally displayed as spaces. 4. Characters may be referred to by column and row (for example 2/5 refers to %). 5. Black represents displayed colour. White represents background. 6. The SAA5281 national option characters are illustrated in Tables 21, 22 and 23.
SAA5281
7. Characters 8/6, 8/7, 9/5, 9/6 and 9/7 are special characters for combining with character 8/5 (E, H and T codes only). Characters 5/12, 5/13, 5/14 and 5/15 are combined with 5/11 (S code only). 8. National option characters will be displayed according to the setting of control bits C12 to C14. These will be mapped into the basic code table into positions shown in Tables 21, 22 and 23. 9. Columns 2a, 3a, 6a and 7a are displayed in graphics mode.
1996 Nov 04
34
SAA5281
Note
Preliminary specification
1. Where NC = national option character position.
full pagewidth
1996 Nov 04
3/8 6/0 NC NC 4/0 4/8 5/0 5/8 6/8 7/0 7/8 3/9 4/1 4/9 5/1 5/9 6/1 6/9 7/1 7/9 3/10 4/2 4/10 5/2 5/10 6/2 6/10 7/2 7/10 3/11 5/11 NC 4/3 4/11 5/3 6/3 6/11 7/3 7/11 NC
Table 20 SAA5281 basic character matrix; note 1
Philips Semiconductors
2/0
2/8
3/0
2/1
2/9
3/1
2/2
2/10
3/2
2/3
2/11
3/3
Integrated Video input processor and Teletext decoder (IVT1.8*)
NC
2/4 3/12 NC 4/4 4/12 5/4 6/4 6/12
2/12
3/4
5/12
7/4
7/12 NC
35
3/13 NC 4/5 4/13 5/5 5/13 6/5 6/13 3/14 4/6 4/14 5/6 5/14 NC 6/6 3/15 4/7 4/15 5/7 5/15 NC 6/7 6/15
NC
2/5
2/13
3/5
7/5
7/13 NC
2/6
2/14
3/6
7/6
7/14 NC
2/7
2/15
3/7
7/7
7/15
MLA630
Philips Semiconductors
Preliminary specification
Integrated Video input processor and Teletext decoder (IVT1.8*)
Table 21 SAA5281P/E national option character set
handbook, full pagewidth
(1)
SAA5281
PHCB
CHARACTER POSITION (COLUMN / ROW) 2/4 4/0 5 / 11 5 / 12 5 / 13 5 / 14 5 / 15 6/0 7 / 11 7 / 12 7 / 13 7 / 14
LANGUAGE C12 C13 C14 2 / 3 ENGLISH 0 0 0
GERMAN
0
0
1
SWEDISH
0
1
0
ITALIAN
0
1
1
FRENCH
1
0
0
SPANISH
1
0
1
MLB458
(1) PHCB are the Page Header Control Bits. Other combinations default to English.
Table 22 SAA5281P/H national option character set
handbook, full pagewidth
(1)
PHCB
CHARACTER POSITION (COLUMN / ROW) 2/4 4/0 5 / 11 5 / 12 5 / 13 5 / 14 5 / 15 6/0 7 / 11 7 / 12 7 / 13 7 / 14
LANGUAGE C12 C13 C14 2 / 3 POLISH 0 0 0
GERMAN
0
0
1
SWEDISH
0
1
0
SERBO-CROAT
1
0
1
CZECHOSLOVAKIA
1
1
0
RUMANIAN
1
1
1
MLA966
(1) PHCB are the Page Header Control Bits. Other combinations default to German. Only the above characters change with the PHCB. All other characters in the basic set are shown in Table 20.
1996 Nov 04
36
Philips Semiconductors
Preliminary specification
Integrated Video input processor and Teletext decoder (IVT1.8*)
Table 23 SAA5281P/T national option character set
SAA5281
andbook, full pagewidth
PHCB
(1)
CHARACTER POSITION (COLUMN / ROW) 2/4 4/0 5 / 11 5 / 12 5 / 13 5 / 14 5 / 15 6/0 7 / 11 7 / 12 7 / 13 7 / 14
LANGUAGE C12 C13 C14 2 / 3 ENGLISH 0 0 0
GERMAN
0
0
1
TURKISH
1
1
0
ITALIAN
0
1
1
FRENCH
1
0
0
SPANISH
1
0
1
MBA430
(1) PHCB are the Page Header Control Bits. Other combinations default to English. Only the above characters change with the PHCB. All other characters in the basic set are shown in Table 20.
1996 Nov 04
37
Philips Semiconductors
Preliminary specification
Integrated Video input processor and Teletext decoder (IVT1.8*)
Table 24 SAA5281P/R national option character set
SAA5281
handbook, full pagewidth
PHCB
(1)
CHARACTER POSITION (COLUMN / ROW) 2/4 4/0 5 / 11 5 / 12 5 / 13 5 / 14 5 / 15 6 / 0 7 / 11 7 / 12 7 / 13 7 / 14
LANGUAGE C12 C13 C14 2 / 3 ESTONIAN LETTISH / LITHUANIAN RUSSIAN 0 1 0
0
1
1
1
0
0
2
3
4
5
6
7
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
MEA597
(1) PHCB are the Page Header Control Bits. Other combinations default to Estonian.
1996 Nov 04
38
Philips Semiconductors
Preliminary specification
Integrated Video input processor and Teletext decoder (IVT1.8*)
Table 25 SAA5281P/K national option character set
SAA5281
2 0
3
4
5
6
7 0
2
3
4
5
6
7
1
1
2
2
3
3
4
4
5
5
6
6
7
handbook, full pagewidth
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
LANGUAGE
FRENCH
ARABIC
PHCB
(1) 1 0 0 1 1 1
(C12, C13, C14)
MLA968 - 1
(1) PHCB are the Page Header Control Bits. Other combinations default to French.
1996 Nov 04
39
Philips Semiconductors
Preliminary specification
Integrated Video input processor and Teletext decoder (IVT1.8*)
Table 26 SAA5281P/L national option character set
SAA5281
2 0
3
4
5
6
7 0
2
3
4
5
6
7
1
1
2
2
3
3
4
4
5
5
6
6
7
7
handbook, full pagewidth
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
LANGUAGE
HEBREW/ENGLISH
ARABIC
PHCB
(1) 1 0 1 1 1 1
(C12, C13, C14)
MLA967
(1) PHCB are the Page Header Control Bits. Other combinations default to Hebrew English.
1996 Nov 04
40
handbook, full pagewidth
100 nF 1 OSCOUT 220 51 P1.1 P0.0 38 P0.1 37 P0.2 36 P0.3 P0.4 P0.5 33 SDA 1 µF 5V RST 10 P3.0 EA 30 ALE PSEN P2.7 P2.6 P2.5 P3.6 17 35 34 33 32 31 30 29 28 27 address select 5V 1 2 3 4 PCF8572 PCF8582 8 7 6 5 3.3 nF 56 k 5V 470 18 XTAL2 19 XTAL1 20 V SS P2.1 P2.0 P2.2 P3.7 P2.3 P2.4 27 26 P3.5 37 36 16 25 24 23 22 21 29 28 P3.3 14 P3.4 15 P3.1 P3.2 5V PON i.c. i.c. i.c. i.c. n.c. n.c. i.c. i.c. i.c. i.c. i.c. i.c. 38 PL out 13 11 12 40 39 CLK EN 31 5V P0.7 9 32 P0.6 34 35 3 3 OSCGND 4.7 k 4 P1.3 5 5V V SS1 i.c. i.c. LINE 23 P1.5 7 SCL 45 8 44 i.c. i.c. i.c. i.c. i.c. 41 PDI 42 43 46 47 LINE 23 6 48 V SS1 REF+ n.c. BLACK CVBS IREF V DD2 POL STTV/LFB VCR/FFB CLK O/P i.c. 49 i.c. link options 4 5 50 P1.2 2 39 220 P1.0 2 OSCIN i.c. 15 pF V DD1 VDD 5V 52 1 40 SDA SCL
10 µF
5V
1996 Nov 04
4.7 k
P1.4 100 nF 6 7 100 nF 8 9 27 k 10 11
22 nF
3.3 µH
8.2 pF
Philips Semiconductors
APPLICATION INFORMATION
3.3 k
27 MHz 3rd overtone
100 nF
CVBS
83C654
5V 12 13 14
100 nF
33 µF
Integrated Video input processor and Teletext decoder (IVT1.8*)
SYNC
1.5 k
41
15 V SS2 R G B RGBREF 20 BLAN COR ODD/EVEN Y SCL SDA 26 V SS3 21 22 23 24 25 16 17 18 19
330 nF
SAA5281
1 k
R
G
B
BLAN
COR
ODD/EVEN
MBD790
Preliminary specification
SAA5281
Fig.15 Application diagram for SDIP52, SOT247-1.
Philips Semiconductors
Preliminary specification
Integrated Video input processor and Teletext decoder (IVT1.8*)
PACKAGE OUTLINES DIP48: plastic dual in-line package; 48 leads (600 mil)
SAA5281
SOT240-1
seating plane
D
ME
A2
A
L
A1 c Z e b1 b 48 25 MH w M (e 1)
pin 1 index E
1
24
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.9 0.19 A1 min. 0.36 0.014 A2 max. 4.06 0.16 b 1.4 1.14 0.055 0.045 b1 0.53 0.38 0.021 0.015 c 0.36 0.23 0.014 0.009 D (1) 62.60 61.60 2.46 2.42 E (1) 14.22 13.56 0.56 0.53 e 2.54 0.10 e1 15.24 0.60 L 3.90 3.05 0.15 0.12 ME 15.88 15.24 0.63 0.60 MH 18.46 15.24 0.73 0.60 w 0.254 0.01 Z (1) max. 2.1 0.083
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT240-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-01-25
1996 Nov 04
42
Philips Semiconductors
Preliminary specification
Integrated Video input processor and Teletext decoder (IVT1.8*)
SAA5281
SDIP52: plastic shrink dual in-line package; 52 leads (600 mil)
SOT247-1
seating plane
D
ME
A2
A
L
A1 c Z e b1 w M (e 1) MH b 52 27
pin 1 index E
1
26
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 5.08 A1 min. 0.51 A2 max. 4.0 b 1.3 0.8 b1 0.53 0.40 c 0.32 0.23 D (1) 47.9 47.1 E (1) 14.0 13.7 e 1.778 e1 15.24 L 3.2 2.8 ME 15.80 15.24 MH 17.15 15.90 w 0.18 Z (1) max. 1.73
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT247-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 90-01-22 95-03-11
1996 Nov 04
43
Philips Semiconductors
Preliminary specification
Integrated Video input processor and Teletext decoder (IVT1.8*)
SAA5281
QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
SOT319-2
c
y X
51 52
33 32 ZE
A
e E HE A A2 A1
Q (A 3) Lp L detail X
pin 1 index
wM bp
64 1 w M D HD ZD 19
20
e
bp
v M A B v M B
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 3.20 A1 0.25 0.05 A2 2.90 2.65 A3 0.25 bp 0.50 0.35 c 0.25 0.14 D (1) 20.1 19.9 E (1) 14.1 13.9 e 1 HD 24.2 23.6 HE 18.2 17.6 L 1.95 Lp 1.0 0.6 Q 1.4 1.2 v 0.2 w 0.2 y 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 7 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT319-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-02-04
1996 Nov 04
44
Philips Semiconductors
Preliminary specification
Integrated Video input processor and Teletext decoder (IVT1.8*)
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Soldering by dipping or by wave The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA5281
with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Repairing soldered joints Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 °C, contact may be up to 5 seconds.
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1996 Nov 04
45
Philips Semiconductors
Preliminary specification
Integrated Video input processor and Teletext decoder (IVT1.8*)
NOTES
SAA5281
1996 Nov 04
46
Philips Semiconductors
Preliminary specification
Integrated Video input processor and Teletext decoder (IVT1.8*)
NOTES
SAA5281
1996 Nov 04
47
Philips Semiconductors a worldwide company
Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 1949 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580/xxx France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstraße 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd. Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722 Indonesia: see Singapore Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 247 9145, Fax. +7 095 247 9144 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Rua do Rocio 220, 5th floor, Suite 51, 04552-903 São Paulo, SÃO PAULO - SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 829 1849 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 3 301 6312, Fax. +34 3 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 632 2000, Fax. +46 8 632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH, Tel. +41 1 488 2686, Fax. +41 1 481 7730 Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West Road, Sec. 1, P.O. Box 22978, TAIPEI 100, Tel. +886 2 382 4443, Fax. +886 2 382 4444 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 © Philips Electronics N.V. 1996
Internet: http://www.semiconductors.philips.com
SCA52
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
537021/1200/02/pp48
Date of release: 1996 Nov 04
Document order number:
9397 750 01461