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A B C D E
1 1
Compal Schematic
2 2
HCL51 Schematics Document
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Intel Yonah Processor with ATIRC410MD/E + DDRII + SB460M
3
2006-04-05 3
REV: 1
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HCL51 LA-3211P
Date: , 11, 2006 Sheet 1 of 43
A B C D E
A B C D E
Compal Schematic
Thermal Sensor Clock Generator
Model Name : HCL51 Fan Control
page 35
Yonah
F75383M ICS951413
page 4 page 12
File Name : LA-3211P uPGA-478 Package
page 4,5
1 1
PSB
H_A#(3..31) 533/667MHz H_D#(0..63)
LCD Conn. CRT & TV-out
page 18 page 19
LVDS Memory BUS(DDRII) 200pin DDRII-SO-DIMM X2
ATI RC410MB/D/E Single Channel BANK 0, 1, 2, 3 page 10,11
1.8V DDRII 400/533/667
uFCBGA-1466
Mini card PCI-Express page 7,8,9
page 25
Alink USB conn x4 Bluetooth
page 26 Conn page 31
USB port 0, 2 on M/B USB port1
USB port 4, 6 on PWRBTN/B
2
3.3V 33 MHz PCI BUS ATI SB460M 3.3V 48MHz 2
IDSEL:AD18 IDSEL:AD22 IDSEL:AD20 3.3V 24.576MHz/48Mhz HD Audio
(PIRQF/H#, (PIRQG#, (PIRQE#/B#,
GNT#3, GNT#1, GNT#2, 3.3V ATA-100
REQ#3) REQ#1) REQ#2)
IDE
S-ATA
page 13~~17
Mini PCI LAN (100/1000)
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CardBus PIDE-HDD SIDE-ODD
socket RTL8100/8110 ENE CB714 Conn. MDC 1.5 HDA Codec
(WLAN) page 23 page 21 Conn ALC883
page 20 page 20 page 31 page 33
(TV-Tuner)
page 25
6 in 1 S-ATA HDD
RJ45 Slot 0 socket Conn.
page 24 page 15
page 22 page 22
Audio AMP
LPC BUS page 34
3 3
RTC CKT. Super I/O Phone Jack x3
page 13
ENE KB910Q page 34
SMsC LPC47N207
page 29 page 28
Power On/Off CKT. Switch/B Conn.
USB port4, 6
page 32
page 31
Touch Pad Int.KBD
page 32 page 30 FIR
TFDU6102-TR3
page 28
DC/DC Interface CKT. CD-PLAY/B Conn. EC I/O Buffer BIOS
page 31
page 36 page 30 page 30
Power Circuit DC/DC MEDIA/B Conn.
page 31
page 37~~43
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HCL51 LA-3211P
Date: , 11, 2006 Sheet 2 of 43
A B C D E
A B C D E
SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Voltage Rails
Full ON HIGH HIGH HIGH HIGH ON ON ON ON
Power Plane Description S1 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
VIN Adapter power supply (19V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
B+ AC or battery power rail for power circuit. N/A N/A N/A
1
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1
+CPU_CORE Core voltage for CPU ON OFF OFF
+0.9VS 0.9V switched power rail for DDR terminator ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.05VS 1.05V switched power rail ON OFF OFF
+1.5VS 1.5V switched power rail ON OFF OFF
+1.8V 1.8V power rail for DDR ON ON OFF Board ID / SKU ID Table for AD channel
+1.8VS 1.8V switched power rail ON OFF OFF Vcc 3.3V +/- 5%
+2.5VS 2.5V switched power rail ON OFF OFF Ra/Rc/Re 100K +/- 5%
+3VALW 3.3V always on power rail ON ON ON* Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+3VS 3.3V switched power rail ON OFF OFF 0 0 0 V 0 V 0 V
+5VALW 5V always on power rail ON ON ON* 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+5VS 5V switched power rail ON OFF OFF 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+VSB VSB always on power rail ON ON ON* 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+RTCVCC RTC power ON ON ON 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
5 100K +/- 5% 1.453 V 1.650 V 1.759 V
6 200K +/- 5% 1.935 V 2.200 V 2.341 V
7 NC 2.500 V 3.300 V 3.300 V
2 2
BOARD ID Table BTO Option Table
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
BTO Item BOM Structure
External PCI Devices Board ID PCB Revision
LAN(10/100) 8100C@
Device IDSEL# REQ#/GNT# Interrupts
0
LAN(GIGA) 8110S@
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CardBus(SD) AD20 2 PIRQE/PIRQH
1 0.2
FIR FIR@
1394 AD16 0 PIRQA
2 0.2
MINI CARD1 MINI1@
LAN(10/100) AD22 1 PIRQG
3
SATA HDD SATA@
Mini-PCI(WLAN/TV-Tuner) AD18 3 PIRQF/PORQH
4
CardReader 4IN1@
5
6
7
EC SM Bus1 address EC SM Bus2 address SKU ID Table
3
Device Address Device Address
SKU ID SKU 3
Smart Battery 0001 011X b Fintek F75383M 1001 100X b
0
EEPROM(24C16/02) 1010 000X b
1
GMT G781-1 1001 101X b
2
3
4
5
6
SB460M SM Bus address 7
Device Address
Clock Generator 1101 001Xb
(ICS951413)
DDR DIMM0 1001 000Xb
DDR DIMM2 1001 010Xb
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2005/06/20 Deciphered Date 2006/06/20 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HCL51 LA-3211P
Date: , 11, 2006 Sheet 3 of 43
A B C D E
5 4 3 2 1
+3VS
(7) H_A#[3..31] H_D#[0..63] (7)
JCPU1A C1
0.1U_0402_16V4Z
H_A#3 J4 E22 H_D#0 1 2
H_A#4
H_A#5
L4
A3#
A4#
YONAH D0#
D1# F24 H_D#1
H_D#2
M3 A5# D2# E26
H_A#6 K5 H22 H_D#3 1 U1
H_A#7 A6# D3# H_D#4 C2
M1 A7# D4# F23 1 VDD SCLK 8 EC_SMB_CK2 (28)
H_A#8 N2 G25 H_D#5
H_A#9 A8# D5# H_D#6 2200P_0402_50V7K THERMDA
D J1 A9# D6# E25 2 D+ SDATA 7 EC_SMB_DA2 (28) D
H_A#10 H_D#7 2
N3 A10# D7# E23
H_A#11 P5 K24 H_D#8 THERMDC 3 6
H_A#12 A11# D8# H_D#9 D- ALERT#
P2 A12# D9# G24
H_A#13 L1 J24 H_D#10 4 5
H_A#14 A13# D10# H_D#11 +1.05VS +CPU_CORE THERM# GND
P4 A14# D11# J23
H_A#15 P1 H26 H_D#12
H_A#16 A15# D12# H_D#13 ADM1032ARMZ-2REEL_MSOP8
R1 A16# D13# F26
1
1
H_A#17 Y2 K22 H_D#14 R1
H_A#18 A17# D14# H_D#15 R2 F75383M_MSOP8
U5 A18# D15# H25
H_A#19 R3 N22 H_D#16 @ 47K_0402_5% 47K_0402_5%
H_A#20 A19# D16# H_D#17
W6 A20# D17# K25
H_A#21 U4 P26 H_D#18
A21# D18# MAINPWON (14,36,37,39)
H_A#22 H_D#19
2
2
Y5 A22# D19# R23
1
H_A#23 U2 L25 H_D#20 C3 C
H_A#24 A23# D20# H_D#21 Q1
R4 A24# D21# L22 1 2 2
H_A#25 T5 ADDR GROUP DATA GROUP L23 H_D#22 B
H_A#26 A25# D22# H_D#23 @ 0.1U_0603_25V7K E 2SC2411K_SC59
T3 A26# D23# M23
H_A#27 H_D#24
3
W3 A27# D24# P25
H_A#28 W5 P22 H_D#25
H_A#29 A28# D25# H_D#26 56_0402_5%
Y4 A29# D26# P23
H_A#30 W2 T24 H_D#27 +1.05VS 1 2
H_A#31 A30# D27# H_D#28 R4
(7) H_REQ#[0..4] Y1 A31# D28# R24
L26 H_D#29
H_REQ#0 D29# H_D#30 H_THERMTRIP#
K3 REQ0# D30# T25
H_REQ#1 H2 N24 H_D#31
H_REQ#2
H_REQ#3
H_REQ#4
K2
J3
REQ1#
REQ2#
REQ3#
D31#
D32#
D33#
AA23
AB24
H_D#32
H_D#33
H_D#34
A +1.05VS
+3VALW
L5 REQ4# D34# V24
1
V26 H_D#35 +1.05VS
H_ADSTB#0 D35# H_D#36
(7) H_ADSTB#0 L2 ADSTB0# D36# W25 1K_0402_5%
H_ADSTB#1 V4 U23 H_D#37
(7) H_ADSTB#1 ADSTB1# D37#
2
C
U25 H_D#38 R5 C
D38#
1
1
U22 H_D#39 R6
D39# H_D#40 R7 R8
2
D40# AB25 470_0402_5%
W22 H_D#41 56_0402_5%
D41# R9 0_0402_5% H_PROCHOT# (14,42)
Y23 H_D#42 75_0402_1%
CLK_CPU_BCLK D42# H_D#43 H_DPRSTP# 2
1
(12) CLK_CPU_BCLK A22 BCLK0 D43# AA26 1
1
CLK_CPU_BCLK# HOST CLK H_D#44 C
2
2
A21 Y26
(12) CLK_CPU_BCLK# BCLK1 D44#
B
1
Y22 H_D#45 C R10 470_0402_5% 2 Q2
D45# H_D#46 B PMBT3904_SOT23
D46# AC26 2 1 2 DPRSLPVR (13,42)
AA24 H_D#47 B E
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H_ADS# D47# H_D#48 E 2SC2411K_SC59
3
(7) H_ADS# H1 ADS# D48# AC22
H_BNR# H_D#49 PROCHOT#
3
(7) H_BNR# E2 BNR# D49# AC23 Q3
H_BPRI# G5 AB22 H_D#50
(7)
(7)
(7)
H_BPRI#
H_BR0#
H_DEFER#
H_BR0#
H_DEFER#
H_DRDY#
F1
H5
BPRI#
BR0#
DEFER#
D50#
D51#
D52#
AA21
AB21
H_D#51
H_D#52
H_D#53
C
(7) H_DRDY# F21 DRDY# D53# AC25
H_HIT# G6 AD20 H_D#54
(7) H_HIT# HIT# D54#
H_HITM# E4 CONTROL AE22 H_D#55
(7) H_HITM# HITM# D55#
H_IERR# D20 AF23 H_D#56
H_LOCK# IERR# D56# H_D#57 +1.05VS
(7) H_LOCK# H4 LOCK# D57# AD24
H_RESET# B1 AE21 H_D#58
(7,13) H_RESET# RESET# D58# H_D#59
D59# AD21
AE25 H_D#60
(7) H_RS#[0..2] D60#
H_RS#0 F3 AF25 H_D#61
H_RS#1 RS0# D61# H_D#62
F4 RS1# D62# AF22
H_RS#2 G3 AF26 H_D#63
H_TRDY# RS2# D63# H_DPRSTP# @ 2 R11 56_0402_5%
(7) H_TRDY# G2 TRDY# 1
J26 H_RESET# R12 2 1 @ 54.9_0402_1%
DINV0# H_DINV#0 (7)
DINV1# M26 H_DINV#1 (7)
AD4 V23 ITP_TMS R13 2 1 40.2_0402_1%
BPM0# DINV2# H_DINV#2 (7)
B AD3 AC20 B
BPM1# DINV3# H_DINV#3 (7)
AD1