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A B C D E
Dual Prestonia or Nocona 533MHz CPUs
FLASH
IPMI
Module
P4 Xeon
BSP
P4 Xeon
GA-8EGXDREL
V1.0
X-BUS VRM 9.1
CPU 1 CPU 2
4 COM 4
x 2
USB
x 4 CPU Host Bus
PP SIO NS (533MHz) 4GB Max
PC87417
LPC 4GB/Sec MEMORY I/F
Bus
Thin 200Mhz x 2 (266Mhz) Registered ECC DDR266 DIMM x 4
FDD IMB (800MB/Sec)
ATA-100
2.1GB/Sec
IDE 1 CSB6 CMIC-SL
ATA-100
RAID
IDE 2 533MHz
0/1/5 ATA-66
IDE 3
FRODO PCI 64b/33Mhz
PCI SATA 4/8 PORTs
PCI BUS 0 64b/33Mhz
3 3
GLAN2 GLAN1
ATi
PCISLOT_6 8MB Rage
33MHz/32b SDRAM XL Raptor - Zero PCISLOT_1-5
Intel Intel Canhhel RAID 33MHz/64b
82540PM 82545PM
PCI PCI
32b/33Mhz 64b/33Mhz
INDEX
PAGE # DESCRIPTION PAGE # DESCRIPTION PAGE # DESCRIPTION
01. BLOCK DIAGRAM & INDEX 24. GLAN2_82540EM_RJ45 47 BLANK
02. RESET_&_CLOCK_BLOCK DIAGRAM 25. PCI_X_SLOT1 48 W83791D_HW_MONITOR_&_IPMI 8 Layer 5mil / 50 Ohm
2 03. CPU_END_1 26. PCI_X_SLOT2 49 SYSTEM_FAN 2
04. CPU_END_1_PWR 27. PCI_X_SLOT_3_&_RADIOS 50 F_PANEL_&_SYSTEM_SWITCH
Inner 1 PWR
05. CPU_MID_2 28. PCI_X_SLOT4 51 SIO417_LPC_&_GPIO
06. CPU_MID_2_PWR 29. FRODO_PCI 52 SIO417_COM_LPC_FDD
Inner 2 GND
07. CPU_CAPS 30. FRODO_PORT_0-3 53 BIOS_WOL_WOM
08. VID_CONTROL_&_RESET_BUFFER 31. FRODO_PORT_4-7 54 USB_KB_MS
09. STITCHING CAP 32. FRODO_POWER 55 SSI_POWER_CONNECTORS
CORE = 30 mil
10. CPU_LEVEL_SHIFT_TERM 33. GLAN1_82545EM_PCI 56 VCC25_&_VCC1_25
11. CMIC_CPU_IF 34. GLAN1_82545EM_ PWR 57 PCB_HOLE_&_RESUME_RESET
Inner 3 GND
12. CMIC_CIOB_IF 35. GLAN1_82545EM_RJ45 58 CPU_VRM_LOGIC
13. CMIC_MEM_IF 36. CSB6_PCI_&_IDE 59 POWER_ROUTING_MAP
Inner 4 PWR
14. CMIC_PWR 37. CSB6_IMB_GPORTS 60 GSMI
15. CMIC_STRAPPING 38. CSB6_POWER 61 RESET_LOGIC
16. DDR_DIMM_1_&_2 39 PCI_IRQ_LATCH_LOGIC 62 I2C ADDRESS & PCIIRQ MAP
1 17. DDR_DIMM_3_&_4 40 PCI_SLOT_5_&_PULL_UP 63 REV_HISTORY 1
18. DDR_SERIAL_TERM 41 PCI_SLOT_6 64 I2C_ROUTING_MAP
19. DDR_1.25V_STLL2_TERM 42 BLANK
20. CLK_GENERATOR 43 ATI_RAGE_XL GIGABYTE TECHNOLOGY CORPORATION
21. ZCR_RAPTOR 44 FRAME_BUFFER_SDRAM Title
BLOCK DIAGRAM, INDEX
22. GLAN2_82540EM_PCI 45 VGA_CON Size Document Number Rev
23. GLAN2_82540EM_POWER 46 PCI_ARBITOR 8EGXDREL-01 1.0
Date: , 06, 2003 Sheet 1 of 64
A B C D E
A B C D E
RESET SCHEME RSB6
PS_PWRGD#
PLLRST PCIRST#
RESET FOR RSB POWER
t0
PCIRST# PCI BUS
PSU PWR GOOD t0+100mS
4 4
ATX PLL RST
t0+100mS
POWER PS_PWRGD PS_PWRGD#
POWERGOOD t0+120mS
SUPPLY
CONN. INVERTER PLLRST PCIRST#
VRM POWERGOOD
t0+50mS
CMIC
PROCESSOR POWERGOOD t0+120mS
PROC_RESET#
RESET GEN POWERGOOD CPU RESET
140mS PERIOD PROCESSOR RESET
RESET Vth = SRESET# RESETDLY# t0+120mS+1mS
4.5V Config RESET - 4
RESET SWITCH PCI RESET
BCLK delay w.r.t. t0+120mS+1mS
PROC_RESET#
CONFIG RESET
t0+120mS+1mS+4 clocks
CPU_PWRGD
3 3
CPU_VRM_PWRGD
AND
CLOCKING SCHEME: 1 Main Synthesizer (CK408)
- CPU 0
2 2
- CPU 1 From CLK BCLK 4 Pairs of 100MHz
- CMIC_SL SYNTH.
Differential CLOCKs
BCLK# CMIC_SL
for 4 DIMMs
CLK SYNTH.
BCLK 3 Pairs of 133MHz
BCLK#
Differential CLOCKs
n
33MHz 33MHz CLOCK TO RSB and
DEVICES behind it.
14.318 MHz
X-TAL
48MHz 48MHz USB CLK to RSB
48MHz 48MHz CLK to SIO
14MHz 14 MHz CLK to RSB
1 1
GIGABYTE TECHNOLOGY CORPORATION
Title
RESET and CLOCKING SCHEME
Size Document Number Rev
1.0
8EGXDREL-01
Date: , 06, 2003 Sheet 2 of 64
A B C D E
A B C D E
VCC3 VCC3 VCC3 VCC3 VCC3 VCC3
CPU_SDA 5,60
CPU_SCL 5,60
MID_CPU Pull-down CPU END THERMAL SMBUS ADDRESS
1K/6/X
1K/6/X
1K/6/X
1K/6/X
1K/6/X
-CPU_SMBALERT 5,37
1
1
1
1
1
C1126
= 98H
P1_SM_TS_ADDR1
P1_SM_TS_ADDR0
0.1U/6
VCC_P
49.9/6/1
49.9/6/1
P1_SM_ADDR2
P1_SM_ADDR1
P1_SM_ADDR0
10 P1_VCCA
1
1
1
10 P1_VCCIOPLL FSB_VCC_SENSE1
R798
R799
R800
R801
R802
TP174
49.9/6/1
49.9/6/1
2
2
2
2
2
10 P1_VSSA -DP[0..3] 5,11
1
FSB_GND_SENSE1 P1_SM_TS_ADDR1
2
TP175
1
P1_SM_TS_ADDR0
R803
R804
1 2 P1_ODTEN P1_TDO P1_SM_ADDR2
P1_COMP1 2
P1_COMP0 2
4 R807 49.9/6/1 P1_TDI P1_SM_ADDR1 4
P1_TCK P1_SM_ADDR0
R805
R806
AD29 P1_SM_WP
1 R808 2 1K/6 -P_TRDY
300/Intel
2
VCC3 -ITP_TRST -P_TRDY 5,11
-DP3
-DP2
-DP1
-DP0
CPU END DATA SMBUS ADDRESS
1K/6
1K/6
1K/6
1K/6
1K/6
2
1
1
1
1
1
P1_TMS
37,48,58,60 -CPU1_SKTOCC
= A0/A1
AC29
AC28
AD28
AD16
AC15
AC18
AE29
AE28
AA28
AB28
AB29
AA29
AE17
AE19
AD4
AD5
AA5
AB4
AA7
AE5
D26
C24
B27
Y29
E16
E25
E24
E19
A25
F24
W6
W7
W8
U69A
A3
B5
Y6
-PD[0..63]
R809
R810
R811
R812
R813
5,11 -PD[0..63]
2
2
2
2
2
TDO
ODTEN
VSSSENSE
VSSA
VCCSENSE
VCCA
SMB_WP
SM_VCC
SM_CLK
TCK
TMS
-DINV[0..3] 5,11
SKTOCC#
VCCIOPLL
SM_VCC1
SM_DAT
SM_ALERT
COMP1
COMP0
TESTHI0
TESTHI1
TESTHI2
TESTHI3
TESTHI4
TESTHI5
TESTHI6
TDI
SM_EP_A2
SM_EP_A1
SM_EP_A0
DP3#
DP2#
DP1#
DP0#
TRDY#
TRST#
SM_TS_A1
SM_TS_A0
-PD0 Y26
-PD1 D0# -DINV3
AA27 D1# DBI3# AB9
-PD2 Y24 AE12 -DINV2
-PD3 D2# DBI2# -DINV1
AA25 D3# DBI1# AD22
-PD4 AD27 AC27 -DINV0
-PD5 D4# DBI0# RN149 VCC_P
Y23 D5#
-PD6 AA24 8P4R/1K
-PD7 D6# P_VID0
AB26 D7# VID0 F3 1 2 VCC
ITP termination
1
-PD8 AB25 E3 P_VID1 3 4 VCC_P
-PD9 D8# VID1 P_VID2
AB23 D9# VID2 D3 5 6
-PD10 AA22 C3 P_VID3 7 8 R814
-PD11 D10# VID3 P_VID4 P1_TDO
AA21 D11# VID4 B3 1 R815 2 150/6 40.2/6/1/X
-PD12 AB20 2 1 P1_TDI 1 R816 2 150/6
-PD13 D12#
AB22 F9 P1_GTLREF1 R944 P1_TCK
2
-PD14 D13# GTLREF3 1K/6 P1_TMS
AB19 D14# GTLREF2 F23 1 R817 2 40.2/6/1
1
-PD15 AA19 W9 -ITP_TRST 1 R818 2 150/6
-PD16 D15# GTLREF1
AE26 D16# GTLREF0 W23 P1_GTLREF0 R819
-PD17 27.4/6/1
3
-PD18
-PD19
AC26
AD25
D17#
D18# DSTBP3# Y11 -DSTBP3
-DSTBP2
Differential Pair 3
AE25 D19# DSTBP2# Y14
-PD20 AC24