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1 2 3 4 5 6 7 8
PCB STACK UP
8L
QT6 BLOCK DIAGRAM 01
CPU CPU THERMAL
LAYER 1 : TOP SENSOR
Penryn 14.318MHz
A LAYER 2 : SGND PAGE 5 A
478P (uPGA)/35W
LAYER 3 : IN2 PAGE 3,4 CLK_CPU_BCLK,CLK_CPU_BCLK#
CLOCK GEN
LAYER 4 : SGND1 CLK_MCH_BCLK,CLK_MCH_BCLK#
DREFCLK,DREFCLK# ALPRS355B MLF64PIN
LAYER 5 : SVCC FSB 667/800/1066
DREFSSCLK,DREFSSCLK#
PAGE 2
LAYER 6 : IN2
LAYER 7 : SGND2 PS8101
LAYER 8 : BOT PAGE 20 27MHz
NORTH BRIDGE
DDRII 667/800 MHz HDMI CON
DDRII-SODIMM1
nVIDIA PAGE 20
VGA PAGE 12,13 Cantiga PCI-Express
Cable 16X NB9M-GE 64 Bit
RJ-45
Docking PM45,GM45 CRT
B CIR/Pwr btn DDRII-SODIMM2 DDRII 667/800 MHz
NB9P-GS 128 Bit B
SPDIF Out PAGE 12,13 PAGE 5~9
PAGE 20
Stereo MIC PAGE 12~18
Dual Link
969p
Headphone Jack LCD CONN Mini PCI-E Card x2
Express Card x1
USB Port
DMI LINK 32.768KHz PAGE 19 Cable Docking x1
PAGE 40 VOL Cntr NBSRCCLK, NBSRCCLK#
SATA - HDD
SATA0 150MB USB2.0 4,7,10,11
PAGE 36 0,1,8,9 5 3 2 12MHz 6
SYSTEM CHARGER(ISL6251AHAZ-T) USB2.0 Ports BlueTooth Webcam Fingerprint
SOUTH BRIDGE
PAGE 41 SATA1 150MB X4 PAGE 33 PAGE 33 PAGE 33 PAGE 33
SATA - CD-ROM CR for UMA
RTS5158E
PAGE 36 PAGE 27
SYSTEM POWER ISL6237IRZ-T
ICH9-M 24.576Hz
PAGE 42
E-SATA
SATA5 150MB PCI-E
PAGE 32 X2 X1 X1 X1
C DDR II SMDDR_VTERM Azalia C
1.8V/1.8VSUS(TPS51116REGR) Mini PCI-E Express
PAGE 46
Accelerometer
PAGE 32 SMBUS PAGE 21,22,23,24 LAN JMICRO 380
LIS3LV02DL Card Realtek Card
for Discrete
Analog (Wireless PCIE-LAN (NEW CARD)
VCCP +1.5V AND GMCH RTL8102E/8111C
LAN/TV)
1.05V(RT8204) 32.768KHz LPC IDT92HD71B7 (10/100/GagaLAN) PAGE 33 PAGE28
PAGE 43 MDC CONN PAGE 36
PAGE 31,32
PAGE 32 PAGE 29
VGACORE(1.025V)Oz8118 IEEE1394 Memory
PAGE 45 Keyboard ENE KBC 25MHz connect for
Discrete
CardReader
Touch Pad PAGE 37 AUDIO
only
Amplifier
KB3926 C0 SPI RJ45
TPA6017A2 PAGE 28 PAGE 29
CPU CORE ISL6266A Capacitive Sense PAGE 22
PAGE 34
PAGE 44 SW PAGE 37
PAGE 37
PAGE 31
D
microphone Audio Jacks Jack to D
(Phone/ MIC) Speaker
PAGE 30 PAGE 30 PAGE 31
GMT G9931P1U
SPI
PROJECT : QT6
FAN PAGE 38 Quanta Computer Inc.
PAGE 40
Size Document Number Rev
Custom
NB5 Block Diagram 1A
Date: Tuesday, February 26, 2008 Sheet 1 of 44
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
[4,6,9,10,11,12,14,15,19,20,21,22,23,24,25,26,27,28,29,30,31,33,35,36,37,41,44] +3V
02
[3,4,5,6,8,9,21,24,34,40,41] +1.05V
+3V
L38
1 2 +3V_CK_MAIN
HCB1608KF-181T15_6 U21
C513
C562 C511 C509 C541 C508 +3V_CK_MAIN 23 61
VDDPLL3 CPUCLKT0 CLK_CPU_BCLK [3]
10U/6.3V_8 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 16 60
A VDD48 CPUCLKC0 CLK_CPU_BCLK# [3] A
SRC8 RP49 4 3 *4P2R-S-0
9
4
VDDPCI
VDDREF
CK505 CPUCLKT1 58 CLK_MCH_BCLK [5]
SRC8# 2 1
CLK_CPU_ITP [3]
CLK_CPU_ITP# [3]
L42 46 57
VDDSRC CPUCLKC1 CLK_MCH_BCLK# [5]
1 2 +3V_CK_CPU +3V_CK_CPU 62
HCB1608KF-181T15_6 VDDCPU SRC8
CPUT2_ITP/SRCT8 54
+3V_CK_MAIN2 19 53 SRC8#
C542 C530 VDD96I/O CPUC2_ITP/SRCC8
27 VDDPLL3I/O
10U/6.3V_8 .1U/10V_4 33 20 SRC0
VDDSRCI/O DOTT_96/SRCT0 SRC0#
43 VDDSRCI/O DOTC_96/SRCC0 21 int
52 VDDSRCI/O
24 SRC1 SRC0 RP47 4 3 *4P2R-S-0
27MHz_Nonss/SRCCLK1/SE1 DREFCLK [6]
L43 56 25 SRC1# SRC0# 2 1
VDDCPU_IO 27Mhz_ss/SRCCLC1/SE2 DREFCLK# [6]
1 2 +3V_CK_MAIN2 55
HCB1608KF-181T15_6 NC
SRCCLKT2/SATACL 28 CLK_PCIE_NEW [33]
29 RP48 2 1 4P2R-S-0
SRCCLKC2/SATACL CLK_PCIE_NEW# [33] CLK_PCIE_VGA [12]
C554 C549 C561 C529 C566 C547 C539 CG_XIN 3 4 3
X1 CLK_PCIE_VGA# [12]
10U/6.3V_8 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 .1U/10V_4 CG_XOUT 2 31
X2 SRCCLKT3/CR#_C CLK_PCIE_CARD [26]
SRCCLKC3/CR#_D 32 CLK_PCIE_CARD# [26] discrete
*100K/F_4 R317 34
SRCCLKT4 CLK_PCIE_3GPLL [6]
SRCCLKC4 35 CLK_PCIE_3GPLL# [6] int
SRC1 RP50 2 1 *4P2R-S-0 DREFSSCLK [6]
63 45 SRC1# 4 3
[23] CK_PWG CK_PWRGD/PD# PCI_STOP# PM_STPPCI# [23] DREFSSCLK# [6]
+3V CPU_BSEL1 R312 2.2K_4 FSB 64 44
+3V FSLB/TEST_MODE CPU_STOP# PM_STPCPU# [23]
48 RP51 4 3 4P2R-S-33
SRCCLKT6 CLK_PCIE_ICH [22] 27M_NONSS [14]
SRCCLKC6 47 CLK_PCIE_ICH# [22] 2 1 27M_SS [14]
2
Q15 R297 R296 [10,11,28,33,36] CGCLK_SMB
7 SCLK SRCCLKT7/CR#_F 51 CLK_PCIE_WLAN [36] discrete
6 SDATA SRCCLKC7/CR#_E 50 CLK_PCIE_WLAN# [36]
2
B R279 10K/F_4 10K/F_4 [10,11,28,33,36] CGDAT_SMB B
10K/F_4 ME2N7002E 37
SRCCLKT9 CLK_PCIE_LAN [31]
3 1 CGDAT_SMB 22 38
[23] PDAT_SMB CLK_PCIE_LAN# [31]
1
GND SRCCLKC9
26 GND
TME 18 41
GND48 SRCCLKT10 CLK_PCIE_SATA [21]
59 GNDCPU SRCCLKC10 42 CLK_PCIE_SATA# [21]
15 GNDPCI
+3V 1 40
GNDREF SRCCLKT11/CR#_H CLK_PCIE_TVC [36]
30 GNDSRC SRCCLKC11/CR#_G 39 CLK_PCIE_TVC# [36]
Q16 36 GNDSRC
2
49 GNDSRC
ME2N7002E 8 R_CLK_NEWCARD_OE# R295 475/F_4
PCICLK0/CR#_A CLK_NEWCARD_OE# [33]
3 1 CGCLK_SMB 10 R_CLK_MCH_OE# R280 475/F_4
[23] PCLK_SMB PCICLK1/CR#_B CLK_MCH_OE# [6]
11 TME R276 33_4
PCICLK2/TME PCLK_DEBUG [36]
12 R_PCLK_KBC R288 33_4
PCICLK3 PCLK_KBC [35]
13 27M_SEL
PCICLK4/27_SELECT
0=overclocking
Y3 65
of CPU and EPAD ITP_EN R285 33_4
PCLK_ICH [22]
SRC Allowed CG_XIN 1 2 CG_XOUT 14 R308 22_4
PCI_F5/ITP_EN CLK_48M_USB [23]
R303 *22_4
CLK_48M_CR [25]
1 = overclocking 17 FSA R315 2.2K_4 CPU_BSEL0
14.318MHZ USB_48MHZ/FSLA
1
1
FSC R289 10K/F_4 CPU_BSEL2
of CPU and SRC C507 C512 5 FSLC R298 33_4
FSLC/TST_SL/REF CLK_14M_ICH [23]
not Allowed 33P/50V_4 33P/50V_4
2
2
SL28541BQCT
+3V
Change to 33p
C C
CK505 QFN64
2
des R293 ICS ICS9LPRS355BKLF ALPRS355000 +3V
10K/F_4 27M_SEL
PIN20 PIN21 PIN24 PIN25 Silego SLG8SP513VTR AL8SP513000
1
27M_SEL PIN13 CLK_MCH_OE# R277 2 1 10K/F_4
Realtek RTM875N-606-VD-GR AL000875000
2
0=UMA DOT96T DOT96C SRCT1/LCDT_100 SRCT1/LCDT_100 CLK_NEWCARD_OE# R294 2 1 10K/F_4
int R299
*10K/F_4
1 = External
1
VGA SRCT0 SRCC0 27Mout-NSS 27Mout-SS
0=UMA
1 = External VGA C501 *33P/50V_4 PCLK_KBC
FSC FSB FSA CPU SRC PCI C503 *27P/50V_4 PCLK_ICH
CPU Clock select
+3V C495 *33P/50V_4 PCLK_DEBUG
CPU_BSEL0 R321 0_4
1 0 1 100 100 33
[3] CPU_BSEL0 MCH_BSEL0 [6]
0 0 1 133 100 33 C518 *10P/50V_4 CLK_48M_USB
2
0 1 1 166 100 33 C514 *10P/50V_4 CLK_48M_CR
*10K/F_4 R314 *1K/F_4
R291 0 1 0 200 100 33 C506 *33P/50V_4 CLK_14M_ICH
R_PCLK_KBC CPU_BSEL1 R316 0_4
[3] CPU_BSEL1 MCH_BSEL1 [6]
1
D D
0 0 0 266 100 33 for EMI
ITP_EN
1 0 0 333 100 33
2
2
+1.05V R322 *1K/F_4
R283 1 1 0 400 100 33
10K/F_4 *10K/F_4 CPU_BSEL2 R278 0_4
PROJECT : QT6
[3] CPU_BSEL2 MCH_BSEL2 [6]
R292 1 1 1 RSVD 100 33
1K to NB only when
Quanta Computer Inc.
1
1
XDP is implement.No
+1.05V R281 *1K/F_4 XDP can use 0 ohm
Enable ITP CLK
Size Document Number Rev
Custom
NB5 Clock Generator 1A
Date: Tuesday, February 26, 2008 Sheet 2 of 44
1 2 3 4 5 6 7 8
5 4 3 2 1
[2,4,5,6,8,9,21,24,34,40,41] +1.05V
[5] H_A#[35:3]
H_A#3
H_A#4
J4
U34A
A[3]#
DGT^8000006
DGT^8000021
ADS# H1 H_ADS# [5] [5] H_D#[63:0]
U34B H_D#[63:0]
03
L5 A[4]# BNR# E2 H_BNR# [5]
ADDR GROUP 0
H_A#5 L4 G5 H_D#0 E22 Y22 H_D#32
A[5]# BPRI# H_BPRI# [5] D[0]# D[32]#
H_A#6 K5 H_D#1 F24 AB24 H_D#33
H_A#7 A[6]# H_D#2 D[1]# D[33]# H_D#34
M3 A[7]# DEFER# H5 H_DEFER# [5] E26 D[2]# D[34]# V24
H_A#8 N2 F21 H_D#3 G22 V26 H_D#35
A[8]# DRDY# H_DRDY# [5] D[3]# D[35]#
H_A#9 J1 E1 H_D#4 F23 V23 H_D#36
D A[9]# DBSY# H_DBSY# [5] D[4]# D[36]# D
H_A#10 N3 H_D#5 G25 T22 H_D#37
H_A#11 A[10]# H_D#6 D[5]# D[37]# H_D#38