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A B C D E
1 1
Compal Confidential
2
Schematics Document 2
AUBURNDALE/CLARKSFIELD with
Intel IBEX PEAK-M core logic
3
Versace 3
2009-07-24
REV:0.4
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/09/15 Deciphered Date 2009/09/15 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4951P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, July 28, 2009 Sheet 1 of 48
A B C D E
A B C D E
Compal Confidential
File Name : Versace Versace Accelerometer
LIS302DLTR
Page 31
Thermal Sensor Fan Control DDR3 1066/1333MHz 1.5V DDR3-SO-DIMM X 2
ADM1032 Page 4 Page 4
Mobile BANK 0, 1, 2, 3 Page 9
XDP Conn.
1 CPU Qual Core Channel A Page 4 1
Display Port X 2 PEG
(Docking) Page 29 MXM 3.0 Type A Connector Clarkesfield
Page 21 CK505
Socket-rPGA989 DDR3 1066/1333MHz 1.5V DDR3-SO-DIMM X 2 Clock Generator
BANK 0, 1, 2, 3 Page 10
37.5mm*37.5mm ICS9LPRS397
** Channel B
Page 4,5,6,7,8 Page 12
CRT to Docking CRT+USB X DP conn LCD conn
Page 29 2 CONN Page 19 Page 20 Page 20
USB x2(Docking)Page 33
DMI X4
Express Card 54 USB X 2 (For I/O) * USB x1(Sub/B for Exp Card)
Page 19
& Card Reader WLAN Card USB3.0 X 2 Page 34
Sub-board UPD720200F1
Page 24 Page 27
FingerPrinter VFM451 daughter board
Page 30
USB2.0 USB2.0 USBx1 Page 28
*
2
USB conn x 1 (For I/O) 2
PCI-E BUS Azalia
BT Conn USB x 1 Page 26
PCI BUS
Intel Ibex Peak M USB x1(Camera)
SATA0 Page 20
10/100/1000 LAN
Intel Hanksville-LM 1071pins USB X1(WWAN Card)
82577LM 25mm*27mm Page 24
Page 22 RICOH 835 SATA1
SATA2
MDC V1.5 RJ11Page 23
CONN
Page 32 Page 25
Page 13,14,15,16,17,18
92HD75
RJ45 CONN * Audio CKT
ONFI Interface
Sub-board Page 30
Page 23
1394 port Card Reader
Conn Braidwood SATA ODD Connector
Page 28 Page 13
3
Mini-Card 2.5" SATA HDD Connector LED 3
LPC BUS NAND Flash Page 13
Page 29
ESATA Connector
Page 13
Power OK CKT.
TPM1.2 SMSC KBC Super I/O *: We will inatll them on same sub Page 33
Docking CONN. SLB9635TT 1098 LPC47N217 board via a board to board
(2) PS/2 Interfaces Page 28 page 31 Page 33
connector.
(2) USB 2.channels
(2) SATA Channels (SATA3&4) **: Daughtor board for stack-up Power On/Off CKT.
(2) Display Port Channels Touch Pad CONN. Page 25
Page 25
USB CONN and VGA CONN.
(1) Serial Port
(1) Parallel Port C OM1 LPT
(1) Line In TrackPoint CONN. ( Docking ) ( Docking )
Int.KBD Page 28 Page 28 DC/DC Interface CKT.
(1) Line Out Page 25
Page 34
(1) RJ45 (10/100/1000) Page 25
4 (1) VGA SPI ROM 4
(1) 2 LAN indicator LED's 4MB X 2 Page 27
(1) Power Button
(1) I2C interface Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/09/15 Deciphered Date 2009/09/15 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4951P 0.4
Page. 27 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, July 28, 2009 Sheet 2 of 48
A B C D E
A
( O MEANS ON X MEANS OFF ) Symbol Note :
Voltage Rails
+RTCVCC +B +5VALW +1.5V +5VS : means Digital Ground
+3VL +3VALW +0.75V +3VS
+1.5VS
power
plane +NVVDD : means Analog Ground
+VCCP
+CPU_CORE
+1.05VS
+1.8VS
State
Install below 43 level BOM structure for ver. 0.1
DEBUG@ : means just build when PCIE port 80 CARD function enable. Remove before MP
S0
O O O O O M92@ : Install for M92 Graphic controller
S1 8072@ : Install for 8072 NIC controller
O O O O O
S3
1098@ : Install for 1098 KBC controller
O O O O X
CK32@ : Install for 32 pin CLOCK GEN
S5 S4/AC
O O O X X
Install below 45 level BOM structure for ver. 0.1
S5 S4/ Battery only
O O X X X 45@ : means just put it in the BOM of 45 level.
S5 S4/AC & Battery
don't exist
O X X X X
1 1
Reserve below BOM structure for ver. 0.1
@ : means just reserve , no build
CONN@ : means ME part.
M93@ : Install for M93 Graphic controller
8075@ : Install for 8075 NIC controller
SMBUS Control Table 1091@ : Install for 1091 KBC controller
THERMAL CK72@ : Install for 72 pin CLOCK GEN
SOURCE BATT XDP SODIMM CLK CHIP MINI CARD DOCK NIC SENSOR G-SENSOR
SMB_EC_CK1
SMB_EC_DA1
SMSC1098 V X X X X X X X X
SMBCLK
SMBDATA
Calpella X V V V V V X X X
SML0CLK
SML0DATA
Calpella X X X X X X V X X
SML1CLK
SML1DATA
Calpella X X X X X X X V V
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/09/15 Deciphered Date 2009/09/15 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-4951P 0.4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, July 28, 2009 Sheet 3 of 48
A
5 4 3 2 1
Layout rule 10mil width trace
Change
Thermal Sensor EMC2113 with CPU PWM FAN R10 to
length < 0.5", spacing 20mil
JCPU1B
Removed RP1 & RP3 connect to U3. 10/27
Layout note: 6.8K to R1 1 2 20_0402_1% AT23 COMP3
+3VS A16
1. Place C1 & C408 close to U1 pin. setup Q1 BCLK CLK_CPU_BCLK_P 16
MISC
R2 1 2 20_0402_1% AT24 B16
2. Place U1 close to JCFAN1. E-diode1. COMP2 BCLK# CLK_CPU_BCLK#_P 16
Change R5 to 22ohm
CLOCKS
U1 Add C408. 11/30 12/04 R3 1 2 49.9_0402_1% G16 AR30 CLK_CPU_XDP
from 68ohm. 11/30 COMP1 BCLK_ITP
2
EMC2113-2-AX_QFN16_4X4 AT30 CLK_CPU_XDP#
R5 R4 1 BCLK_ITP#
2 49.9_0402_1% AT26 COMP0
22_0402_5% H_THERMDC 1 16 REMOTE2+ E16
DN DP2/DN3 PEG_CLK CLK_EXP 14
PEG_CLK# D16 CLK_EXP# 14
1 2 H_THERMDA 2 15 REMOTE2- 1 2 PAD T1 TP_SKTOCC# AH24
1
C1 2200P_0402_50V7K DP DN2/DP3 2200P_0402_50V7K C408 SKTOCC#
A18
D +3VS_THER 3 14 R9 1 2 2.05K_0402_1%
DPLL_REF_SSCLK
A17 Intel doc 395136: D
VDD TRIP_SET DPLL_REF_SSCLK#
0.1U_0402_16V4Z
R35 1 2 10K_0402_5% +VCCP 1 2 H_CATERR# AK14 Remove R6 & R7 connect to GND directly. 11/06
CATERR#
THERMAL
C2
1 FAN_PWM 4 13 R10 1 2 6.8K_0402_5% +3VS R8 49.9_0402_1%
31 FAN_PWM PWM_IN SHDN_SEL
+3VS R13 1 2 10K_0402_5% 5 12 F6
ADDR_SEL GND SM_DRAMRST# SM_DRAMRST# 11
1 2 H_PECI_ISO AT15
2 16 H_PECI PECI
6 11 FAN_PWM_OUT R133 1 2 +3VS R11 0_0402_5% AL1 SM_RCOMP0 R12 1 2 100_0402_1%
16,21 THERM_SCI# ALERT# PWM SM_RCOMP[0]
10K_0402_5% AM1 SM_RCOMP1 R14 1 2 24.9_0402_1%
R18 1 TACH SM_RCOMP[1] SM_RCOMP2 R15
+3VS 2 7 SYS_SHDN# TACH 10 SM_RCOMP[2] AN1 1 2 130_0402_1%
@ 10K_0402_5% H_PROCHOT# 1 2 H_PROCHOT#_D AN26
GND
43 H_PROCHOT# PROCHOT#
8 9 SMB_CLK_S3 9,10,12,14,26 R16 0_0402_5% AN15 PM_EXTTS#0 R17 1 2 10K_0402_5% +VCCP
SMDATA SMCLK PM_EXT_TS#[0]
DDR3
MISC
AP15 PM_EXTTS#1 R19 1 2 0_0402_5%
PM_EXT_TS#[1] PM_EXTTS#1_R 9,10
H_THERMTRIP# 1 2 R20 1 2 10K_0402_5% +VCCP
17
R21 0_0402_5% H_THERMTRIP# 1 2 H_THERMTRIP#_R AK15
16 H_THERMTRIP# THERMTRIP#
Install R133. 7/14 R22 0_0402_5%
9,10,12,14,26 SMB_DATA_S3
AT28 XDP_PRDY#
PRDY#
Add PD R211 for FAN_PWM. 11/30 PREQ# AP27 XDP_PREQ# Place close to JCPU1.
FAN_PWM R211 1 2 10K_0402_5% AN28 XDP_TCK R23 1 2 @ 51_0402_5%
H_CPURST# TCK
1 2 H_CPURST#_R AP26 RESET_OBS# TMS AP28 XDP_TMS
PWR MANAGEMENT
R24 0_0402_5% AT27 XDP_TRST#
TRST#
JTAG & BPM
Q24 1 2 H_PM_SYNC_R AL15 AT29 XDP_TDI
15 H_PM_SYNC PM_SYNC TDI
2N7002_SOT23-3 R25 0_0402_5% AR27 XDP_TDO
TDO XDP_TDI_M
AR29
H_THERMTRIP# 1 H_CPUPW RGD 2 VCCPW RGOOD_1 AN14
TDI_M XDP_TDO_M Follow DIOR's design. 2/20
D
S
3 H_THERMTRIP#_U1 21 1 VCCPWRGOOD_1 TDO_M AP29
R26 0_0402_5%
AN25 XDP_DBRESET#
DBR# XDP_DBRESET# 13,15
H_CPUPW RGD 1 2 VCCPW RGOOD_0 AN27
G
16 H_CPUPW RGD
2
R27 0_0402_5% VCCPWRGOOD_0
PW R_GD 11,13,31,34
AJ22 XDP_BPM#0_R R126 1 2 0_0402_5% XDP_BPM#0
C BPM#[0] C
Change Q24.2 connect from +3VS to PWR_GD. 12/11 15 PM_DRAM_PWRGD 1 2 VDDPW RGOOD_R AK13 SM_DRAMPWROK BPM#[1] AK22 XDP_BPM#1_R R127 1 2 0_0402_5% XDP_BPM#1
R28 0_0402_5% AK24 XDP_BPM#2_R R141 1 2 0_0402_5% XDP_BPM#2
BPM#[2] XDP_BPM#3_R R142 0_0402_5% XDP_BPM#3
BPM#[3] AJ24 1 2
AM15 AJ25 XDP_BPM#4
REMOTE thermal sensor 34 VTTPWRGOOD VTTPWRGOOD BPM#[4]
BPM#[5] AH22
AK23
XDP_BPM#5
XDP_BPM#6
H_PWRGD_XDP 1 BPM#[6]
2 H_PW RGD_XDP_R AM26 TAPPWRGOOD BPM#[7] AH23 XDP_BPM#7
Layout note: R30 0_0402_5%
1. Place Q1 close to bottom DDR DIMM. 1 2 PLT_RST#_R AL14
Intel S3 16 BUF_PLT_RST# RSTIN#
1
C