Text preview for : File_Server_Theory_of_Operation_Apr85.pdf part of apple File Server Theory of Operation Apr85 apple file_server File_Server_Theory_of_Operation_Apr85.pdf
Back to : File_Server_Theory_of_Ope | Home
File Server
Theory of Operation
Michael Dhuey
Ron Hochsprung
4 - 3 - 85
Table of 'Contents
Introduction 2
1.0 Memory State Machine 4
1.1 Memory Map 7
1.2 CLOCKS PAL 11
1.3 DECODE1 PAL 12
1.4 DECODE2 PAL 12
1.5 RAMSM1 PAL 13
1.6 RAMSM2 PAL 13
1.7 IRQ PAL 26
2.0 Disk State Machine 27
2.1 Control Register 31
2.2 MISC PAL 32
2.3 DSTATE PAL 33
2.4 ENDCNT PAL 40
2.6 BCOUNT PAL 40
2.7 SHIFT PAL 42
2.8 SYNC1 PAL 42
2.9 SYNC2 PAL 42
2.10 ECCChip 45
2.11 Disk RAM Buffer 45
3.0 Disk Servo / Clock Interface 50
3.1 Versatile Interface Adapter (65C22) 50
3.2 Real Time Clock 56
3.3 SERIAL PAL 56
3.4 Soft Power 56
4.0 Serial Interface 58
4.1 Serial Communications Controller (8530) 58
4.2 MINI DIN-8 connectors 59
5.0 Small Computer Standard Interface (5380) 62
File Server - Theory of Operation (Preliminary ) April 3, 1985 Page 1
Introduction
The File Server (FS) is designed to be a shared 20 (or 40) M byte file system for Macintosh.
It contains one (or two) 20 Mbyte Winchester technology hard disks, 1 M byte of memory mapped
RAM with 8 contexts, 64 K bytes of ROM, an 8 MHz 68000 CPU, two serial ports, and a SCSI
compatible port. It is normally a shared resource on AppleTalk at 230.4 K baud. The Small
Computer Standard System Interface (SCSI) is compatible with industry standard data storage
devices such as Winchester disks, tape drives, and printers. It provides both expansion and media
compatibility to devices not directly supported by Apple.
The FS design can be divided into five logical components: the memory state machine, the
disk state machine, the serial interface, the disk servo/clock interface, and the SCSI interface.
The memory state machine interfaces the 68000 CPU to the RAM, ROM, VIA, SCC, Disk
command latch, and SCSI interface. It generates a series of system clocks from the 31.3344 MHz
crystal by simple division and a little cycle stretching. These clocks are combined with signals from
the 68000 CPU to generate the RAM, ROM, VIA, SCSI and SCC access timing. The memory state
machine gives priority access of RAM to the disk state machine at the expense of the 68000 CPU.
This is transparent to the 68000 as it is merely held off while the Direct Memory Access (DMA) is
being made. The high order 68000 address bits are sent through a memory mapper. This maps the 2
M bytes of virtual RAM into 1024 2K byte pages for each of eight contexts. Each page can be
protected from any access or write protected from write access. These protection bits are used in the
user state of the 68000. All I/O devices are protected from access in the User state of the 68000.
The disk state machine interfaces the 16 bit words of the RAM to the bit stream on the disk.
It contains a 16 bit shift register, a RAM address counter, a 4 bit counter, a state sequencer, an Error
Correction Chip (ECC), and an address decoder. All transfers of data to or from the disk are through
DMA accesses to the top 1 K bytes of physical RAM. This area is accessed by the disk state machine
to bring sectors of 532 bytes of data to or from the disk. The sectors are transferred with one of four
state sequences: format, read-ID, read, and write. Format is only used to write the initial headers and
data on the disk when it is new. Read-ID reads the next sector that comes under the head into
memory. This avoids header comparesand allows the fastest possible access. Read reads the sector
if the header in RAM matches the one on the disk. Write writes the sector from RAM if the header in
RAM matches the one on the disk.
The serial interface is the Serial Communications Controller (SCC) chip and driver and
receiver chips. The SCC is the 4 MHz Z8530 chip from Zilog and the drivers are two 26LS30 chips
and the receivers are two 75175 chips. The SCC is capable of most serial communications protocols
such as asynchronous, synchronous, BISYNC, HOLC, and SDLC. It can also FM encode the data
stream for self-clocking modes used at high data rates. The 26LS30 and 75175 driver and receiver
chips allow RS-232C as well as RS-422 modes of connection. The RS-232C mode provides the
additional handshake lines Data Carrier Detect (DCD), Request To Send (RTS), and Clear To Send
(CTS). This allows the use of asynchronous auto-answer modems. Port A of the SCC can also
support synchronous modems.
The disk servo/clock interface is used to control the movement of the read/write head of the
disk and to access the real time clock chip. The interface consists of a Versatile Interface Adapter
(VIA), a real time clock chip, a PAL (SERIAL), and a 74LS32. The 74LS32 is purely to hold the
address lines to the register selects high until an actual access from the 68000. If the address lines are
allowed to float the VIA is unreliable. The VIA contains a system timer to generate a 16 ms interrupt
similar to the Macintosh. Also, the 1 second interrupt of the real time clock is available. The SERIAL
PAL is used to connect the 8 bit synchronous shift register of the VIA to the disk servo and the real
File Server - Theory of Operation (Preliminary ) April 3, 1985 Page 2
time clock. Commands to move the disk head are sent to the servo as a sequence of asynchronous
characters. The SERIAL PAL generates the start and stop bits to make the 8 bit shift register into the
10 bit asynchronous character. It also reverses the line to receive status from the servo.
Finally, the SCSI interface is the expansion port to allow high capacity and high
performance peripherals to be added to .the FS. It consists of an NCR5380 SCSI controller chip.
This 40 pin DIP is the complete interface and drives the SCSI bus directly.
Additional documents related to this design are:
MC68000 16-BIT MICROPROCESSOR, Motorola Semiconductor, 1983;
ZILOG 1983/84 COMPONENTS DATA BOOK, Zilog, 1983;
PAL PROGRM:rv.1ABLE ARRAY LOGIC HANDBOOK, Monolithic Memories Inc., 1983;
SERIAL CLOCK AND 256 BYTE RAM SPECIFICATION, Bob Bailey, 7-2-84;
50 WATT INTERNATIONAL POWER SUPPLY - THEORY OF OPERATION, David
Egner;
SPECIFICATION - 20MB RIGID DISK DRIVE, John Moon, 1-12-85;
NCR 5380 SCSI INTERFACE CHIP PRELIMINARY DESIGN MANUAL, NCR
Microelectronics Division;
SCSI SMALL COMPUTER SYSTEM INTERFACE, ANSI X3T9.2/82-2 - Rev. 14,5-
2-84.
MINI-DIN CONNECTOR SCHEME, Peter Ashkin, 1-25-85.
File Server - Theory of Operation (Preliminary ) April 3, 1985 Page 3
1.0 Memory State Machine
The memory state machine consists of the PALs: CLOCKS, RAMSM1, RAMSM2, and
DECODE 1, DECODE2. They generate the control signals for the 68000 CPU, the RAM chips, the
RAM address multiplexers, the RAM data bus buffers, the memory map, the ROMs, the VIA, the
SCC, the SCSI, and the disk command latch.
The 16 Mbyte address space of the FS is divided into 4 sections: RAM, ROM, memory map,
and 1/0 (Figure 1.1). Each of these sections is 4 Mbytes of the address space. The RAM section
represents the first 4 Mbytes of the address space. This section is implemented as a 2 Mbyte logical
address space with 2 Kbyte pages. This is mapped to a physical address space of 1 Mbytes. The
ROM section represents the second 4 Mbyte section. It is a 64 Kbyte ROM physical address space.
The memory map section is the third 4 Mbyte section. It holds the physical page address and
protection for each of the logical pages. There are 8 versions or contexts of the logical address space.
This is to allow rapid context switching from user to user to supervisor states. When the supervisor
state is active context 0 is used. When the user state is active the context register, which is part of the
control register, contains the active context number. The top 4 Mbyte section of the address space is
the I/O address space. The control register, SCC, SCSI, and VIA occupy the I/O address space.
This address space, as well as the memory map, is only accessible in supervisor state.
The FS data bus is separated into two 16 bit components as shown in Figure 1.2. The main
component connects the 68000 CPU to the RAM buffers, the memory map, the control register, the
ROMs, the.SCC, the VIA, and the SCSI interface. The RAM chips are on a separate bus with the
disk state machine and the RAM buffer. The RAM buffer connects the two buses when the 68000
accesses RAM. This allows the higher priority memory accesses by the disk state machine to occur
directly to the RAM while the RAM buffer prevents the 68000 CPU from interfering. In fact, the
68000 is free to access anything except the RAM while the DMA from the disk state machine is
occurring.
Important:
The 68000 Test and Set (TAS) instruction must not be used. The instruction takes too
long to execute to guarantee the DMA memory cycles will occur properly. This is a requirement of
Macintosh and Lisa software as well so this is not a serious limitation.
File Server - Theory of Operation (Preliminary ) April 3, 1985 Page 4
Figure 1.1 Address Space
File Server - Theory of Operation (Preliminary ) April 3, 1985 Page 5
68000 ... 16 ....
16
.... ....
....
AppleTalk
RS-232
. 8
.. ...
8