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Burroughs
BURROUGHS SCIENTIFIC PROCESSOR
PARALLELISM - THE DESIGN STRATEGY FOR THE BSP
SSP -~------------------ BURROUGHS SCI ENTI F IC PROCESSOR
CONTENTS
Page
AN OVERVIEW A-l
BSP Objective A-l
BSP System A-2
BSP Key Features A-3
BSP Organization A-3
BSP Characteristics A-4
Parallel Processor A-4
Conflict-free Memory Access A-4
Vector Performance A-5
Performance Optimization A-5
File Memory A-6
Vectorizing FORTRAN Compiler A-6
BSP Design A-7
BSP Superiority A-7
IN PERSPECTIVE A-9
The BSP - ANew Approach A-9
Linear Vectors A-l0
A Different Kind of Supercomputer A-ll
System Manager A-ll
Overlapped Instruction Mode A-ll
Linear Vector Approach to Parallelism A-12
Scalar Operations A-13
BSP Approach to Scalars A-14
The BSP Design A-15
110 Subsystem A-15
Computational Envelope A-16
File Memory A-16
Summary A-17
PARALLEL ARCHITECTURE A-19
Parallelism A-19
Templates A-~H
Arithmetic Elements A-22
Conflict-free Memory Access A-25
Parallel Processor Control Unit A-27
Scalar Processing Unit A-29
BSP Software A-30
A-iii
~~~ ~~~~~~~~~~~~~~~~~~~~~BURROUGHSSCIENTIFIC PROCESSOR
SSP HU R H () U ( 1 H .(~ ;-; C lEN T IF! C PH () CESS 0 R
BURROUGHS SCIENTIFIC PROCESSOR
PARALLEL ARCHITECTURE
PARALLELISM
The capability of the Burroughs Scientific Processor (BSP) to sustain high
processing rates is achieved via unique parallel designs. The BSP comprises
multiple processors arranged to operate in parallel. The combined potential
of multiple processors is brought to bear on large computational applications.
Figure 3 illustrates the overall architecture of the Burroughs Scientific Processor
(BSP). Four types of parallelism are featured within this architecture; that is,
four different classes of computation occur simultaneously. They are:
1. The arithmetic performed by the 16 arithmetic elements (AE's),
2. Memory fetches and stores, and the transmission of data
between memory and the AE' s,
3. Indexing, vector length, and loop control computations in the
parallel processor control unit,
4. The generation of linear vector operation descriptions, which
takes place in the scalar processor unit (SPU).
The BSP is analogous to an efficiently operated business. The SPU and its control
memory are the executive suite. The executive's instructions are passed to the
administrative clerks in the parallel processor control unit. This unit then does
the bookkeeping and keeps all the major components of the business as busy and
as efficient as possible.
A-19
~~p ~~~~~~~~~~~~~~~~~~~~-BURROUGHSSC'ENT'F'CPROCESSOR
FILE MEMORY
FI LE STORAGE UNIT
DATA AND PROGRAM (4 - 64 M WORDS)
FI LE TRANSFERS
(1.5 M BYTES/SEC) FILE MEMORY
CONTROLLER
75 M BYTE/SEC
CONTROL UNIT PARALLEL PROCESSOR
CONTROL PROCESSOR
MEMORY
(256 K WORDS) -- PARALLEL MEMORY
(0.5 - 8 M WOR OS)
SCALAR 100 M WORDS/SEC
PROCESSOR I
ALIGNMENT NETWORK
MCPAND 11
MAINTENANCE
COMMUNICATIONS CONTROL
AND