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1 2 3 4 5 6 7 8
PCB STACK UP www.bufanxiu.com
BU1 Block Diagram
LAYER 1 : TOP
LAYER 2 : SGND
Intel
LAYER 3 : IN1
CLOCK GENERATOR
Merom CK505
A A
LAYER 4 : IN2 (35W) ICS9LPR363
Page 2
LAYER 5 : VCC Page 3,4
LAYER 6 : BOT FSB(667/800MHZ)
R.G.B
CRT
Page 18
VCC_CORE 533/ 667 MHZ DDR II DDRII-SODIMM1
LVDS X1
LCD(WXGA 13W) Crestline GM DDRII-SODIMM2
Page 18 Page 12,13
+1.5V
SATA Page 5,7,8,9,10,11
SATA - HDD
Page 19 G SENSOR
+1.05V
PATA
IDE - ODD DMI(x2/x4)
Page 19
B +1.25V B
System 0
Page 24 USB PORT 0
PCI-Express
+1.8VSUS System 1
Page 24 USB PORT 1
ICH8M MINI CARD MINI CARD NEW CARD 100/10 LAN
+3VPCU System 2
WLAN RTL8101E
+3V_S5 Page 24 USB PORT 2 USB 2.0 Page 23 Page 23 (BOT) Page 24 (BOT) Page 20
+3VSUS
+3V WLAN
+5VPCU Page 23 USB PORT 3
+5V_S5 Connector
DAUGHTER Azalia PCI Bus
RJ11/RJ45/USB DAUGHTER BOARD
+5V BORD
Finger Printer (BOT) Page 14,15,16,17
SMDDR_VTERM Page 24 USB PORT 4
SMDDR_VREF PCMCIA Card RJ45 RJ11 USB
Bluetooth (BOT) LPC
32.768KHz
Controller Reader/1394
Page 24 USB PORT 5 (CB 1410) (R5C833)
Page 21 (BOT) Page 22
C New Card (BOT) C
Page 24 USB PORT 6 PCMCIA 1394
(BOT)
5 IN 1 (BOT)
Reserved (BOT)
WPC8763LDG
Page 23 USB PORT 7
PCI ROUTING
Page 26
TABLE IDSEL INTERUPT DEVICE
Camera (BOT)
REQ0# / GNT0# AD17 INTA#,INTB# R5C832
Page 18 USB PORT 8 REQ1# / GNT1# AD20 INTC# CB1410
FAN Touch Key FLASH
AUDIO/FM/USB DAUGHTER BOARD PAD Board ROM
HP HP AMP AUDIO CODEC
(ALC262) Connector
INT SPK SPK AMP BTO BOM OPTION
MDC 1.5 CB@ : CARD BUS
FP@ : FINGER PRINTER
D BT@ : BLUETOOTH D
Page 25 CM@ : CAMERA
GS@ : G-SENSOR
NEW@ : NEW CARD
USB LCD@ : LCD TYPE PANEL
LED@ : LED TYPE PANEL
1394@ : 1394
Quanta Computer Inc.
RJ11 PROJECT : BU1 Santa Rosa
Size Document Number Rev
Block Diagram 1A
Date: Monday, March 26, 2007 Sheet 1 of 33
1 2 3 4 5 6 7 8
5 4 3 2 1
Clock Generator www.bufanxiu.com Gen Differential IO power
Clock +1.25V_VDD +1.25V
L25
+3V L26 PBY160808T-301Y-N_6 C411 .1U_4 PBY160808T-301Y-N_6
'EMI FILTER BKP1608HS181-T(180,1.5A)'
C426 C427 C428 C422 C425 C424 C419 C420 C416
R90
C414 .1U_4 *10U_810U_8 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4
10U_8
D 0_6 C408 10U_8 D
H=1.2mm ICS9LPRS365BGLFT
0.1U close to each VDD_IO Power pin
SLG8SP512T: AL8SP512K05
C43 .1U_4 U22 IC(64P) ICS9LPRS365BGLFT(TSSOP)
VDD_CK_VDD_PCI 2 48
C418 .1U_4 VDD_CK_VDD_48 VDD_PCI IO_VOUT
9 VDD_48
VDD_CK_VDD_PCI 16 64 CGCLK_SMB
VDD_CK_VDD_REF VDD_PLL3 SCLK CGDAT_SMB
61 VDD_REF SDA 63
R404 CK505
C412 .1U_4 VDD_CK_VDD_PCI 39 38 PM_STPPCI# [16]
VDD_CK_VDD_CPU VDD_SRC SRC5/PCI_STOP#
55 VDD_CPU SRC5#/CPU_STOP# 37 PM_STPCPU# [16]
0_6
R68 +1.25V_VDD 12 54 CLK_CPU_BCLK_R RP50 1 2 0X2
VDD_96_IO CPU0 CLK_CPU_BCLK [3]
C415 .1U_4 20 53 CLK_CPU_BCLK#_R 3 4
VDD_PLL3_IO CPU0# CLK_CPU_BCLK# [3]
26 VDD_SRC_IO_1
0_6 45 51 CLK_MCH_BCLK_R RP52 1 2 0X2
VDD_SRC_IO_3 CPU1 CLK_MCH_BCLK [5]
36 50 CLK_MCH_BCLK#_R 3 4
VDD_SRC_IO_2 CPU1# CLK_MCH_BCLK# [5]
49 VDD_CPU_IO
SRC8/ITP 47
SRC8#/ITP# 46
R85 56_4 PCLK_DEBUG_R 1 35 CLK_PCIE_3GPLL#_R RP58 1 2 0X2
[23,26] PCLK_DEBUG PCI0/CR#_A SRC10# CLK_PCIE_3GPLL# [6]
34 CLK_PCIE_3GPLL_R 3 4
SRC10 CLK_PCIE_3GPLL [6]
PCI4/SRC5_EN: PU be used, R81 56_4 PCLK_PCM_R 3
[21] PCLK_PCM PCI1/CR#_B
the CK505 will be configured to +3V R86 10K_4 33 CLK_MCH_OE#_R R410 475_4 CLK_MCH_OE# [6]
R78 56_4 PCLK_R5C833_R SRC11/CR#_H NEW_CLKREQ#_R R412 475_4
use Pin37/38 to SRC5 clock.If [22] PCLK_R5C833 4 32 NEW_CLKREQ# [24]
R82 *10K_4 PCI2/TME SRC11#/CR#_G
PD be detect at powe-on,the
CK505 will setting Pin 37/38 to R405 56_4 PCLK_591_R 5 30 CLK_PCIE_NEW_R RP59 3 4 0X2
[26] PCLK_591 PCI3 SRC9 CLK_PCIE_NEW [24]
PCI_STOP/CUP_SOTP(Default +3V R74 *10K_4 31 CLK_PCIE_NEW_R# 1 2
SRC9# CLK_PCIE_NEW# [24]
is setting to R73 22_4 PCI_CLK_SIO_R 6
R79 10K_4 PCI4/SRC5_EN CLK_PCIE_MINI2_R RP54
PCI_STOP/CUP_SOTP) SRC7/CR#_F 44 1 2 0X2 CLK_PCIE_MINI2 [23]
C R406 56_4 PCLK_ICH_R CLK_PCIE_MINI2#_R C
7 PCIF5/ITP_EN SRC7#/CR#_E 43 3 4 CLK_PCIE_MINI2# [23]
+3V R409 *10K_4
CG_XIN 60 41 CLK_PCIE_MINI_R RP56 1 2 0X2
[15] PCLK_ICH XTAL_IN SRC6 CLK_PCIE_MINI [23]
R407 10K_4 40 CLK_PCIE_MINI#_R 3 4
SRC6# CLK_PCIE_MINI# [23]
CG_XOUT 59 XTAL_OUT CLK_PCIE_LAN_R RP57
PCIF5/ITP_EN: PU be used,
SRC4 27 3 4 0X2 CLK_PCIE_LAN [20]
the CK505 will be configured R71 33_4 FSA 10 28 CLK_PCIE_LAN#_R 1 2
[16] CLKUSB_48 USB_48/FSA SRC4# CLK_PCIE_LAN# [20]
to use Pin46/47 to CPU ITP CLK_BSEL0 R72 2.2K_4
clock.If PD be detect at CLK_BSEL1 57 24 CLK_PCIE_ICH_R RP55 3 4 0X2
FSB/TEST/MODE SRC3/CR#_C CLK_PCIE_ICH [15]
powe-on,the CK505 will setting 25 CLK_PCIE_ICH#_R 1 2
SRC3#/CR#_D CLK_PCIE_ICH# [15]
Pin 46/47 to SRC8(Default is CLK_BSEL2 R87 2.2K_4 FSC 62 REF0/FSC/TESTSEL CLK_PCIE_SATA_R RP53
setting to SRC8) SRC2/SATA 21 3 4 0X2 CLK_PCIE_SATA [14]
R88 33_4 8 22 CLK_PCIE_SATA#_R 1 2
[16] 14M_ICH VSS_PCI SRC2#/SATA# CLK_PCIE_SATA# [14]
11 VSS_48
15 17 DREFSSCLK_R RP13 1 2 0X2
VSS_IO SRC1/SE1 DREFSSCLK [6]
19 18 DREFSSCLK#_R 3 4
VSS_PLL3 SRC1#/SE2 DREFSSCLK# [6]
52 VSS_CPU
23 13 DREFCLK_R RP51 3 4 0X2
VSS_SRC1 SRC0/DOT96 DREFCLK [6]
29 14 DREFCLK#_R 1 2
VSS_SRC2 SRC0#/DOT96# DREFCLK# [6]
42 VSS_SRC3
58 VSS_REF CKPWRGD/PWRDWN# 56 CK_PWRGD [16]
ICS9LPRS365AGLFT/ SLG8SP512T During initial power-up be used to
sample FSB speed with FSA/B/C
H=1.5mm
C407 30P_4 CG_XIN
(1)PCI2/TME: PU be used, the CK505 cannot over clock any of the clock for Trust Mode security purposes.
2
Y6
CL=20p (2)PCI4/SRC5_EN: PU be used, the CK505 will be configured to use Pin37/38 to SRC5 clock.
14.318MHZ If PD be detect at powe-on,the CK505 will setting Pin 37/38 to PCI_STOP/CUP_SOTP
Clock Gen I2C
(Default is setting to PCI_STOP/CUP_SOTP) +3V
1
B C406 30P_4 CG_XOUT B
(3)PCIF5/ITP_EN: PU be used, the CK505 will be configured to use Pin46/47 to CPU ITP clock. Q3
XTAL length < 500mils If PD be detect at powe-on,the CK505 will setting Pin 46/47 to SRC8 RHU002N06 R94
2
(Default is setting to SRC8)
10K_4
3 1 CGDAT_SMB
[13,16,19,23,24] SDATA
(4)SLG8SP512 Pin 6 select Pin 17, 18 output is LCDCLK or 27 M, PD is LCDCLK, PU is 27 M ,
Pin 37, 38 will fixed be use CPU_Stop and PCI_Stop.
(5)SLG505YC64 CK505 Standar parts follow standar setting +3V
Q4
CPU Clock select
RHU002N06 R95
2
BSEL Frequency Select Table [3] CPU_BSEL0
R59 0_4 CLK_BSEL0
MCH_BSEL0 [6]
10K_4
3 1 CGCLK_SMB
[13,16,19,23,24] SCLK
FSC FSB FSA Frequency
+1.05V R66 *56_4
0 0 0 266Mhz
FSA
R65 *1K_4
0 0 1 133Mhz
+3V
0 1 1 166Mhz
R80 0_4 CLK_BSEL1
[3] CPU_BSEL1 MCH_BSEL1 [6]
0 1 0 200Mhz R411 10K_4 NEW_CLKREQ#_R
R77 *0_4
A
1 1 0 400Mhz
A1A: (9/20) Remove 0ohm FSB A
+1.05V R408 *1K_4
1 1 1 Reserved
1 0 1 100Mhz R55 0_4 CLK_BSEL2
[3] CPU_BSEL2 MCH_BSEL2 [6]
R62 *0_4
Quanta Computer Inc.
1 0 0 333Mhz
FSC PROJECT : BU1 Santa Rosa
+1.05V R56 *1K_4 Size Document Number Rev
CLK. GEN./ CK505 1A
Date: Monday, March 26, 2007 Sheet 2 of 33
5 4 3 2 1
5 4 3 2 1
www.bufanxiu.com
CPU Thermal monitor
U24A
[5] H_A#[16:3]
H_A#3 J4 H1
A[3]# ADS# H_ADS# [5]
CPU(HOST)
H_A#4
ADDR GROUP 0
L5 A[4]# BNR# E2 H_BNR# [5]
H_A#5 L4 G5 +3V
A[5]# BPRI# H_BPRI# [5]
H_A#6 K5
H_A#7 A[6]#
M3 A[7]# DEFER# H5 H_DEFER# [5]
H_A#8 N2 F21
A[8]# DRDY# H_DRDY# [5]
H_A#9 J1 E1
A[9]# DBSY# H_DBSY# [5]
H_A#10 N3
H_A#11 A[10]#
P5 A[11]# BR0# F1 H_BREQ#0 [5]
H_A#12 P2 A[12]#
CONTROL
H_A#13 L2 D20 H_IERR# R16 56.2_4 +1.05V
H_A#14 A[13]# IERR# +3V R431 R432 R437
P4 A[14]# INIT# B3 H_INIT# [14]
H_A#15 P1
H_A#16 A[15]# Q33 10K_4 10K_4 200_6
R1 A[16]# LOCK# H4 H_LOCK# [5]
2
D RHU002N06 LM86VCC D
[5] H_ADSTB0# M1 ADSTB[0]#
[5] H_REQ#[4:0] RESET# C1 H_CPURST# [5]
H_REQ#0 K3 F3 [18,26,27] MBCLK 3 1 C455
REQ[0]# RS[0]# H_RS#0 [5]
H_REQ#1 H2 F4
REQ[1]# RS[1]# H_RS#1 [5]
H_REQ#2 K2 G3 .1U_4
H_REQ#3 J3
REQ[2]# RS[2]#
G2
H_RS#2 [5]
+3V
H=1.75mm
REQ[3]# TRDY# H_TRDY# [5]
H_REQ#4 L1 U23
REQ[4]# Q34 H_THERMDA
[5] H_A#[35:17] HIT# G6 H_HIT# [5]
2
H_A#17 Y2 E4 RHU002N06 8 1
A[17]# HITM# H_HITM# [5] SCLK VCC
H_A#18 U5
H_A#19 A[18]# C454
R3 A[19]# BPM[0]# AD4 [18,26,27] MBDATA 3 1 7 SDA DXP 2
H_A#20
ADDR GROUP 1
W6 A[20]# BPM[1]# AD3
H_A#21 U4 AD1 6 3 2200P_4
XDP/ITP SIGNALS
H_A#22 A[21]# BPM[2]# ALERT# DXN
Y5 A[22]# BPM[3]# AC4
H_A#23 U1 AC2 *10K_4 4 5 H_THERMDC
H_A#24 A[23]# PRDY# R434