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XEROX
Office Products Division
Office Systems Business Unit
To: Ed Miller Date: June 18, 1981
From: Roy Ogus Org: SDD/SD&T Workstation Design
Subject: Opportunities for Dandelion Cost Reduction
Filed: [lris]
Introduction
This memo explores some of the opportunities that exist for reducing the manufacturing cost of the
current Dandelion pTcx:essor. All the changes discussed nere relate only to the DandelirJD
electronics; cost reductions through reducing the cost of the housing, cables, peripherals, and power
supply, are not covered in this memo.
A significant reduction in cost will occur if an entire logic module can be dispensed with in the
system. The removal of a gate here and a flip-flop there is usually not meaningful unless the sum
of these small logic savings add up such that an entire function can be moved from one module to
another, potentially eliminating the module.
The changes discussed below are divided into two broad categories, viz. straightforward changes, i.e.
those that can be made without a large redevelopment effort, and longer term changes, i.e. those
that require a substantial development or tools effort, or are dependant on components not yet
available.
Straightforward Cost Reduction Opportunities
Straightforward opportunities for cost reduction in the Dandelion will be available either when more
highly integrated memory components become available at a competitive price, or when some of the
optional functions are removed from the systems. This sections explores these possibilities.
Memory system
a) 64K Dynamic RAMs
The first p'otential cost reduction technique is to convert the main memory RAM component from
the current 16K dynamic RAM to the 64K dynamic RAM. When this occurs, there is the
possibility of implementing up to 256K words on the Memory Controller, thus dispensing with the
Storage module on systems which do not require more than 256K words. (It is expected than the
8000 processors will not need more than this for some time.) Even though an entire module can be
removed from the system, the system savings still depends on the cost of the 64K RAM chip. At
current prices, it is still more expensive to implement the memory system with 64K chips rather
than 16K chips. The point at which there is a cost benefit by using 64K chips can be computed as
follows.
Opportunities for Dandelion Cost Reduction' 2
Let C16 and CM be the cost of 16K and 64K chips respectively. The materials cost of the
Dandelion memory modules can be expressed by
Cost (PWB) + Cost (Burn In) + Cost (RAM parts) + Cost (other parts)
Cost(PWB} + Cost(Burn In} + Cxx*Nxx + Cost(otherparts}, (1)
where "xx" is either "16" or "64", and N xx is the number of type "xx" RAM chips used. [Source:
OSBU Program Management Book (OSBU-PMB), section on Manufacturing and Distribution. Note
that Labor and Overhead costs are not included.]
Let MCC-16 and MSC-16 denote the 16K-based Memory controller and Storage modules
respectively. Let Cost (16) denote the cost of the 16K-based memory system containing 192K
words.
Thus, from (1) and OSBU-PMB (using the base costs),
Cost(MCC-16} = $94 + $6 + $91 + 88*C16
= $191 + 88*C16
and,
Cost(MSC-16} = $72 + $2 + $46 + 176*C16
= $120 + 176*C16
Thus, from (1)
Cost(16} = Cost(MCC-16} + Cost(MSC-16}
= 311 + 264*C16 (2)
A 64K-based memory controller, MCC-64, containing 192K words, will have a cost, from (1) and
OSBU-PMB (using the base costs), of
Cost(64} = Cost(MCC-64}
= $94 + $6 + $91 + 66*C64
= $191 + 66*C64 (3)
The use of 64K memory chips becomes more economical when the price of the 64K chips drops
relative to the 16K devices such that the cost of the memory sytem implemented by 64K devices is
less than the cost of the system implemented by 64K devices. Thus, using (2) and (3),
Cost(64} < Cost(16}
$191 + 66*C64 < 311 + 264*C16
C64 < 1.82 + 4*C16 (4)
The following table indicates the relative costs of the 64K and 16K devices such that the 64K-based
memory system containing 192K words becomes cheaper than the 16K-based implementation:
16K cost (Cl~ [$] 64K cost (C~ [$]
1 5.82
2 9.82
3 13.82
4 17.82
OpporturUtiesjor Dandelion Cost Reduction
Thus, for example, if the cost of a 16K chip is $2, then the 64K chip must cost $9.82 or less for the
64K-based implementation to be cheaper.
Actually, the costs not considered here, viz. the labor and overhead costs, will change the values in the table above. For
example, the OSBU-PMB specifies base costs of the 16K and 64K chips as $2.87 and $14.00, respectively. According to
the table above, for a 16K cost of $2.87, the break-even 64K price is $13.35, indicating that, considering materials costs
alone, the 64K is still not economical. However, it is shown that when labor and overhead costs are included, the 64K-
based implementation will be less costly.
To get an idea of the amount of UMC reduction possible, we can consider the difference in
memory costs. From (2) and (3) the difference,
Cost(J6) - Cost(64) = 120 + 264*C16 - 66*C64 (5)
As~ume the cost of the 16K device is $2.87. If the cost of the 64K device is $13.35 then from (5)
the memory system will cost the same. If the price of the 64K chip goes down to $10, then the
64K-based system will cost $218 less.
b) Removal of E"or Correction Logic
Another method to redu<.e the memory system cost is to remove the eaor-correction logic. The
simple parity checking would remain, so that all single errors would be trapped. Note that this cost
reduction method should only be considered when more data is available on the memory system
error characteristics, indicating a low enough probability of single errors. Only the case using the
64K memory devices is considered here.
Removing the error correction logic from the memory system will discard 5 memory chips per
memory bank. In addition, 9 other miscellaneous chips can be dispensed with in the memory
system. Thus, for the 192K memory implemented in 64K chips (three banks), the cost savings will
be
9 +15*C64 (5)
For $10 64K chips the savings will be $159, while $8 64K chips will save $129.
Central Processor
The RAM-implemented control store (48 chips) comprises 30% of the total number of CP integrated
circuits. The control store is 4K x 48 implemented using forty-eight 2147L 4Kx1 RAM chips.
Possible ways to reduce the control store cost are through the use of higher density RAMs or
through conversion to Prom which can be found in more dense packages.
a) Higher density RAMs
The current control store RAMs are 4K bit RAM chips (2147L), requiring 48 chips to implement
the array. 16K bit RAM chips exist which are configured as 4K x 4 bits. The use of the 2168
chips would cut down the number of chips by a factor of 4. If the cost of the 2168 chips is less than
four times the cost of the 2147 chips then this change would be cost-efective. Current costs of the
2147 and 2168 chips are approximately $5.25 and $30, respectively, however the cost of the 2168
parts is expected to drop below $20 in 1982.
Opportunities for Dandelion Cost Reduction
This change has no system implications 8l}d could be easily incorporated into the CP design.
However, the tasks of qualification of the 2168 parts, and the determination of second sources for
the parts, would have to be carried out
b)1 Prom Control Store
Another potential cost savings could be gained if the control store would be implemented in Prom
instead of the less-dense RAM. 4Kx4 and 4Kx8 proms will be available from Monolithic
Memories, Inc. (part numers 63RA1641 and 63RA1681) within about a year, which would cut down
the number of components from 48 to 12 or 6 components respectively. The acual cost savings (if
any) would have to be computed using the relative costs of the Prom and RAM chips (the Prom
prices are not yet available).
It should be pointed out, however, that converting to Prom control store in the CP will incur other
additional costs, as well as having a large impact on the system microcode and lOP software. Each
Prom would be a distinct part which has to be produced and inventoried, adding to the number of
different components in the system. If the part is not qualified (as will almost certainly be the
case), a qualification program would have to be carried out with its attendant costs.
The microcode could not be changed dynamically, precluding the use of the same Dandelion for
more than one configuration (e.g. as a Workstation or a Raven Printer Server), unless the microcode
for all the configurations could be stored together in the control store. Currently this is not possible
due to lack of space.
Subsequent changes to the microcode would be tedious and costly to implement since this would
involve retrofitting substantial numbers of machines in the field.
In addition, there are large system implications. The booting process utilizes the writeability in
several ways. Initial diagnostics are loaded into the control store and executed, and device and
system initialization procedures are executed before the standard microcode is loaded. The standard
microcode is close to filling the control store. There are also stand alone diagnostics which utilize
writeable control store.
If the control store is changed from RAM to Prom, then these functions can only be executed from
microcode which is always present within the control store. The 4K control store size prohibits
these functions from being accomplished in the Prom Dandelion in their current form. There are
two possible options. One is to have the Prom Dandelion contain more than 4K of control store.
The second is to develop diagnostic and initialization strategies which would use an absolute
minimum of control store space. It is probable that 4K is still not large enough. Consideration of
the diagnostic strategy changes will require discussions with people from the diagnostic area, and
probably people from manufacturing because of the new limitations during assembly and test
, Changing the booting strategy would involve large changes to the microcode, as well as to the boot
code (microcode and lOP software), including the EProm code.
c) CMOS Control Store RAMs
Another type of cost reduction is to reduce life cycle costs by reducing the amount off power
consumed by the system. This will improve reliability and result in cost savings through a lowered
failure rate of the system. In addition. this will alleviate the current burden on the power supply.
It is known that the use of 64K memory components (especially when the 64K-based MSC is
implemented) will impose a large burden on the + 5V power supply, perhaps even exceeding the
designed output in some cases (e.g. using a highly populated XMSC module).
Opportunities for Dandelion Cost Reduction 5
One way to reduce the + SV current signific~ly is to use CMOS control store RAM components.
Hitachi makes a CMOS RAM component, the HM6147, which is pin-for-pin compatible with the
2147L 4Kx1 RAM currently used in the control store. The 2147L implemented control store uses
6.72 amps from the +SV power supply, and dissipates 36 watts of power. The comparable numbers
for the HM6147 are 0.72 amps and 3.6 watts, an order of magnitude reduction.
The HM6147 CMOS RAM is currently a single-sourced component, but there are plans for
Motorola (and perhaps Intel) to second source the component. The component would also have to
be qualified before if can be considered a viable replacement for the 2147.
Options Module
Raven and RS232C controller
Other savings can be realized if certain optional functions are removed from the system. The cost
saving would of course only be applicable in configurations not requiring the particular function.
Two such optional functions are the Raven controller and the RS232C/RS366 controller. Removing
the Raven control would save about 20 equivalent chips. The corresponding chip savings for the
Rf>232C/RS306 controller is about 30 equlvalent chips. The cost savings would be more than a $l-
a-chip since there are several LSI components in the two controllers. The Raven controller would
save approximately $30, while the RS232C controller could save about $60.
lOP Module
Removal of Floppy Disk Controller
A savings of about 28 equivalent chips (approximitely $40) can be achieved if the floppy disk
controller is removed from the lOP. There would be an additional savings of about $300 for the
removal of the drive. This change can probably only be contemplated for a workstation machine,
which has Etherbooting implemented.
There are other implications in removing the floppy disk. The diagnostics are run from the floppy
disk, and cases where the CP does not function, the machine can still be diagnosed from the lOP.
This would not be possible if there was no floppy disk, since the diagnostics would have to be
fetched from the Ethernet, requiring the CP to be functional. In addition, software distribution is
. currently achieved using floppy disks. This would have to be redesigned to allow distribution over
the Ethernet Initialization of a server machine on a newtwork with no other servers can, of course,
not do without the floppy disk
Conve.rsion to CMOS Time-of Day circuit in Maintenance Panel
The original Time-of-Day (TOO) circuit which was designed for the Dandelion was implemented in
CMOS logic, stored entirely on the Maintenance Panel module. On recommendation of the
ED/Parts group this design was abandoned in favor of a completely TTL design. This had the
effect of requiring additional space on the lOP module to house the most of the TOD circuitry. If
the original TOO circuit was re-used, then 12 chips on the lOP could be dispensed with. There still
might have to be qualification activity on some of the parts. This savings is small, and also does
not free up enough room on the lOP to allow moving any other function. This change is
documented here for the record.
Opportunities for Dandelion Cost Reduction' 6
Conclusions
This section summarizes the potential savings described above. Note that some of the techniques
have little or no effect on the system operation, while others have a large impact This impact
should first be evaluated before considering using the cost-reduction technique.
64K Dynamic RAMs. This technique is clearly one that should be implemented. The economics
are such that the 64K-based system is on the verge of being (or is already) cost-effective.
Considerations still to be resolved are the availability of 64K parts, and the qualification of
suitable vendors for supply.
Removal of Error Correction Logic. More data on and analysis of 64K memory failure rates in the
system is needed before this technique should be considered.
Higher density RAM Control Store. This change is attractive since it frees up 36 chip locations on
the CP card, an is a relatively simple change to implement. However, there is still some risk
in that the 2168 parts are still not available in production quantities. It is expected that this
will not be a problem in 1982.
Prom Control Slore. This change should be considered with great caution. The appropriate Prom
chips are not yet available, and thus not qualified or second-sourced. It is not clear yet
whether Prom usage will result in a cost savings (or at least initially). But most importantly,
this change has a large impact on the system operation. The ramifications of a Prom control
store on booting, diagnostics operation, and handling of system changes, should be studied
carefully before deciding to implement the change.
CMOS Control Store RAMs. It is difficult to put a value on the cost savings of this change, since
the savings will be in life-cycle costs due to increased reliability (hopefully). Other benefits
of this change are to reduce the load on the + SV power supply, thus increasing the overload
margin when the 64K-based memory is used.
Removal of Raven and/or RS232C Controller. This savings can only be realized in machines that
can dispense with these functions. Other benefits will occur if other savings together with
these result in the entire Options card being able to be dispensed with.
Removal of Floppy Disk Controller. This savings can be achieved in machines that do not need the
floppy disk. This will depend on Etherbooting being implemented, and the corresponding
software changes to initialize the rigid disk from the Ethernet There are also Field
implications, in that diagnostics, and distribution of software will have to be redesigned.
CMOS Time-of Day circuit. A relatively small savings is achieved using this technique. It might
have the added benefit of isolating the TOD from the system in a better manner than is now
done, perhaps reducing the interference problems in the TOD circuitry.
Thus, the recommended cost reductions are the use of 64K memory chips, and the 4Kx4 control
store chips. In addition, the Raven and RS232C controllers may be dispensed with in certain
configurations.
A significant savings will be achieved if the Dandelion can be reduced to a 4-board machine
(Memory Control, CP, lOP, and HSIO). Implementing the 64K-based memory system, using the
4Kx4 control store chips, and removing the RS232C and Raven controllers, still does not allow the
Options card to be removed since the Ethernet controller (almost 100 equivalent chips currently) has
to placed on the other boards, which do not obviously have the space. More work needs to be done
to determine how to remove the fifth board (if that is possible).
Opportunities for Dandelion Cost Reduction 7
Longer Term Cost Reduction Opportunities
The changes described in this section are those which are not immediately feasible. This may be
due to a substantial development effort being required, together with the implementation of new
design tools. Alternatively, the change may be dependent on usage of vendor components which
are not yet available.
a) Ethernet controller
Intel and other vendors are currently developing LSI components specially designed to implement
Ethernet controllers for LSI microprocessor systems. These compQnents are more than 18 months
from being in production.
It is not apparent to me that the Intel Ethernet controller chip (82D2-E) would allow any cost
reduction in the Dandelion Ethernet controller. It is speciafically designed to interface to an 8086-
like bus structure which is not compatible with the Dandelion I/O controller bus structure. A
reasonable amount of logic would have to be implemented to convert between the two bus
structure, and this could offset any potential savings through the use of the LSI controller. The
82D2-E interfaces to the processor through memory, and thus a two-ported memory system would
have to be aoded to the controller for communications to thl': CPo
The Intel Ethernet Serial Interface (ESI) chip, however, applears to fit in more easily with the
current controller structure. The ESI integrates the front-end controller functions such as
transceiver interfacing, and data stream encoding and decoding (phase-lock loop). Using the ESI
chip could save approxiately 14 chips and about 60 discretes in the Ethernet controller.
b) Gate Array usage
This section takes a first look at the potential for implementing parts of the Dandelion CP module
using gate-array techniques. The available Texas Instruments gate array components were used as
the basis the study.
Assuming that as much of the CP was converted to gate array implementation, then the Dandelion
CP could be implemented with the following components:
? Control-Store chips (depends on whether RAM or Prom)
7 Gate Array Chips
11 RAM Memory Chips (4-256x4, 7-16x4)
4 2901 ALU Chips
15 MSI Chips
In some cases, it may not make sense to implement the section of random logic in gate arrays, since
it still may be cheaper to implement the random logic. However, this analysis serves to illustrate
the largest savings in chips that would be possible.
The details of the gate array chips are as follows:
LRot-StkP-IB-NibByte
replaces 29 Ie's
contains 1000 gates
has 67 I/O signals
Opportunities for Dandelion Cost Reduction 8
NIAD.. 7
replaces 7+ IC's
contains 294 gates
has 64 110 signals
NI,AB.. l1
replaces 9+ IC's
contains 192 gates
has 66 1/0 signals
FDecodes
replaces 7+ Ie's
contains 160 gates
has 64 1/0 signals
Erro,. Kern-Task
replaces 9+ Ie's
contains 337 gates
has 71 110 signals
Carry-Shift-DispBr
replaces 7+ IC's
contains 156 gates
has S2 110 signals
Clock-Ma,.Misc
replaces 9+ Ie's
contains 189 gates
has 67 1/0 signals
Appendix A contains the full details of what logic in the CP is replaced by the various gate array
chips
Opportunities for Dandelion Cost. Reduction 9
Appendix A: Gate Array Component Details
Following are the details of the gate arrays referenced in the memo. The numbers in braces
indicate the number of gate array gates required for each chip which is replaced. The TI gate
arrays were used as basis of this study. The information on the gate array implementations was
provided by Don Charnley.
LRot-StkP-IB-NibByte
8257 {64}
2S809 {45}
LS283 {60}
25809 {45}
8240 {9}
8373 {8I}
8373 {8I}
8374 {65}
8260(1/2) {7}
L8374 (2/4) {33}
F934S3 {20}
F93453 {20}
2S810 {40}
25810 {40}
2S810 {40}
25810 {40}
S241 {16}
S257 {64}
S257 {64}
S257 {64}
8241(4/8) {8}
8241 (4/8) {8}
8138 [3/8] {IO}
8138[1/8] {4}
S138 [2/8] {7}
S138[5/8] {16}
800 (1/4) {I}
SOO (1/4) {I}
820 (112) {I}
820 (112) {I}
F93453 (1/4) {10}
810 (1/3) {I}
800 (1/4) {I}
SlO (1/3) {I}
800 (1/4) {I}
8138 [3/8] {IO}
8374 [4/8] {33}
LS32 (1/4) {3}
S02 (1/4) {3}
Inputs:
X.O.XIS
Y:O ..Y.IS
1S.0.. 1S.3
IX.O.. IXJ
fY.O .. fYJ
pfZ.O..pfZJ
pfS.2, pSE, AlwaysClk, WaitClk, ppCLK
Wait, AllowMDR", MesaInt
Opportunities for Dandelion Cost Reduction 10
Outputs:
IB.0..IB.7
IBEmptyErr. EKErr.O'. EKErr.l'
NIA 0