Text preview for : ASUS 900pv PINEVIEW. Schematic diagram. REV 1.0G.pdf part of asus ASUS 900pv PINEVIEW. Schematic diagram. REV 1.0G asus ASUS 900pv PINEVIEW. Schematic diagram. REV 1.0G.pdf
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5 4 3 2 1
CLOCK GEN
IDT427
D D
LCD Board
PINEVIEW
LCD LVDS 2 TTL SODIMM*2, 200P
CRT
C C
LINE OUT
Debug Conn Speaker
AZALIA CODEC
SOUTH Realtek ALC269
EXT MIC
EC BRIDGE
ENE KBC3310
INT MIC
TIGERPOINT
SPI ROM Internal KB Touch Pad
B B
USB Port x3
MINICARD WLAN
SD/MMC Card Reader
Card au6336 LAN Atheros
AR8132 RJ-45
Reader
Camera
MINIPCIE 3G
CONN CARD
SATA HDD SATA
A A
Conn
BLUETOOTH
Title : Cover Page
ASUSTek Computer Inc. Engineer: Henry_Yang
Size Project Name Rev
A3 PINEVIEW 1.0G
Date: Wednesday, January 14, 2009 Sheet 1 of 42
5 4 3 2 1
5 4 3 2 1
5 4 3 2 1
ICH7M GPIO DEFAULT&NOW
SETTING
Pin Pin Name Type Tolerance Powe Well Default Now Setting Pin Pin Name Type Tolerance Powe Well Default Now Setting
AB18 GPIO0/BM_BUSY# I/O 3.3V CORE GPI BM_BUSY# A21 GPIO26 I/O 3.3V Resume GPO GPO,VCORE_DOWN
C8 GPIO1/REQ5# I/O 5V CORE GPI REQ5# B21 GPIO27 I/O 3.3V Resume GPO GPO,CARD_READER_EN#
D D
G8 GPIO2/PIRQE# I/OD 5V CORE GPI PIRQE# E23 GPIO28 I/O 3.3V Resume GPO GPO,MODEM_EN#
F7 GPIO3/PIRQF# I/OD 5V CORE GPI PIRQF# C3 GPIO29/OC5# I/O 3.3V Resume Native OC5#
F8 GPIO4/PIRQG# I/OD 5V CORE GPI PIRQG# A2 GPIO30/OC6# I/O 3.3V Resume Native OC6#
G7 GPIO5/PIRQH# I/OD 5V CORE GPI PIRQH# B3 GPI031/OC7# I/O 3.3V Resume Native OC7#
AC21 GPIO6 I/O 3.3V CORE GPI GPI,No Function,10K Pull +3VS AG18 GPIO32/CLKRUN# I/O 3.3V CORE GPO CLKRUN#
AC18 GPIO7 I/O 3.3V CORE GPI GPO,WLAN_LED AC19 GPIO33/AZ_DOCK_EN# I/O 3.3V CORE GPO GPO,No Function,NC
E21 GPIO8 I/O 3.3V Resume GPI GPI,EXTSMI# U2 GPIO34/AZ_DOCK_RST# I/O 3.3V CORE GPO GPO,No Function,NC
E20 GPIO9 I/O 3.3V Resume GPI GPI,No Function,10K Pull +3VS AD21 GPIO35 I/O 3.3V CORE GPO GPO,CAMERA_EN
A20 GPIO10 I/O 3.3V Resume GPI GPO,WLAN_ON# AH19 GPIO36/SATA2GP I/O 3.3V CORE GPI GPI,No Function,10K Pull +3VS
B23 GPIO11/SMBALERT# I/O 3.3V Resume Native SMBALERT# AE19 GPIO37/SATA3GP I/O 3.3V CORE GPI GPI,PCB_ID0
F19 GPIO12 I/O 3.3V Resume GPI GPI,KBC_SCI# AE20 GPIO38 I/O 3.3V CORE GPI GPI,PCB_ID1
E19 GPIO13 I/O 3.3V Resume GPI GPO,VCCP_DOWN AD20 GPIO39 I/O 3.3V CORE GPI GPI,PCB_ID2
R4 GPIO14 I/O 3.3V Resume GPI GPO,1.5VS_DOWN NA GPIO40 NA NA NA NA NA
E22 GPIO15 I/O 3.3V Resume GPI GPI,No Function,10K Pull +3VSUS NA GPIO41 NA NA NA NA NA
C C
AC22 GPIO16/DPRSLVR I/O 3.3V CORE Native DPRSLVR NA GPIO42 NA NA NA NA NA
D8 GPIO17/GNT5# I/O 3.3V CORE GPO BIOS_SEL1 NA GPIO43 NA NA NA NA NA
AC20 GPIO18/STPPCI# I/O 3.3V CORE GPO STP_PCI# NA GPIO44 NA NA NA NA NA
AH18 GPIO19/SATA1GP I/O 3.3V CORE GPI GPI,No Function,10K Pull +3VS NA GPIO45 NA NA NA NA NA
AF21 GPIO20/STPCPU# I/O 3.3V CORE GPO STP_CPU# NA GPIO46 NA NA NA NA NA
AF19 GPIO21/SATA0GP I/O 3.3V CORE GPI GPI,No Function,10K Pull +3VS NA GPIO47 NA NA NA NA NA
A13 GPIO22/REQ4# I/O 3.3V CORE Native REQ4# A14 GPIO48/GNT4# I/O 3.3V CORE Native BIOS_SEL0
AA5 GPIO23/LDRQ1# I/O 3.3V CORE Native LDRQ1# AG24 GPIO49/CPUPWRGD I/O V_CPU_IO V_CPU_IO Native CPUPWRGD
R3 GPIO24 I/O 3.3V Resume GPO GPO,MINICARD1_EN#
D20 GPIO25 I/O 3.3V Resume GPO GPO,DUAL_DOWN
B B
A A
Title : System setting
ASUSTek Computer Inc. Engineer: Henry_Yang
Size Project Name Rev
A3 PINEVIEW 1.0G
Date: Wednesday, January 14, 2009 Sheet 2 of 42
5 4 3 2 1
0.1 A Beta
5 4 3 2 1
5 4 3 2 1
AC_BAT_SYS +VCCP 16
CPU_VRON UP6111ADD VCCP_PWRGD
15 16
A2
3
A/D_DOCK_IN +5VSUS
AC_BAT_SYS +3VSUS +5VS 13 +3V_LCD 14
D Adapter SUSB_ON AP4800 ASM1117 D
VSUS_ON RT8205CGQW +5VSUS A6
MB39A132 12
B2 A5 +3VA
4
BAT +3VSUS
VSUS_GD +3VS 13
Battery A7 SUSB_ON AP4800
12
21 FLASH CARD
Signal S0/S1 S3 S4/S5 Power S_PCIRST#
VSUS_ON H H Adapter H SB EC
AC_BAT_SYS
3
Battery L 13 14
SUSC_ON +1.8V 21 PLT_RST# AR8132
SUSB_ON H L L Main UP6111AQDD +VTT_DDR
BAT_IN
12 +5VS RT9173CPSP
AC_OK
SUSC_ON H H L DUAL WLAN
+1.8V 14 XDP
+1.5VS
SUSB_ON APL5912KA TPT LANRST#
BUFFER
C
+3VA SUSC_ON 12 14 PINEVIEW RSTIN# C
+1.8V
ENE KB3310 SUSB_ON 12 +1.2VS
+5VS RT9173CPSP
A5 VSUS_ON CPU_VRON 15 AC_BAT_SYS
+0.89VS
55ms VCCP_PWRGD SYS_RESET# TPT SYS_RESET#
A7 VSUS_GD VCOREPWRGD 18 UP6111AQDD 17 17 RSTBTN
16 +1.8V
10ms +1.8VS CLK Gen
VCCP_PWRGD RT9173CPSP
A9 O_PWR_SW# PM_PWROK 19 0.89VS_PWRGD 16
17 Or SUSB_ON RESET MAP
A10 +3VS
A8 S_PCIRST# 21 +1.8VS
PM_RSMRST#
PM_SUSB#
PM_SUSC#
C_PCI_EC 19 20 H_PWRGD
+1.8V
PM_PWRBTN#
Battery Mode AC_BAT_SYS
B10-->B11 +VCORE +0.89VS
250ms
17 0.89VS_PWRGD
RT8152 18 +1.5VS
Or C_FSB_NB 18
1 11 11 :CPU_VRON VCOREPWRGD +VCCP
PINEVIEW C_PCIE_NB 18
+VCC_RTC PM_PWROK 19 18 +1.2VS
+ C_96M_NB 18
BATT VCOREPWRGD CLK_EN#
B
+5VSUS 18 PM_PWROK C_LCD_LVDS B
18
+3VSUS S_PCIRST# 18
21 19
+1.5VS PLT_RST# 21 PLT_RST# D2_CLK
(internal) CPURST#
21 22 SODIMM
+5VS Intel TIGERPOINT
C_PCIE_SB 19
+3VS
+VCCP C_48M_USB 19 +3VS Onboard S_PCIRST# 21
+3VSUS Flash
C_PCI_SB 19 FSB CLK 100M
C_REF_SB 19 CLK_EN# CPU MCH ITP 19
CLK_EN
18
H_PWRGD 20 REF CLK 14M +3VS Flash S_PCIRST# 21
ICH Module
19 PCIE CLK 100M
USB CLK 48M MCH ICH
+3VSUS MINICARD 19
ICH
C_PCIE_WIFI 18 19 IDT427 LAN
+3VS
A A
+1.5VS MINICARD PLT_RST# 21 PCI CLK 33M
19 ICH EC LVDS CLK 100M
DEBUG 19
MCH
Title : Sequence
C_PCIE_L2 18
+3VSUS
AR8132 PLT_RST# 21 19 ASUSTek Computer Inc. Engineer: Henry_Yang
SATA CLK 100M UMA CLK 96M 19 Size Project Name Rev
ICH MCH A3 PINEVIEW 1.0G
Date: Wednesday, January 14, 2009 Sheet 3 of 42
5 4 3 2 1
5 4 3 2 1
5 4 3 2 1
USB0 USB CONN
+3VS 1 2 PIRQE#
(16) FALLINT1
0Ohm TPR9 USB1 USB CONN
/GSENSOR
7 8 TPRN1D REQ1# 1 2 PIRQF#
8.2KOHM (16) FALLINT2
1 2 TPRN1A REQ2# USB2 USB CONN
8.2KOHM
5 6 TPRN1C RSVD3 0Ohm TPR11
8.2KOHM
7 8 TPRN6D RSVD2 /GSENSOR
8.2KOHM
USB3 USB CONN
5 6 TPRN4C FRAME# G sensor
8.2KOHM
D 7 8 TPRN4D DEVSEL# USB4 Camera D
8.2KOHM
3 4 TPRN5B IRDY#
8.2KOHM
1 2 TPRN3A SERR#
8.2KOHM
USB5 Card Reader
3 4 TPRN1B STOP#
8.2KOHM
7 8 TPRN3D PLOCK#
8.2KOHM
5 6 TPRN3C TRDY# USB6 Blue tooth
8.2KOHM
3 4 TPRN3B PERR#
8.2KOHM
+3VS USB7 3G
1 2 TPRN6A PIRQA#
8.2KOHM
1 2 TPRN5A PIRQB#
8.2KOHM
7 8 TPRN5D PIRQC#
8.2KOHM
3 4 TPRN4B PIRQD# TPC9
8.2KOHM
3 4 TPRN6B PIRQE# C_PCIE_SB# 2 1 10PF/50V
8.2KOHM
5 6 TPRN5C PIRQF# /X Near Tigerpoint.
8.2KOHM SU1B
1 2 TPRN4A PIRQG# TPC10
8.2KOHM
5 6 TPRN6C PIRQH# C_PCIE_SB 2 1 10PF/50V 1 1
8.2KOHM
/X DMITP2 DMITP1 R23 H7
(7) DMI_RXN0 DMI0RXN USBP0N U_USB1- (21)
+3VSUS 0.1UF/10V R24 H6
(7) DMI_RXP0 DMI_TXN0_R DMI0RXP USBP0P U_USB1+ (21)
TPC5 1 2 P21 H3
(7) DMI_TXN0 DMI_TXP0_R DMI0TXN USBP1N U_USB2- (21)
2 1 PME# GND TPC3 1 2 P20 H2
(7) DMI_TXP0 DMI0TXP USBP1P U_USB2+ (21)
(7) DMI_RXN1 T21 DMI1RXN USBP2N J2 U_USB3- (21)
TPR75 10KOhm N/A 0.1UF/10V 0.1UF/10V T20 J3
(7) DMI_RXP1 DMI1RXP USBP2P U_USB3+ (21)
TPC7 1 2 DMI_TXN1_R T24 K6
(7) DMI_TXN1 DMI_TXP1_R DMI1TXN USBP3N U_USB4- (21)
TPC6 1 2 T25 K5
(7) DMI_TXP1 DMI1TXP USBP3P U_USB4+ (21)
1 T19 DMI2RXN USBP4N K1 U_CAM- (20)
Remain 0.1UF/10V TPT57 1 T18 K2
SU1A DMI2RXP USBP4P U_CAM+ (20)
1 TPT58 1 U23 L2
PCICLK DMI2TXN USBP5N U_CARD- (19)
C DMITP3 1 TPT59 1 U24 L3 C
DMI2TXP USBP5P U_CARD+ (19)
. 1 A5 B22 DMITP4 TPT60 1 V21 M6
PAR AD0 DMI3RXN USBP6N U_BT- (15)
TPT55 DEVSEL# B15 D18 TPT61 1 V20 M5
DEVSEL# AD1 DMI3RXP USBP6P U_BT+ (15)
J12 C17 TPT62 1 V24 N1
(12) C_PCI_SB PCICLK AD2 DMI3TXN USBP7N U_3G- (15)
A23 C18 TPT63 1 V23 N2
(26) S_PCIRST# PCIRST# AD3 DMI3TXP USBP7P U_3G+ (15)
IRDY# B7 B17 TPT64
PME# IRDY# AD4 If disable Port0,all PCIE port will be disable.
C22 PME# AD5 C19
SERR# B11 B18 D4
SERR# AD6 OC0# U_USBOC#1 (21)
STOP# F14 B19 K21 C5 +3VSUS
STOP# AD7 (41) X_L1X1_RXN PERN1 OC1# U_USBOC#23 (21)
PLOCK# A8 D16 0.1UF/10V K22 D3
PLOCK# AD8 (41) X_L1X1_RXP PERP1 OC2#
TRDY# A10 TRDY# AD9 D15 (41) X_L1X1_TXN
0.1UF/10V TPC501 2 L1_TXN_R J23 PETN1 OC3# D2 OC3 2 10KOhm 1 TPR4
PERR# D10 A13 TPC511 2 L1_TXP_R J24 E5 OC4 5 TPRN2C
PERR# AD10 (41) X_L1X1_TXP PETP1 OC4# OC5 10KOhm6
FRAME# A16 E14 M18 E6 7 TPRN2D
FRAME# AD11 (22) X_L2X1_RXN PERN2 OC5#/GPIO29 OC6 10KOhm8
H14 0.1UF/10V M19 C2 1 TPRN2A
AD12 (22) X_L2X1_RXP PERP2 OC6#/GPIO30 10KOhm2
AD13 L14 (22) X_L2X1_TXN
TPC2 1 2 L2_TXN_R K24 PETN2 OC7#/GPIO31 C3 OC7 3 10KOhm4
TPRN2B
TPT67 TPC4 1 0.1UF/10V L2_TXP_R K25
AD14 J14 (22) X_L2X1_TXP 2 PETP2
1 A18 GNT1# AD15 E10 (17) X_LANRXN L23 PERN3
E16 C11 0.1UF/10V L24
(42) GNT2# GNT2# AD16 (17) X_LANRXP PERP3
AD17 E12 (17) X_LANTXN
0.1UF/10V TPC1 1 2 LAN_TXN_RL22 PETN3
REQ1# TPC8 1 LAN_TXP_R USBRBIAS TPR2
G16 REQ1# AD18 B9 (17) X_LANTXP 2 M21 PETP3 USBRBIAS G2
REQ2# A20 B13 P17 G3 2 1
REQ2# AD19 (15) X_3GX1_RXN PERN4 USBRBIAS#
L12 0.1UF/16V P18
AD20 (15) X_3GX1_RXP PERP4
AD21 B8 (15) X_3GX1_TXN
0.1UF/16V TPC482 1 3G_TXN_RN25 PETN4
22.6Ohm
G14 A3 TPC492 1 3G_TXP_R N24 GND
(42) BOOTSEL1 GPIO48/STRAP1# AD22 (15) X_3GX1_TXP PETP4
(42) BOOTSEL2 A2 STRAP2#/GPIO17 AD23 B5 CLK48 F4 C_48M_USB (12)
(18,41) MINICARD2_EN# C15 GPIO22 AD24 A6 Place
(15,18) 3GLAN_OFF C9 GPIO1 AD25 G12
AD26 H12 near
C8 +VCCDMI_PLL_ICH
B AD27
D9
TPT B
PIRQA# B2 AD28 TPR1 24.9Ohm
PIRQA# AD29 C7
PIRQB# D7 C1 1 2 DMI_COMP H24
PIRQC# PIRQB# AD30 DMI_ZCOMP
B3 PIRQC# AD31 B1 J22 DMI_IRCOMP
PIRQD# H10
PIRQE# PIRQD#
E8 PIRQE#/GPIO2 (12) C_PCIE_SB# W23 DMI_CLKN
PIRQF# D6 W24
PIRQF#/GPIO3 (12) C_PCIE_SB DMI_CLKP
PIRQG# H8 H16
PIRQH# PIRQG#/GPIO4 C/BE0#
F8 PIRQH#/GPIO5 C/BE1# M15
C/BE2# C13 MMAP-360
C/BE3# L16
(42) TOPBLOCK_SWAP D11 STRAP0#
RSVD2 K9
RSVD3 RSVD2
M13 RSVD3
MMAP-360
A A
Title : DMI&USB
ASUSTek Computer Inc. Engineer: Henry_Yang
Size Project Name Rev
A3 PINEVIEW 1.0G
Date: Wednesday, January 14, 2009 Sheet 4 of 42
5 4 3 2 1
5 4 3 2 1
5 4 3 2 1
+VCCP
2
CLK 14MHZ has a TPR22
To CPU and
22ohm resistor near LDRQ0/1 LPC DMA/master SATA RX,TX all need AC couple 1KOhm Vcore
clk Gen. request,ICH7M has internal PU, and place near Connector side /X controller
TPR19 0Ohm