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Keysight Technologies
Tips and Advanced Techniques for
Characterizing a 28 Gb/s Transceiver




White Paper




DesignCon 2013
Introduction
With the increased use of data services, the performance demand at every level of
the network is increasing. Just a few years ago, the state of the art was 11 Gigabits
per second (Gb/s) serial channel data transmission. New standards such as OTU4
and 100 GbE, now require greater rates of data throughput, while at the same time
demanding lower power and a smaller physical footprint. These new standards now
call for transceiver rates in excess of 25Gb/s per channel. As a result of this demand,
engineers must now design, develop and validate boards and systems that have
multiple 28Gb/s transceiver channels1. With transceivers running at these rates,
the entire serial transmission and measurement eco-system is challenged. The
serial transmission channel must be designed to support these significantly greater
bandwidths. Additionally, the task of designing, developing, qualifying and validat-
ing the physical hardware layer must adapt to these new challenges. Not only does
this mean that the test equipment hardware must be able to support the increased
bandwidth and dynamic range, but now the instrument software must also be able to
remove the unwanted effects of the interconnecting structures between the DUT and
the test equipment input ports.

Xilinx has manufactured and assembled a printed circuit board test vehicle for the
purpose of demonstrating and characterizing the aforementioned advanced FPGA
with the 28 Gb/s transceivers. Although great care was taken in the design and fab-
rication of the board, there is still some degradation in the signal between the launch
point at the device package pins and the board connectors. For a user to effectively
evaluate the transceiver, they must be able to view the original signal as it appears
at the package pin. Attempting to probe the signal at the package pin is not possible
because the vias at the package pin are back drilled and are not readily accessible
through traditional probing techniques. Even if one could access the pins at the
package pin vias, the probe itself would create even more problems by disturbing the
signal integrity of the channel through the observer effect.

The effects of the interconnection between the test equipment and the DUT can
no longer be ignored as risetimes drop to 15pS ( ~2mm electrical length on a PCB)
for a 28 Gb/s data rate and the corresponding transmission bandwidth jumps to 33
GHz. In complex systems, there is impairment on the connecting fixture channel
caused by package ballout, board vias and traces, connectors, and cables. Since the
channel transfer function acts like a low pass filter, it is critical to be able to isolate
one segment at a time and optimize the path for the targeted frequency range. The
ability to de-embed the interconnecting fixture channel requires up-front design of
calibration standards to correctly place reference planes at the DUT pins as well as
EM simulations to validate and adjust the calibration standards for improved accu-
racy 2. De-embedding of the fixture from a measurement is not new, but the analysis
and trade-offs that must be made in identifying the correct methodology for a 28
Gb/s SERDES measurement at the DUT pin brings up questions like AFR 2x Through
vs. TRL calibrations 3, partial vs. full de-embedding, and filtering vs. bandwidth to
support Fourier Transforms and Nyquist sampling requirements. The challenge
accepted in this experimental signal integrity project is in demonstrating the design,
simulation, measurement, processing, and validation of the fixture de embed model
for a given application.
03 | Keysight | Tips and Advanced Techniques for Characterizing a 28 Gb/s Transceiver - White Paper



Authors
Jack Carrel, Xilinx
Robert Sleigh, Agilent Technologies
Heidi Barnes, Agilent Technologies
Hoss Hakimi, Xilinx
Mike Resso, Agilent Technologies


Abstract
SERDES links screaming along at 28Gb/s are not trivial to validate and measure. The
entire serial transmission and measurement eco-system must be considered to accu-
rately characterize the waveform and jitter performance at the device pin. Even the best
of characterization boards will end up with signal degrading vias, transmission lines, and
connectors on the path from the device to the measuring instrument. Accurate de-em-
bedding requires careful selection and measurement of calibration structures. Measure-
ment based model building enables verification and optimization of the measurement
reference planes. Additionally, the PLL, bandwidth, and peaking enable the recovery of
accurate and compliant jitter measurements with sub-picosecond resolution. The design
and de-embedding of the test fixture path along with the instrument set-up play an
important part in the ability of an oscilloscope to recover the undistorted waveform from
a transmitter pumping out bits every 36 pS.
04 | Keysight | Tips and Advanced Techniques for Characterizing a 28 Gb/s Transceiver - White Paper



Authors Biography
Heidi Barnes, is a Senior Application Engineer for High Speed Digital applications in the
EEsof EDA Group of Agilent. Past experience includes over 6 years in signal integrity for
ATE test fixtures for Verigy, an Advantest Group, and 6 years in RF/Microwave microcir-
cuit packaging for Agilent Technologies. She recently rejoined Agilent Technologies in
April, and holds a Bachelor of Science degree in electrical engineering from the Califor-
nia Institute of Technology.

Mike Resso, the Signal Integrity Applications Expert in the Component Test Division of
Agilent Technologies, has over twenty years of experience in the test and measurement
industry. His background includes the design and development of electro-optic test
instrumentation for aerospace and commercial applications. His most recent activity has
focused on the complete multiport characterization of high speed digital interconnects
utilizing Time Domain Reflectometry (TDR) and Vector Network Analysis (VNA). Mike
has twice received the Agilent Technologies Spark of Insight award for his contributions
to the company. Mike received a Bachelor of Science degree in Electrical and Computer
Engineering from University of California.

Rob Sleigh is a Product Marketing Engineer for sampling scopes in Agilent Technologies'
Oscilloscope Products Division. He is responsible for product development for the divi-
sion's high-speed electrical and optical digital communications analyzer and jitter test
products. Rob's experience at Agilent Technologies/Hewlett-Packard includes 5 years in
technical support, and over 8 years in sales and technical marketing. Prior to working at
Agilent Technologies/HP, Rob worked for 10 years at Westel Telecommunications in Van-
couver, British Columbia, Canada, designing microwave and optical telecommunication
networks. Rob earned his B.S.E.E. degree from the University of Victoria.

Jack Carrel is an Applications Engineer at Xilinx. He has over 25 years of experience in
product development and design in the fields of Instrumentation, Test and Measure-
ment, and Telecommunications. His background includes development of electro-optic
modules, Multi-gigabit transceiver boards, high speed and high resolution data acqui-
sition systems for government and commercial applications. Most recently he has been
involved in product design using multi-gigabit transceivers with specific focus on PCB
design issues. He has published in several professional publications. Jack received his
Bachelor of Science degree in Electrical Engineering from the University of Oklahoma.

Hoss Hakimi is a Principal Engineer at Xilinx. He has 20+ years of experience at various
Telecom, semiconductor, and computer industries specializing on high level behavior
modeling and top-down design methodology in ASIC/FPGA design, synthesis, Substrate
Design, 3D Interconnect Parasitic Extraction, Understanding of high speed signal integ-
rity and PCB power integrity and simulation. Hoss holds an Electrical Engineering from
San Jose State University, and he has completed MS courses in the EE department at
University of California Berkeley.
05 | Keysight | Tips and Advanced Techniques for Characterizing a 28 Gb/s Transceiver - White Paper




Overview of a 28Gbps SERDES Channel
A printed circuit board was designed and built with the following goals:

1. Provide a set of channels for carrying 28Gbps signals from the Xilinx FPGA to an
external device such as a piece of test equipment.
2. Provide a set of test structures that assist with de-embedding the PCB channel.

The signal path for the 28Gbps signals is from the Xilinx Virtex-7 FPGA to SMA connector
that is the working point for connection to devices such as test equipment (e.g. oscillo-
scopes) or data transmission devices (e.g. optical transceivers). The components of the
signal path are:

1. BGA to PCB interface structure including the solder ball pad and BGA launch
structure on the PCB.
2. Differential loosely coupled embedded stripline traces
3. PCB to connector interface structure including vias and connector PCB pads.
4. Samtec BullsEyeTM connector and test cable.

Samtec