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5 4 3 2 1
X17 Block Diagram Project code : 91.4H901.001
PCB Number : 07256 CPU V_CORE
40,41
Revision : SB ISL6265
Thermal
& Fan INPUTS OUTPUTS
DDRII Slot 0
CLK GEN DDRII 667/800 MHz Channel A
AMD S1G2 CPU G792 23 MMC Board:48.4H902.0SA(07940)
667/800 8 DCBATOUT VCC_CORE
ICS9LPRS480 3 SMBUS
D
638-Pin uFCPGA LED Board:48.4H704.0SA(07865) D
DDRII Slot 1 DDRII 667/800 MHz Channel B SYSTEM DC/DC
MMC Board USB Board: 48.4H903.0SB(07939) 43
667/800 9 4,5,6,7 TPS51124
CONN 30
INPUTS OUTPUTS
HyperTransport Power SW
OUT
16X16 G577 24 1D8V_S3
IN
DCBATOUT
DDRIII 52 53 1D2V_S0
DDRII
32Mbx32bitsx4pcs Side Port
North Bridge (64MB)12
ATi M86-ME New Card SYSTEM DC/DC
PCIE x 1 & USB 2.0 x 1 42
TV-OUT 24 PCIE X16
AMD RS780MN 24 TPS51125
VRAMx4 GDDR3 HyperTransport LINK0 CPU I/F
512MB INPUTS OUTPUTS
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DX10 IGP PCIE Mini-Card
HDMI
HDMI CONN 49,50,51,52,53,54,55 LVDS/TVOUT/TMDS PCIE x 1 & USB 2.0 x 1 802.11a/b/g/n 5V_S5
17 24 DCBATOUT
DISPLY PORT X2 3D3V_S5
C
CRT Side Port Memory C
CRT CONN 16 CRT MUX
1 X 16 PCIE I/F RealTek 1000 SYSTEM DC/DC
PCIE x 1 RJ45 CONN
1 X 4 PCIE I/F WITH SB RTL8111C 25 26 45
LVDS
LDO
17'' LCD 15 LVDS MUX 6 X 1 PCIE I/F 10,11,12,13
INPUTS OUTPUTS
PCIE x 1 & USB 2.0 x 1 MINI CARD
TV TUNER 24 5V_S5 0D9V_S3
1394 PCIE 3D3V_S0 1D5V_S0
1394 28
card reader PCIE
4X4 USB 2.0 x 1 Bluetooth 27
SYSTEM DC/DC
JMB380 South Bridge LDO 45
SD/MMC
MS/MS Pro/xD
28
28 AMD SB700 USB 2.0 x 1 WUSB 29
INPUTS OUTPUTS
USB 2.0
3D3V_S5 1D2V_S5
USB 2.0/1.1 ports 3D3V_S0 2D5V_S0
Digital Array Mic USB 2.0 x 1 CAMERA
ETHERNET (10/100/1000Mb) 15
B
32 Azalia High Definition Audio
B
SYSTEM DC/DC
CODEC ATA 66/100
USB 2.0 x 3 USB Board TPS51125 42
AZALIA SATA
MIC IN PCI/PCI BRIDGE (USBx3) 29
ALC888 INPUTS OUTPUTS
ACPI 1.1
LINE IN LPC I/F e-SATA Combo 5V_AUX_S5
STAT & USB 2.0 x 1 DCBATOUT
(USBx1) 29 3D3V_AUX_S5
18,19,20,21,22 PATA
LINE1 OUT/ OP AMP 31
HP OUT G1412 32 SATA MAXIM CHARGER
LED Board HDD x2 47
LPC Bus 30 BQ24745
CONN 37
LINE2 OUT OP AMP INPUTS OUTPUTS
W/SPDIF G1412 33 SATA ODD
30 AD+ DCBATOUT
BT+
KBC
Winbond WPC775L Hyper Flash
27
2CH 35,36
A
SPEAKER
OP AMP A
LPC
G1432Q 32
SPI DEBUG Digitally HsinCorporation
signed Hsichih,dd
Wistron
21F, 88, Sec.1, Tai Wu Rd.,
by
CONN 37 DN: cn=dd, o=dd, ou=dd,
Taipei Hsien 221, Taiwan, R.O.C.
OP AMP CIR Title
email=dddd@yahoo.
SUBWOOFER APA3010 33 35 Touch Int. Flash ROM System Block Diagram
Pad 37 KB37 2MB 36 Size
A3
Document Number
com, c=US
X17
Rev
SA
5 4 3 2
Date: Friday, February 15, 2008
Date:Sheet 1
1
2009.12.04 19:35:22
of 56
+07'00'
5 4 3 2 1
SB700 Functional Strap Definitions
USB PORT# DESTINATION
Note:1 VIP3 MUST NOT BE PULLED HIGH ON M82-M
0 Combo(ESATA/USB) Note:2 GPIO8 MUST NOT BE PULLED HIGH ON M86-M or M7X
D D
1 USB1
PCI EXPRESS DESTINATION RECOMMENDED SETTINGS
0= DO NOT INSTALL RESISTOR
2 USB2 CONFIGURATION STRAPS 1 = INSTALL 10K RESISTOR
Lane 0 NEW CARD X = DESIGN DEPENDANT
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED, NA = NOT APPLICABLE
RSVD = ATI RESERVED
3 CAMERA THEY MUST NOT CONFLICT DURING RESET (DO NOT INSTALL)
Lane 1 WLAN
M8x M7x
STRAPS PIN DESCRIPTION OF DEFAULT SETTINGS
4 Bluetooth
Lane 2 LAN BIF_MSI_DIS VIP1 MESSAGE SIGNAL INTERRUPT ENABLED NA 0
5 NEW CARD BIF_AUDIO_EN VIP3 ENABLE HD AUDIO (M7XM and M86M ONLY) Note:1 X X
Lane 3 CARD READER
2.0 &1394
BIF_64BAR_EN_A VIP5 64 BIT BARS DISABLED NA 0
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6 USB3 TX_PWRS_ENB GPIO0 PCIE FULL TX OUTPUT SWING X X
SB700 Lane 4 TV tuner TX_DEEMPH_EN GPIO1 PCIE TRANSMITTER DE-EMPHASIS ENABLED X X
7 WLAN BIF_DEBUG_ACCESS GPIO4 DEBUG SIGNALS MUXED OUT 0 0
C
Lane 5 NC BIF_AUDIO_EN GPIO8 ENABLE HD AUDIO X RSVD C
( M82M ONLY) Note:2
8 TV TUNER BIF_GEN2_EN_A GPIO5 Allows either PCIe 2.5GT/s or 5.0GT/s operation X 0
BIOS_ROM_EN GPIO_22_ROMCSB DISABLE EXTERNAL BIOS ROM NA X
9 WUSB ROMIDCFG(3:0) GPIO[13:11,9] SERIAL ROM TYPE OR MEMORY APERTURE SIZE SELECT XX X X X X X X
VIP_DEVICE_STRAP_ENA VSYNC IGNORE VIP DEVICE STRAPS O O
10 NC BIF_VGA DIS PSYNC VGA ENABLED 0 O
BIF_HDMI_EN HSYNC HDMI ENABLE (SEE NOTE 2) X X
11 NC DEBUG_ I2C_ENABLE GPIO6 Internal use only 0 0
12 NC MEM_TYPE
ANY UNUSED
GPIO OR DVP MEMORY TYPE,MAKE AND SIZE INFO X X X X X X X X
1.1 THAT ARE NOT
CONFIG STRAPS
13 NC FOR EXAMPLE
DVPDATA20:23
IN THIS DESIGN
B Release BOM need modify B
Page Location Schematic BOM 2nd Source ATI RESERVED CONFIGURATION STRAPS
ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED,
P3 U41(CLK GEN) 71.09480.003 71.09480.003 71.08628.003 THEY MUST NOT CONFLICT DURING RESET
VHAD0 VIP0 VIP2 VIP4 VIP6 VIP7 GPIO2 GPIO3 H2SYNC
P10 U65(RS780MN) 71.RS780.M02 71.RS780.M07
PULLUP PADS ARE NOT REQUIRED FOR THESE STRAPS BUT IF THESE GPIOS ARE USED,
P18 U74(SB700) 71.SB700.M02 71.SB700.M06 THEY MUST NOT CONFLICT DURING RESET
GPIO_28_TDO GENERICC GPIO21_BB_EN
U57,U11,U52,U51,
P41 (CPU power) ZZ.COMBO.001 84.04634.037
NOTE 1: HD AUDIO MUST ONLY BE ENABLED NOTE 2: HDMI MUST ONLY BE ENABLED
U56,U53 ON SYSTEMS THAT ARE LEGALLY ENTITLED. SYSTEMS THAT ARE LEGALLY ENTITLED.
ON
IT IS THE RESPONSIBILITY OF THE SYSTEM IT IS THE RESPONSIBILITY OF THE SYSTEM
DESIGNER TO ENSURE ENTITLEMENT DESIGNER TO ENSURE ENTITLEMENT
P46 U62(GPU power) ZZ.COMBO.001 84.07686.037 Main source 3rd source
A A
U17 (Side Port) 72.18512.M0U(Qimonda) 72.55162.00U(HYNIX) 72.45116.A0U(Samsung)
P12 72.18512.M0U Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
72.18321.A0U(Qimonda 900M) 72.18321.00U(Qimonda 700M) Taipei Hsien 221, Taiwan, R.O.C.
P53 P54
U68~U71 (Vram) 72.18321.00U(Qimonda 700M) 72.41032.B0U(Samsung)
Title
Table of Content
Size Document Number Rev
A3
X17 SA
Date: Friday, February 15, 2008 Sheet 2 of 56
5 4 3 2 1
5 4 3 2 1
3D3V_S0 3D3V_CLK_VDD
R248
1 2
0R3-0-U-GP
1
1
1
1
1
1
1
1
1
C524 C457 C790 C788 C520 C493 C787 C776 C775
3D3V_S0
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
R233
2
2
2
2
2
2
2
2
2
1 2 3D3V_48MPWR_S0
SC4D7U6D3V3KX-GP
1
1
D 3D3V_CLK_VDD C456 C458 D
2D2R3J-2-GP SC1U10V2KX-1GP
DY
2
2
R246
1 2 VDD_REF 3000mA.80ohm
0R3-0-U-GP
1
3D3V_S0 C485
R527 SC1U10V2KX-1GP
1 2
2
0R3-0-U-GP
1D1V_S0 1D1V_CLK_VDDIO
R242
1 2
0R3-0-U-GP
1
1
1
1
1
1
1
DY C472 C523 C519 C789 C783 C784 C786 C469
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
R236 SC27P50V2JN-2-GP
1 DY 2 2 1
2
2
2
2
2
2
2
3D3V_CLK_VDD
1