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1 2 3 4 5 6 7 8
865G-M8 Rev :1.0
A Page Title of Schematic : A
Schematics Version History Table : Title Page Title Page
Circuit Ver. PCB Ver. Total Page Modificatory Page Date Cover Sheet 1
A A 32 uATX 244mmx220mm 01/17/ ' 06 System Block Diagram 2
1.0 1.0 32 02/17/ ' 06 P4 775P Part A 3
P4 775P Part B 4
P4 775P Part C 5
P4 775P Part C 6
P4 775P Part C 7
Clock Generator 8
B I865(MCH)Part A 9 B
I865(MCH)Part B 10
DDR Serial Resistors 11
DDIMM 1&2 ( DDR SDRAMs ) 12
DDR SSTL-2 Terminations 13
DDR Power 14
AGP 8X Slot 1.5V 15
ICH5 Part A 16
ICH5 Part B 17
ICH5 Part C 18
IDE Connector 19
C C
USB/FWH 20
LPC_FDD/KB/M 21
I/O Ports 22
H/W Monitor 23
AC97 Codec 24
Audio Interface 25
ATX Power & Front Panel 26
LAN/CNR 27
775P Vcore DC-DC 28
MIS DC-DC 29
D PCI Slot 1&2 30 D
PCI Slot 3 31
CNR 32 Elitegroup Computer Systems
Title
Cover Sheet
Size Document Number Rev
Custom 865G-M8 1.0
Date: Tuesday, February 21, 2006 Sheet 1 of 32
1 2 3 4 5 6 7 8
A B C D E
PCB : 244 x 220 mm ; 4 layers
intel
DEVICE IDSEL INT# REQ# GNT#
PCI1 16 C/D/E/F PREQ-1 PGNT-1 P4 Processor re.2.0 Prescoot, Cedar Mill & Smithfield
4
PCI2 17 D/E/F/G PREQ-2 PGNT-2 4
PCI3 18 E/F/G/H PREQ-3 PGNT-3
Clock Gen 775 pin
LAN 25 F PREQ-4 PGNT-4
ICS952647
BW : 4.1GB/s @ FSB : 533MHz & Freq : 133MHz
48pin SSOP
BW : 6.4GB/s @ FSB : 800MHz & Freq : 200MHz
BW : 2.1GB/s @ DDR :200/266/333MHz & Freq : 133MHz
BW : 1.066GB/s @ Freq : 66MHz BW : 3.2GB/s @ DDR : 266/333/400MHz & Freq : 200MHz
AGP1 Slot 132p intel
iSP/G DDIMM1: DDR Socket 184P
8X / 1.5V
3
DDIMM2 : DDR Socket 184P 3
VGA (G only) 932pin FC-BGA
BW : 266MB/s @ Freq : 66MHz
USB V2.0
USB1 USB2 USB3 USB4 USBLAN BW : 133MB/s @Freq : 33MHz
2 ports 2 ports 2 ports 2 ports 8 ports intel PCI1 Slot 120pin @ AD16
IDE2 40pin Up to Ultra ATA/100 ICH5 PCI2 Slot 120pin @ AD17
IDE1 40pin Two IDE Channel 460pin EBGA PCI3 Slot 120pin @ AD18
SATA1 7Pin
2
AC' 97 & Lan I/F SATA2 7pin 2
Lan Chip
Audio Codec RTL8100C USBLAN
ALC655 intel LPC bus RJ45
100pin
FWH
32pin PLCC
Mic In Super I/O
Line Out W83627EHF
Line In 128pin PQFP
1 1
Elitegroup Computer Systems
Title
Size
System Block Diagram
Document Number Rev
1.0
B
Date:
865G-M8 2 of
Tuesday, February 21, 2006 Sheet 32
A B C D E
5 4 3 2 1
VTT_OUT_L VTT_OUT_L RSVD_G6
R315 62-O
VTT_OUT_R VTT_OUT_R RSVD_AK6
R316 62-O
MCH_GTLREF_CPU
9 MCH_GTLREF_CPU
BC260
.1U-O
CPUVID0
CPUVID0 21,29
CPUGTLREF1
VSSSEN VSS_SENSE_AN6 01/16/2006 CPUVID1 For Cedar Mill & SMITHFIELD Processor 12/08/2005
29 VSSSEN CPUVID1 21,29
R318 0 CPUVID2
MC118 CPUVID3
CPUVID2 21,29 TRACE WIDTH 10 MIL
CPUVID3 21,29
COMP4
COMP5
COMP6
SPACE 7 MIL
MSID1
MSID0
VCCSEN VCC_SENSE_AN5 10uF-08-O CPUVID4
29 VCCSEN CPUVID4 21,29
R317 0 CPUVID5
CPUVID5 21,29
COMP7
CPU1A ;FOR CEDAR&SMITH;
AM5
AM2
AM3
AC4
AH2
AN5
AN6
G10
AE3
AE4
AE6
AK6
AK4
D14
D16
D23
A20
E23
E24
B13
AL5
AL6
AL4
F23
F29
W1
G6
C9
D1
H2
N4
N5
LGA775 MSID1 R680 60-0402
E5
E6
E7
P5
V1
Y3
F6
T2
J2
J3
D D
MSID0 R681 60-0402
RESERVED0
RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
RESERVED6
RESERVED9
RESERVED10
RESERVED11
RESERVED12
RESERVED13
RESERVED14
RESERVED15
RESERVED16
RESERVED17
RESERVED18
RESERVED19
RESERVED20
RESERVED21
RESERVED22
RESERVED23
RESERVED24
RESERVED25
RESERVED26
RESERVED27
RESERVED28
RESERVED29
RESERVED30
RESERVED31
RESERVED32
RESERVED33
RESERVED34
RESERVED35
VID0
VID1
VID2
VID3
VID4
VID5
VCC_MB_REGULATION
VSS_MB_REGULATION
H_D0 B4 L5 H_A3
9 H_D0 D0 A3 H_A3 9
H_D1 C5 P6 H_A4 ;FOR SMITHFIELD;
9 H_D1 D1 A4 H_A4 9
H_D2 A4 M5 H_A5
9 H_D2 D2 A5 H_A5 9
H_D3 C6 L4 H_A6 ;FOR CEDAR&SMITH;
9 H_D3 D3 A6 H_A6 9
H_D4 A5 M4 H_A7 COMP4 R682 60-0402 VTT_OUT_L VTT_OUT_L
9 H_D4 D4 A7 H_A7 9
H_D5 B6 R4 H_A8
9 H_D5 D5 A8 H_A8 9
H_D6 B7 T5 H_A9 COMP5 R683 60-0402
9 H_D6 D6 A9 H_A9 9
H_D7 A7 U6 H_A10
9 H_D7 D7 A10 H_A10 9
C167
H_D8 H_A11 ;FOR CEDAR&SMITH
0.1uF-0402
9 H_D8 A10 D8 A11 T4 H_A11 9
H_D9 A11 U5 H_A12
9 H_D9 D9 A12 H_A12 9
H_D10 B10 U4 H_A13
9 H_D10 D10 A13 H_A13 9
H_D11 C11 V5 H_A14
9 H_D11 D11 A14 H_A14 9
H_D12 D8 V4 H_A15
9 H_D12 D12 A15 H_A15 9
H_D13 B12 W5 H_A16 ;FOR SMITHFIELD;
9 H_D13 D13 A16 H_A16 9
H_D14 C12 AB6 H_A17 COMP6 R684 60-0402 VTT_OUT_R VTT_OUT_R
9 H_D14 D14 A17 H_A17 9
H_D15 D11 W6 H_A18
9 H_D15 D15 A18 H_A18 9
H_D16 G9 Y6 H_A19 COMP7 R685 60-0402
9 H_D16 D16 A19 H_A19 9
H_D17 F8 Y4 H_A20
9 H_D17 D17 A20 H_A20 9
C168
H_D18 H_A21 ;FOR SMITHFIELD;
0.1uF-0402
9 H_D18 F9 D18 A21 AA4 H_A21 9
H_D19 E9 AD6 H_A22
9 H_D19 D19 A22 H_A22 9
H_D20 D7 AA5 H_A23
9 H_D20 D20 A23 H_A23 9
H_D21 E10 AB5 H_A24
9 H_D21 D21 A24 H_A24 9
H_D22 D10 AC5 H_A25
9 H_D22 D22 A25 H_A25 9
H_D23 F11 AB4 H_A26
9 H_D23 D23 A26 H_A26 9
H_D24 F12 AF5 H_A27
9 H_D24 D24 A27 H_A27 9
H_D25 D13 AF4 H_A28
9 H_D25 D25 A28 H_A28 9
H_D26 E13 AG6 H_A29
9 H_D26 D26 A29 H_A29 9 VTT_OUT_R
H_D27 G13 AG4 H_A30
9 H_D27 D27 A30 H_A30 9
H_D28 F14 AG5 H_A31
9 H_D28 D28 A31 H_A31 9
H_D29 G14 AH4
9 H_D29 H_D30 D29 A32
9 H_D30 F15 D30 A33 AH5
H_D31 G15 AJ5
9 H_D31 H_D32 D31 A34 H_BPM0 ER134 49.9-1
9 H_D32 G16 D32 A35 AJ6
H_D33 E15
9 H_D33 H_D34 D33 H_BPM1 ER135 49.9-1
9 H_D34 E16 D34
H_D35 G18 AJ2 H_BPM0
9 H_D35 H_D36 D35 BPM0 H_BPM1 H_BPM2 ER136 49.9-1
C
9 H_D36 G17 D36 BPM1 AJ1 C
H_D37 F17 AD2 H_BPM2
9 H_D37 H_D38 D37 BPM2 H_BPM3 H_BPM3 ER137 49.9-1
9 H_D38 F18 D38 BPM3 AG2
H_D39 E18 AF2 H_BPM4
9 H_D39 H_D40 D39 BPM4 H_BPM5 H_BPM4 ER138 49.9-1
9 H_D40 E19 D40 BPM5 AG3
H_D41 F20
9 H_D41 H_D42 D41 H_BPM5 ER139 49.9-1
9 H_D42 E21 D42
H_D43 F21 J16
9 H_D43 H_D44 D43 DP0
9 H_D44 G21 D44 DP1 H15
H_D45 E22 H16
9 H_D45 H_D46 D45 DP2
9 H_D46 D22 D46 DP3 J17
H_D47 G22
9 H_D47 H_D48 D20
D47 Please BMP TERMINATION NEAR to CPU
9 H_D48 H_D49 D48 H_REQ0
9 H_D49 D17 D49 REQ0 K4 H_REQ0 9
H_D50 A14 J5 H_REQ1
9 H_D50 D50 REQ1 H_REQ1 9
H_D51 C15 M6 H_REQ2
9 H_D51 D51 REQ2 H_REQ2 9
H_D52 C14 K6 H_REQ3
9 H_D52 D52 REQ3 H_REQ3 9
H_D53 B15 J6 H_REQ4
9 H_D53 D53 REQ4 H_REQ4 9
H_D54 C18
9 H_D54 H_D55 D54
9 H_D55 B16 D55
H_D56 A17 AE8
9 H_D56 H_D57 D56 SKTOCC
9 H_D57 B18 D57
H_D58 C21
9 H_D58 H_D59 D58 TESTHI0
9 H_D59 B21 D59 TESTH0 F26
H_D60 B19 W3 TESTHI1
9 H_D60 H_D61 D60 TESTH1
9 H_D61 A19 D61 TESTH2 F25
H_D62 A22 G25
9 H_D62 H_D63 D62 TESTH3
9 H_D63 B22 D63 TESTH4 G27
TESTH5 G26
G24 TESTHI12 R319 62 VTT_OUT_L VTT_OUT_L
H_RS0_L TESTH6 TESTHI2_7
9 H_RS0_L B3 RS0 TESTH7 F24
H_RS1_L F5 G3 TESTHI8 BC261 .1U
9 H_RS1_L H_RS2_L RS1 TESTH8 TESTHI9
9 H_RS2_L A3 RS2 TESTH9 G4
H5 TESTHI10
TESTH10 TESTHI11
TESTH11 P1
W2 TESTHI12 BOOTSEL R320 1K-O VTT_OUT_R
TESTH12
TESTHI0 R321 62 V_FSB_VTT
B B
Y1 BOOTSEL
H_D[0..63] BOOTSELECT TESTHI2_7 R322 62
H_D[0..63] 9
TESTHI1 R323 62 VTT_OUT_L
H_A[3..31]
H_A[3..31] 9
TESTHI8 R324 62
TESTHI9 R325 62
TESTHI10 R326 62
For Cedar Mill Processor 12/08/2005
TESTHI11 R327 62
FOR Prescoot remove this circuit
Close CPU H1 pin 7/5
Please Rs & CAPs Close to CPU
CPUGTLREF1 VTT_OUT_R VTT_OUT_R
R686 49.9-1
1
220P
100-1
1U
C169
C170
R687
C171
.01U
GTLREF= 0.67 * VTT = 0.8V
2
GTLREF GENERATION CIRCUITS
A A