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1
01
Page Title of schematic page Rev. Date Page Title of schematic page Rev. Date
01 Page List 1B 11/12 23 KB/USB/FAN/PS 1B 12/03
02 Block Diagram 1B 24 VCORE(ISL6265A) 1B
03 CPU HT/ CONTROL(1/3) 1B 11/12 25 3VPCU&5VPCU(PM6686) 1B
04 CPU MEMORY(2/3) 1B 26 1.5VSUS/VTT_MEM 1B
05 CPU POWER/GND(3/3) 1B 11/30 27 DYN_VCC1.1(OZ8116LN) 1B
06 RS880M HT/SPMEM(1/4) 1B 11/12 28 VCC1.1(OZ8116LN)-7A 1B
07 RS880M GFX/PCIE(2/4) 1B 29 VCC1.8/0.9/2.5/1.0 1B
08 RS880M SYSTEM(3/4) 1B 12/15 30 POWER(BAT IN / ADA IN/ UL) 1B
09 RS880M POWER(4/4) 1B 31 CHARGER (ISL6252A) 1B
10 SB820M PCI/CLK/LPC(1/4) 1B 12/15 32 SMALL BOARD 1B 11/30
11 SB820M AUDIO/USB(2/4) 1B 12/07 33 POWER SEQUENCE 1B
12 SB820M SATA(3/4) 1B 12/07 34 CHANGE LIST 1B
A A
13 SB820M POWER(4/4) 1B
14 DDR3 SODIMMX2 1B 12/07
15 CRT/LVDS 1B 11/12
16 HDMI 1B 12/15
17 WLAN/HDD/ODD 1B 11/30
18 CARD READER(RTS5186) 1B 12/15
19 Express Card/LED/BT 1B 12/15
20 Codec(ALC269Q-VB5-GR) 1B 12/07
21 LAN RTL8111E 1B 12/15
22 NPCE781 1B 12/15
QUANTA
Title
COMPUTER
PAGE LIST
Size Document Number Rev
1.Level 1 Environment-related Substances Should NEVER be Used. B 3A
2.Purchase ink, paint, wire rods, and Molding resins only from the business Partners that Sony approves as Green Partners.
AMD
Date: Saturday, March 20, 2010 Sheet 1 of 34
1
1 2 3 4 5
Danube Block Diagram 02
GLAN #0 UNBUFFERED
RJ45 DDRIII 1333MT/S DDR3
Realtek RTL8111E P21
AMD S1G4 CPU SODIMM-A
P14
A A
Champlain
#1 638 PIN (uFCPGA) UNBUFFERED
P3-5 DDRIII 1333MT/S DDR3
SODIMM-B
Hyper Transport P14
LINK0
16x16
#2
LVDS LCD P15
WLAN Module
802.11bgn P17
#3
RS880M R/G/B
CRT P15
PCIE-Gen2
#4 528 PIN (BGA) HDMI HDMI 1.3
P16
21mm x 21mm
P6-9
#5
PCIE(X4)
B B
HDA Link
SB820M Realtek ALC269Q-VB5-GR
P20
528 Pin BGA
21mm x 21mm
P10-13
MIC. Jack Audio Jack INT.SPKR. Digital MIC
USB 1.1/2.0
3.3V LPC,33MHZ
P32 P32 P20 P15
SATA
SATA
SD HC MS DUO
Card Reader
RTK RTS5186 P18
C C
USB Slot *3 SATA HDD *1 SATA ODD *1
P23 P17 P17
Camera
PCU
P15
NPCE781
ExpressCard *1 P22
ExpressCard
P19
USB CON*1 Blue Tooth
P19 SPI
INT.K/B
LED Button
TOUCH PAD BIOS Power/Speep POWER
PCI-E *1 P23 P22
NUM/CAPS/SCRL Wireless
T/P SWITCH
Wireless ASSIST
HDD VAIO
MS/SD WEB
D Charge D
QUANTA
Title
COMPUTER
Block Diagram
Size Document Number Rev
1.Level 1 Environment-related Substances Should NEVER be Used. Custom AMD 3A
2.Purchase ink, paint, wire rods, and Molding resins only from the business Partners that Sony approves as Green Partners.
Date: Saturday, March 20, 2010 Sheet 2 of 34
1 2 3 4 5
5 4 3 2 1
VCC1.1
1.5A(1.8W) VCC2.5
3A:addC291 & C137 change from 0.1u to 180pf
T33
C291
CPU_LDT_RST#
180p_4
CPU_LDT_REQ#_CPU
R58
R55
301/F_4
*301/F_4
03
VCC1.5
for power noise T14 CPU_LDT_PWRGD R64 301/F_4
C113 C111 C114 C109 C25 C26 C27 C137
4.7U/6.3V_6 4.7U/6.3V_6 4.7U/6.3V_6 0.22u_4 0.22u_4 180p_4 180p_4 180p_4
3A:R69 change to short pad C179 C154 C153 CPU_LDT_STOP# R52 301/F_4 VCC1.5
4.7U/6.3V_6 1U_4 0.1u_4 U21D
D U21A F8 M11 D
HCLK_CPU_C R54 169/F_4 HCLK_CPU#_C VDDA1 VSS R19 10K_4
T10 T11 F9 VDDA2 RSVD11 W18 1.5VSUS
VCC1.1 D1 VLDT_A0 HT LINK VLDT_B0 AE2 VCC1.1
D2 AE3 C134 3900p_4 HCLK_CPU_C A9 A6 CPU_SVC_R
VLDT_A1 VLDT_B1 10 CLK_CPU_HTP CLKIN_H SVC
D3 AE4 C133 3900p_4 HCLK_CPU#_C A8 A4 CPU_SVD_R 1.5VSUS R18 1K/F_4 C182 3A:reserve C182 0.1
10 CLK_CPU_HTN
2
VLDT_A2 VLDT_B2 CLKIN_L SVD Q3 *0.1u_4
D4 VLDT_A3 VLDT_B3 AE5
R69 *short_4 R_CPU_LDT_RST# B7 MMBT3904
10 CPU_LDT_RST# RESET_L
HT_CADIN_H0 E3 AD1 HT_CADOUT_H0 CPU_LDT_PWRGD A7 CPU_THERMTRIP#_L 1 3
L0_CADIN_H0 L0_CADOUT_H0 10,24 CPU_LDT_PWRGD PWROK CPU_THERMTRIP# 11
HT_CADIN_L0 E2 AC1 HT_CADOUT_L0 CPU_LDT_STOP# F10 AF6 CPU_THERMTRIP#_L
L0_CADIN_L0 L0_CADOUT_L0 8,10 CPU_LDT_STOP# LDTSTOP_L THERMTRIP_L
HT_CADIN_H1 E1 AC2 HT_CADOUT_H1 CPU_LDT_REQ#_CPU C6 AC7 CPU_PROCHOT# 3A:reserve C184 0.1uF
HT_CADIN_L1 L0_CADIN_H1 L0_CADOUT_H1 HT_CADOUT_L1 2/10 add R69 short pad for Guam for debug LDTREQ_L PROCHOT_L CPU_MEMHOT#_L
F1 L0_CADIN_L1 L0_CADOUT_L1 AC3 MEMHOT_L AA8
HT_CADIN_H2 G3 AB1 HT_CADOUT_H2 CPU_SIC AF4 1.5VSUS R32 1K/F_4
L0_CADIN_H2 L0_CADOUT_H2 11 CPU_SIC SIC
HT_CADIN_L2 G2 AA1 HT_CADOUT_L2 CPU_SID AF5 C184
L0_CADIN_L2 L0_CADOUT_L2 11 CPU_SID SID
HT_CADIN_H3 G1 AA2 HT_CADOUT_H3 CPU_ALERT AE6 W7 THERMDC *0.1u_4
HT_CADIN_L3 L0_CADIN_H3 L0_CADOUT_H3 HT_CADOUT_L3 ALERT_L THERMDC THERMDA R33 *0_4
H1 L0_CADIN_L3 L0_CADOUT_L3 AA3 THERMDA W8 22 CPU_PROCHOT CPU_PROCHOT# 10
HT_CADIN_H4 J1 W2 HT_CADOUT_H4 R34 44.2/F_4 HT_REF0 R6
HT_CADIN_L4 L0_CADIN_H4 L0_CADOUT_H4 HT_CADOUT_L4 R35 44.2/F_4 HT_REF1 HT_REF0
K1 L0_CADIN_L4 L0_CADOUT_L4 W3 VCC1.1 P6 HT_REF1
3
HT_CADIN_H5 L3 V1 HT_CADOUT_H5
HT_CADIN_L5 L0_CADIN_H5 L0_CADOUT_H5 HT_CADOUT_L5
L2 L0_CADIN_L5 L0_CADOUT_L5 U1 24 CPU_VDD0_FB_H F6 VDD0_FB_H VDDIO_FB_H W9 3A:change Prochot to meet NEO.
HT_CADIN_H6 L1 U2 HT_CADOUT_H6 1.5VSUS R234 1K/F_4 CPU_SIC E6 Y9
L0_CADIN_H6 L0_CADOUT_H6 24 CPU_VDD0_FB_L VDD0_FB_L VDDIO_FB_L
HT_CADIN_L6 M1 U3 HT_CADOUT_L6 R233 1K/F_4 CPU_SID 2
HT_CADIN_H7 L0_CADIN_L6 L0_CADOUT_L6 HT_CADOUT_H7 R231 1K/F_4 CPU_ALERT
N3 L0_CADIN_H7 L0_CADOUT_H7 T1 24 CPU_VDD1_FB_H Y6 VDD1_FB_H VDDNB_FB_H H6 CPU_VDDNB_FB_H 24
HT_CADIN_L7 N2 R1 HT_CADOUT_L7 AB6 G6 Q28
L0_CADIN_L7 L0_CADOUT_L7 24 CPU_VDD1_FB_L VDD1_FB_L VDDNB_FB_L CPU_VDDNB_FB_L 24 1.5VSUS
HT_CADIN_H8 E5 AD4 HT_CADOUT_H8 2N7002E
HT_CADIN_L8 L0_CADIN_H8 L0_CADOUT_H8 HT_CADOUT_L8 CPU_DBRDY
F5 AD3 T21 G10
1
C
HT_CADIN_H9 L0_CADIN_L8 L0_CADOUT_L8 HT_CADOUT_H9 CPU_TMS DBRDY C
F3 L0_CADIN_H9 L0_CADOUT_H9 AD5 T13 AA9 TMS DBREQ_L E10 CPU_DBREQ# R40 301/F_4 1.5VSUS
HT_CADIN_L9 F4 AC5 HT_CADOUT_L9 TDITDOTCK T9
CPU_TCK AC9
HT_CADIN_H10 L0_CADIN_L9 L0_CADOUT_L9 HT_CADOUT_H10 CPU_TRST# TCK 1.5VSUS
G5 L0_CADIN_H10 L0_CADOUT_H10 AB4 TMSTRST_Lfor ICT T16 AD9 TRST_L TDO AE9 CPU_TDO T5
HT_CADIN_L10 H5 AB3 HT_CADOUT_L10 CPU_TDI AF9 R31
L0_CADIN_L10 L0_CADOUT_L10 T4 TDI
HT_CADIN_H11 H3 AB5 HT_CADOUT_H11 *10K_4
HT_CADIN_L11 L0_CADIN_H11 L0_CADOUT_H11 HT_CADOUT_L11 CPUTEST23
H4 L0_CADIN_L11 L0_CADOUT_L11 AA5 T3 AD7 TEST23 TEST28_H J7 T6
HT_CADIN_H12 K3 Y5 HT_CADOUT_H12 H8
L0_CADIN_H12 L0_CADOUT_H12 TEST28_L T7
2
HT_CADIN_L12 K4 W5 HT_CADOUT_L12 R62 1K/F_4 CPUTEST18 H10 R27 Q4
HT_CADIN_H13 L0_CADIN_L12 L0_CADOUT_L12 HT_CADOUT_H13 R72 1K/F_4 CPUTEST19 TEST18 *MMBT3904
L5 L0_CADIN_H13 L0_CADOUT_H13 V4 G9 TEST19 TEST17 D7 T12 *1K/F_4
HT_CADIN_L13 M5 V3 HT_CADOUT_L13 1B: install R41 E7 T8
CPU_MEMHOT#_L 3 1 MEMHOT# 10,14
HT_CADIN_H14 L0_CADIN_L13 L0_CADOUT_L13 HT_CADOUT_H14 R41 510/F_4 CPUTEST25H TEST16 R44 *301/F_4
M3 L0_CADIN_H14 L0_CADOUT_H14 V5 1.5VSUS E9 TEST25_H TEST15 F7
HT_CADIN_L14 M4 U5 HT_CADOUT_L14 R46 510/F_4 CPUTEST25L E8 C7 R67 *301/F_4 S1g4 does not support MEMHOT#
HT_CADIN_H15 L0_CADIN_L14 L0_CADOUT_L14 HT_CADOUT_H15 TEST25_L TEST14
N5 L0_CADIN_H15 L0_CADOUT_H15 T4 T1
HT_CADIN_L15 P5 T3 HT_CADOUT_L15 R9 1K/F_4 CPUTEST21 AB8 C3
L0_CADIN_L15 L0_CADOUT_L15 R10 1K/F_4 CPUTEST20 TEST21 TEST7
AF7 TEST20 TEST10 K8
HT_CLKIN_H0 HT_CLKOUT_H0 R13 1K/F_4 CPUTEST24 VFIX MODE
HT_CLKIN_L0
J3
J2
L0_CLKIN_H0 L0_CLKOUT_H0 Y1
W1 HT_CLKOUT_L0 R14 1K/F_4 CPUTEST22
AE7
AE8
TEST24
C4 CPUTEST29H VID Override Circuit
HT_CLKIN_H1 L0_CLKIN_L0 L0_CLKOUT_L0 HT_CLKOUT_H1 R12 1K/F_4 CPUTEST12 TEST22 TEST8
J5 L0_CLKIN_H1 L0_CLKOUT_H1 Y4 AC8 TEST12
HT_CLKIN_L1 K5 Y3 HT_CLKOUT_L1 1.5VSUS R15 1K/F_4 CPUTEST27 AF8 SVC SVD Voltage Output
L0_CLKIN_L1 L0_CLKOUT_L1 TEST27 R73
TEST29_H C9
HT_CTLIN_H0 HT_CTLOUT_H0
HT_CTLIN_L0
N1
P1
L0_CTLIN_H0 L0_CTLOUT_H0 R2
R3 HT_CTLOUT_L0
C2
AA6
TEST9 TEST29_L C8 80.6/F_4
0 0 1.1V
HT_CTLIN_H1 L0_CTLIN_L0 L0_CTLOUT_L0 HT_CTLOUT_H1 TEST6 CPUTEST29L
HT_CTLIN_L1
P3
P4
L0_CTLIN_H1 L0_CTLOUT_H1 T5
R5 HT_CTLOUT_L1 A3 H18
0 1 1.0V
L0_CTLIN_L1 L0_CTLOUT_L1 RSVD1 RSVD10
B 3A:delete R238 A5 RSVD2 RSVD9 H19
1 0 0.9V B
B3 RSVD3 RSVD8 AA7
SOCKET_638_PIN B5
C1
RSVD4 RSVD7 D5
C5
1 1 0.8V
HT_CADIN_H[0..15] 6 HT_CADOUT_H[0..15] 6 RSVD5 RSVD6
HT_CADIN_L[0..15] 6 HT_CADOUT_L[0..15] 6
SOCKET_638_PIN
HT_CLKIN_H[0..1] 6 HT_CLKOUT_H[0..1] 6
VCC1.5 R48 1K/F_4
HT_CLKIN_L[0..1] 6 HT_CLKOUT_L[0..1] 6
3A:delete R51,R50 R53 1K/F_4
HT_CTLIN_H[0..1] 6 HT_CTLOUT_H[0..1] 6
CPU_SVC_R
HT_CTLIN_L[0..1] 6 HT_CTLOUT_L[0..1] 6 CPU_SVC 24
CPU_SVD_R
CPU_SVD 24
R61 *301/F_4
Q5 R45 *301/F_4
3A:delete con20 & C31 & C267
SMB_CLK 1 6 BATT_SCK 22,30
VCC3
VCC3 R66 10K_4 2 VCC3
U8
C138 0.1u_4 1 8 SMB_CLK
A VCC SMBCLK SMB_CLK A
SMB_DAT 4 3
11 TS_ALERT# 6 ALERT SMDATA 7 SMB_DAT
SMB_DAT
VCC3 R74 10K_4 5 VCC3
BATT_SDA 22,30
QUANTA
THERMDA
25 SHDN# 4
5
T_CRIT_A D+ 2
3
2N7002DW
Title
COMPUTER
GND D- C143
G780P81U 220p_4 CPU HT/CONTROL(1/3)
THERMDC Size Document Number Rev
1.Level 1 Environment-related Substances Should NEVER be Used. Custom 3A
2.Purchase ink, paint, wire rods, and Molding resins only from the business Partners that Sony approves as Green Partners.
AMD
Date: Saturday, March 20, 2010 Sheet 3 of 34
5 4 3 2 1
5 4 3 2 1
1.5VSUS VCC0.9 U21B
CPU_VDDR35W->0.9V
VCC0.9