Text preview for : A22-6900-1_DataAcquisitionFeatures.pdf part of IBM A22-6900-1 DataAcquisitionFeatures IBM 360 model44 A22-6900-1_DataAcquisitionFeatures.pdf



Back to : A22-6900-1_DataAcquisitio | Home

File No. S360-13
Form A22-6900-1




Systems Reference Library




Data Acquisition Special Features for the
IBM System/360 Model 44


trol, and interface of three special features:
Direct Word
Direct Data Channel
Priority Interrupt
These features are particularly suitable for high-speed data
acquisition and relatively complex control applications in the
scientific fields.
Additional information can be found in IBM System/360 Model
44 Functional Characteristics, Form A22-6875, and IBM System/
360 Principles of Operation, Form A22-6821.
SECOND EDITIOl'

This is a major revision of, and obsoletes, A22-6900-0. Changes to the text
are indicated by a vertical line to the left of the change; revised illustrations
are denoted by the symbol. to the left of the caption.
Significant changes or additions to the specifications contained in this
publication will be reported in subsequent revisions or Technical Newsletters.



Requests for copies of IBM publications should be made to your IBM repre-
sentative or to the IBM branch office serving your locality.



This manual has been prepared by the IBM Systems Development Division,
Product Publications, Dept. B98, P.O. Box 390, Poughkeepsie, New York
12602. Send comments concerning the manual to this address.
Contents




Direct Word . 5
Operation .... 5
Instructions 5
Write Direct Word 5
Read Direct Word 5
Interface between CPU and External Devices 6
Interface Lines and Signal Timings 6
Connectors and Pin Assignments 8
U sing Direct \Vord with External Interrupt 8
Electrical Specifications 8
Direct Data Channel 12
Operation 12
I/O Addressing 12
Instructions 12
Start I/O 12
Test I/O
Halt I/O 18
1 est Channel . . . . . . . . . . . . 10
Channel Status Word 13
Interface between CPU and External Devices 13
Interface Lines and Signal Timings . . . . . . . . . . . . .. 13
Connectors and Pin Assignments 16
Electrical Specifications 16
Priority Interrupt .................. . 17
Operation .............. . 17
Advanced System Requirements 17
Compatibility with Other System/360 Models 17
Signal Exchanges 17
Interrupt Levels ... 18
Priority and Masking of Interrupts .. . ........ 19
Conflicts between Priority Interrupts and
Basic System Interrupts . . . . . . . . . . . . . . . . .. 20
Instructions 20
Load PSW Special . . . . . ........ 20
Change Priority Mask 21
Systems Programming with Priority Interrupts 21
Response Times 23
Interface between CPU and External Devices 24
Interface Lines and Signal Timings 24
Connectors and Pin Assignments 26
Electrical Specifications 26
Direct Word




Operation erand is located on a word boundary; otherwise, a
The direct word feature provides for the transfer of a specification exception results in a program interrup-
full 32-bit word of information between an external tion.
device and the main storage of the system. Its purpose The eight signal-out lines are utilized also for READ
IHHECT WOHD.
is io permii communicaiion with a variety of non-IBM
Time in ~licroseconds: 3.0 basic, 2.25 with high-
external devices in the function of data acquisition. It
corresponds closely to the direct control feature of
System/360, but it has no interrupt lines and also differs
Ispeed general registers, using single in.dexing (B =1= 0 ).
Condition Code: The code remains the same.
significantly in passing a word rather than a byte. Program Interruptions:
Sometimes this feature may be expediently reserved Operation (The direct word feature is not in-
for the passing of control and synchronizing informa- stalled. The operation is suppressed.)
tion while the system channels are used for the volume Privileged Operation (The instruction is encoun-
of data, although this is not a restriction. tered with the CPU in the problem state. The
Information and control signals are exchanged over operation is suppressed.)
the direct word interface lines (Figure 1). To effect Protection (The operand location is protected for
the transfer of the word of information, two instruc- fetching, and the key in storage does not match
tions are added to the Model 44 instruction set: WRITE the protection key in the psw. The operation is
DIRECT WORD to place a word on the direct-out lines, terminated. )
and READ DIRECT \YORD to take information from tlw 0\ (~dressing (TIle opcrarld l()cation is Olltsidc the
direct-in lines. available main storage of the installation. The
upUaliUIJ .i~ lc1ll1.illateJ.)
Specification (The operand is not located on a
Instructions \vord boundary. The operation is suppressed.)

Write Direct Word Read Direct Word

WRDW Dl (8 1 ), '2 [SI] RDDW Dl (8 1), '2 [Sl]


---1-- --7 --] -----------]-----------------r----------------]
~5
[ _____ ____________ ~2 I __~I
_____ ~~
____________ ______ _
----~~-
2
-- -- -I-~I-J------~~----
[ ---------- - --- ---- - -- -- ----- ---- ----- o 7 8 15 16 19 20 31
o 78 15 16 1920 31
Unless a signal is present on the hold-in line, this in-
This instruction causes the word at the location desig- struction causes a word of data to be accepted from the
nated by the operand address to be fetched from 32 direct-in lines and placed in the location designated
storage and made available as a set of 32 static signals hy the operand address. No parity is accepted with
on the direct-out lines. These signals remain available the data signals, but four parity bits are generated as
on the direct-out lines until the next WRITE DIRECT WORD the data are placed in storage.
is executed. No parity is presented with these 32 data The eight instruction bits 8-15 are made available
hits. ( unconditionally) as 0.5 to 1 microsecond timing pulses
Also, the eight instruction bits 8-15 are made avail- on the signal-out lines. No parity is presented with
ahle as 0.5 to 1 microsecond timing pulses on the signal- these eight bits.
out lines. No parity is presented with these eight bits. Concurrently with the eight signal-out pulses, a 0.5
Concurrently with the eight signal-out pulses, a 0.5 to 1 microsecond timing pulse is provided on the read-
to 1 microsecond timing pulse is provided on the write- out line.
out line. The timing of the signal-out and write-out The hold-in line is tested for the presence of a hold
pulses is such that they overlap the change of the static I signal after the read-out signal has been completed; if
signals on the direct-out lines. data are to be accepted, the hold signal must be absent
The operand address must have zeros in its two low- for at least 0.5 microsecond. As long as the hold signal
order bit positions, thereby designating that the op- is present, the CPU does not complete the operation.

Direct \Von.l 5
(Excessive duration of the operation may cause timer
updating to be omitted.)
~
The operand address must have zeros in its hvo low- ~ illil
order bit positions, thereby designating that the oper- ~~ t
'~ I
and is located on a word boundary; otherwise, a speci-
fication exception results in a program interruption.
The eight signal-out lines are utilized also for WRITE

Time in ;Uicroseconds: 4.5 basic, 3.7,5 with high-
speed general registers, plus external delay, using
single indexing (B -# 0).
) ~-+__________~~~~__~Si=gn~al~O~u~t7 -4.T .
__
Signal Out 0



I !'III ~
Condition Code: The code remains unchanged. Direct Ward 1 Line Read Out
Feature
Program Interruptions: (In CPU) 1 Line Write Out

Operation (The direct word feature is not in- _~LJ~ ________ ~j_
I
_li() 19~ ____~---EJ
stalled. The operation is suppressed.)
Direct In 0
Privileged Operation (The instruction is encoun- 32 Lines
Direct In 31
tered with the CPU in the problem state. The
operation is suppressed.)
Part Number 5372977
Protection (The operand location is protected
for storing, and the key in storage does not Part Number 5372977

match the protection key in the psw. The op- Part Number 5372977
IBM cables supplied for the direct word
eration is terminated.) feature are available in lengths up to 50 OEM
feet. Longer cables may be obtained on
Addressing (The operand location is outside the request price quotatian (RPQ) basis.
Control
Unit
available main storage of the installation. The Part Number 5372980
operation is terminated.) Part Number 5372980

Specification (The operand is not located on a Part Number 5372980
word boundary. The operation is suppressed.)
See Figure 3
Programming Note NOTES-
In the case of a single data source (for example, 32 * Maximum length of stub (connecting line to circuit card) is 6 inches.
** Burndy connector ME23XR-1, mounted on the non-IBM unit, is supplied by the user.
contact sense points), the hold-in line may be left per- T = Li'le terminator

manently down. If external logic is provided to switch
one of several data sources onto the direct-in lines, the Figure 1. Interface Lines and Cabling for Direct Word Feature
hold-in line is raised to prevent the CPU from sampling
minimum of 100 nanoseconds; that is, data already on
the 32 lines while the data are changing and therefore
the direct-out lines are valid for at least 100 nano-
invalid.
seconds after the rise of the write-out pulse to its up
level, and new data are valid for at least 1oo nano-
seconds before the fall of the write-out pulse below its
Interface between CPU and External Devices u n lcn'Dl
L'P . I v \ ' \......-.1.


Interface Lines and Signal Timings The write-out pulse has a minimum width of 500
All the interface lines and the cabling necessary to nanoseconds and a maximum width (including tran-
carry them are shown in Figure 1. sitions) of 1,000 nanoseconds. Once the write-out
The signals on the interface lines, functionally de- pulse falls, it does not rise for at least 500 nanoseconds.
scribed under "vVrite Direct \Vord" and "Read Direct
Direct-In, Hold-In, Read-Out
'Vord," have timings presented in more detail here and
The down level of the hold-in signal indicates that the
in Figure 2. In the fo11owing descriptions, the up level
static signals on the 32 direct-in lines are no longer
is the active level: the down level is the inactive level.
changing from old data to new data and are there-
Direct-Out, Write-Out fore valid for transfer to main storage.
The down level of the write-out pulse indicates that The up level of the hold-in signal must overlap the
the static signals on the 32 direct-out lines are no transition of the signals on the direct-in lines by a
longer changing from old data to new data and are minimum of 100 nanoseconds; that is, data already on
therefore valid for transfer to the external device. the direct-in lines must be valid for at least 100 nano-
The up level of the write-out pulse overlaps the seconds after the rise of the hold-in signal to its up
transition of the signals on the direct-out lines by a level, and new data must be valid for at least 100

6
><-
------------__
~ A ----..I
I I

Direct Out (Data from Old Data : : New Data
Storage, 32 Bits) _____ - - - ________ h _ h _____ - - - - - - - - - - - - - - - - - - - -




(Static Signals)

~ ------..1 ~ U -----t-+I
~ :~ H .! C l+-
I I ~ I

Write Out (Pulse)
~ I
i ~'--------------------------------'~
I
"I. ! I


---+-I
:.


1
0 I.
1


I
L
J
I

.. I
I
E ~
I
P - - - - - - - - - 1~1
..




Signal Out (Bits 8-15
of Instruction)(Pulses) ~ i
i~ N
: : "------------------------------~~
I



:. : M : "I~ 0 - - - - - - - - - 1-.;1
..
-l :. K ... : G f+-
Til


N
I I




Read Out (Pulse)
~
:~ : I I -------------------------~
I
I 1 I
I~ N "I~ R III
NOTE: Signals shown as seen at output of receiver, that is, inverse to interface signals.

A,B,C,D,E,F,G Maximum transition time is 200 nanoseconds.

H, J, K Minimum duration is 500 nanoseconds.

L, M, N Maximum, including transition, 1,000 nanoseconds.

B, l) Leading edges coincidental within skew tolerances.
_, _ _ 1-_

.................. '''::;1 .......... :::;1'--' ...... " " " , ..... ,'-"'-,,''-'',