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1 1




QCLA4,5
2




Eureka 14" & 15" 2




LA-8862P REV 0.2 Schematic
3
Intel Processor(Ivy Bridge / Sandy Bridge) 3




PCH(Panther Point)
2011-11-24 Rev 0.2




4 4




Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/01/31 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
B 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QCLA4,5
Date: Thursday, February 16, 2012 Sheet 1 of 48
A B C D E
A B C D E




Intel CPU
Ivy Bridge
Sandy Bridge
eDP Conn.
1

rPGA-989 Memory BUS(DDRIII) 200pin DDRIII-SO-DIMM X2 1

page 13
37.5mm*37.5mm Dual Channel BANK 0, 1, 2, 3 page 11,12

page 5,6,7,8,9,10 1.5V DDRIII 1066/1333/1600 MT/s




CRT FDI X8 DMI X4
page 14
2.7GT/s 5GT/s



USB30 4x USB Right USB Left
5V 5GT/s USB20 port 2,3 USB20 port 0,1
USB30 port 3,4 USB30 port 1,2
USB20 4x page 25 page 30
LVDS Conn.
5V 480MHz
page 13

2
USB20 3x FingerPrinter Int. Camera 2


5V 480MHz USB port 8 USB port 11
EC SMBus page 29 page 13
HDMI-CEC HDMI Conn.
page 15

page 15 Intel PCH USB20 3x PCIeMini Card PCIeMini Card
5V 480MHz
Panther Point PCIe Gen1 1x
WiMax USB port 9 3G/TV#1
TV#2
USB port 12
USB port 10
page 27 page 27
1.5V 5GT/s
RJ45 RTL8105E-VD 10/100M PCIe Gen1 1x PCIeMini Card
SATA Gen3 port 1
page 40 RTL8111F-VB 1G 1.5V 5GT/s
5V 6GHz(600MB/s) WLAN PCIe port 2 mSATA
PCIe port 1 page 31 SATA port 1
FCBGA-989 page 27 page 27 B-CAS SIM
25mm*25mm page 26 page 27

Cardreader PCIe Gen1 1x SATA Gen3 port 0 5V 6GHz(600MB/s)
RTS5229 1.5V 5GT/s
PCIe port4 page 16,17,18,19,20,21,22,23,24
page 29 SATA port 2 SATA ODD SATA HDD
3 5V 3GHz(300MB/s) SATA port 2 SATA port 0 3
page 23 page 23
PCIe Gen2 2x
1.5V 5GT/s
LPC BUS HD Audio
3.3V 33 MHz 3.3V 24MHz
USB3.0 Right-side USB3.0 Left-side
HDA Codec UPD720202 UPD720202
PCIe port5 PCIe port6
ALC280 page 31 page 32
SPI ROM Debug Port ENE KB930/KB9012 page 33
page 36 page 35
(4MB + 2MB)
page 16
RTC CKT.
page 16
SPK Conn JPIO
page 34
(HP & MIC)
page 34
DC/DC Interface CKT. Touch Pad Int.KBD EC ROM CIR G-Sensor
page 38 page 37 page 36 page 35 page 36
(128KB) 36
page
4 4

Power Circuit DC/DC EC SMBus
page 39,40,41,42,43,
44,45,46,47,48,49 Finger Printer/B
page 26 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

Power On/Off CKT. Power/B THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
page 37 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
page 37 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS QCLA4,5 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Thursday, February 16, 2012 Sheet 2 of 48
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5 4 3 2 1



DESIGN CURRENT 0.1A +3VL
DESIGN CURRENT 0.1A +5VL
B+
Ipeak=10.63A, Imax=7.44A, Iocp min=12.3A DESIGN CURRENT 11A +5VALW
SUSP#

DESIGN CURRENT 1.8A +1.8VS
SY8033BDBC
SUSP

D D
N-CHANNEL DESIGN CURRENT 6.5A +5VS
SI4800 BCPWON
DESIGN CURRENT 0.1A +5VS_L_BCAS
P-CHANNEL
AO-3413
KB_LED

TPS51125 DESIGN CURRENT 0.4A +5VS_LED
P-CHANNEL
AO-3413
+5VS
DESIGN CURRENT 0.3A +3VS_HDP
LDO
G9191
ODD_EN#
DESIGN CURRENT 1.6A +5VS_ODD
P-CHANNEL
AO-3413
SYSON

Ipeak=6A, Imax=4.2A, Iocp min=8A DESIGN CURRENT 13.5A +1.5V
SY8036 SUSP

N-CHANNEL DESIGN CURRENT 5A +1.5V_CPU
FDS6676AS
SUSP
C C
N-CHANNEL DESIGN CURRENT 1.5A +1.5VS
FDS6676AS


0.75VR_EN#

DESIGN CURRENT 1A +0.75VS
VCCPPWRGD
G2992

Ipeak=6A, Imax=4.A, Iocp min=8 DESIGN CURRENT 6A +VCCSA
SY8037

LNB EN

Imax=0.3A, Iocp min=0.8A DESIGN CURRENT 0.3A +16VS
APW7137

Ipeak=5A, Imax=3.5A, Iocp min=6.2A DESIGN CURRENT 7.5A +3VALW
WOL_EN

P-CHANNEL DESIGN CURRENT 0.1A +3V_LAN
SUSP AO-3413

N-CHANNEL DESIGN CURRENT 6A +3VS
B B
SI4800 UMA_ENVDD

P-CHANNEL DESIGN CURRENT 2A +LCD_VDD
AO-3415


FELICA_PWR
DESIGN CURRENT 0.1A +FLICA_VCC
P-CHANNEL
AO-3413
VR_ON

DESIGN CURRENT 94A +CPU_CORE
NCP6132A DESIGN CURRENT 50A +GFX_CORE

SUSP#

Ipeak=14A, Imax=9.8A, Iocp min=16.92A DESIGN CURRENT 15A +1.05VS_VCCP
TPS51212




A A




Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Tree
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QFKAA
Date: Thursday, February 16, 2012 Sheet 3 of 48
5 4 3 2 1
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( O MEANS ON X MEANS OFF )
Voltage Rails
+5VS
+RTCVCC B+ +5VL +5VALW +1.5V
+3VS
+3VL +3VALW
+1.8VS
+VSB
power +1.5VS
1 plane +1.05VS
1


+0.75VS BTO Option Table
+CPU_CORE
+VGA_CORE Function HDMI Camera & Mic TPM MINI PCI-E SLOT
+GFX_CORE
description HDMI Camera & Mic TPM Half Card
+VTT
State
+VRAM_1.5VS explain HDMI Digital MIC Analog MIC SLB 9635 SLB 9655 WIMAX
+3VS_DGPU
BTO [email protected] [email protected] [email protected] [email protected] [email protected] [email protected]
+1.05VS_DGPU



Function SPI ROM Green CLK USB 3.0 Sleep & Charge LAN
S0
O O O O O O description SPI ROM Green CLK USB 3.0 Sleep & Charge LAN

S1 explain WIN8 Green CLK NOGCLK Internal 10/100M Giga
O O O O O O
2 BTO [email protected] [email protected] [email protected] [email protected] [email protected] [email protected] 2
S3
O O O O O X
S5 S4/AC
O O O O X X
S5 S4/ Battery only
O O O X X X
S5 S4/AC & Battery
don't exist
O X X X X X


PCH SM Bus Address

Power Device HEX Address
+3VS DDR SO-DIMM 0 A0 H 1010 0000 b
3
+3VS DDR SO-DIMM 1 A4 H 1010 0100 b 3
+3VS Clock Generator D2 H 1101 0010 b
+3VS New Card
+3VS WLAN/WIMAX
+3VS Clock Generator
+3VS 3G


SIGNAL
STATE SLP_S3# SLP_S4# SLP_S5#
EC SM Bus1 Address EC SM Bus2 Address
Full ON HIGH HIGH HIGH

Power Device HEX Address Power Device HEX Address S1(Power On Suspend) HIGH HIGH HIGH

+3VL Smart Battery 16 H 0001 0110 b +3VS PCH 96 H 1001 0110 b S3 (Suspend to RAM) LOW HIGH HIGH
+3VL HDMI-CEC 34 H 0011 0100 b +3VS NVIDIA GPU 9A H 1001 1010 b
S4 (Suspend to Disk) LOW LOW HIGH
+3VS G-Sensor 40 H 0100 0000 b
+3VS Light Sensor 52 H 0101 0010 b S5 (Soft OFF) LOW LOW LOW
4 Power Device HEX Address 4

G3 LOW LOW LOW
+3VL Cap. Sensor Virtual I2C


Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/09/03 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
QFKAA
Date: Thursday, February 16, 2012 Sheet 4 of 48
A B C D E
5 4 3 2 1




JCPUB

100 MHz
@ A28 CLK_CPU_DMI Stuff RC157 and RC158 if do not support eDP
BCLK CLK_CPU_DMI 17
1000P_0402_50V7K 2 1 CC63 PM_DRAM_PWRGD_R H_SNB_IVB# C26 A27 CLK_CPU_DMI#




MISC

CLOCKS
11,21 H_SNB_IVB# PROC_SELECT# BCLK# CLK_CPU_DMI# 17
@ 120 MHz +1.05VS_VCCP
1000P_0402_50V7K 2 1 CC62 H_PWRGOOD_R T1 PAD TP_SKTOCC# AN34
SKTOCC# A16 CLK_CPU_EDP
DPLL_REF_CLK A15 CLK_CPU_EDP# CLK_CPU_EDP# 1 2
DPLL_REF_CLK# RC157 1K_0402_5%
D CLK_CPU_EDP 1 2 D
T2 PAD H_CATERR# AL33 RC158 1K_0402_5%
CATERR#




THERMAL
+1.05VS_VCCP H_PECI AN33 R8 H_DRAMRST#
31 H_PECI PECI SM_DRAMRST# H_DRAMRST# 7




DDR3
MISC
RC44 2 1 62_0402_5% H_PROCHOT# RC159
1 2 H_PROCHOT#_R AL32 AK1 SM_RCOMP_0 RC56 2 1 140_0402_1% DDR3 Compensation Signals
31 H_PROCHOT# PROCHOT# SM_RCOMP[0]
56_0402_5% A5 SM_RCOMP_1 RC59 2 1 25.5_0402_1% Layout Note:Place these
SM_RCOMP[1] A4 SM_RCOMP_2 RC61 2 1 200_0402_1%
RC45 2 1 10K_0402_5% H_PWRGOOD SM_RCOMP[2] resistors near Processor
H_THERMTRIP# AN32
21 H_THERMTRIP# THERMTRIP# @
H_DRAMRST# 1 2
CC34 180P_0402_50V8J

AP29
PRDY# AP27
PREQ# by ESD requestion and place near CPU
@
1000P_0402_50V7K 2 1 CC70 H_PECI AR26 XDP_TCK_R PAD T4
TCK AR27 XDP_TMS_R PAD T5
TMS




PWR MANAGEMENT
@ H_PM_SYNC AM34 AP30 2 1




JTAG & BPM
18 H_PM_SYNC XDP_TRST#_R
1000P_0402_50V7K 2 1 CC71 H_PM_SYNC PM_SYNC TRST# RC55 51_0402_5%
AR28 XDP_TDI_R PAD T6
@ RC187 TDI AP26 XDP_TDO_R PAD T7
1000P_0402_50V7K 2 1 CC66 BUF_CPU_RST# 1 2 H_PWRGOOD_R AP33 TDO
21 H_PWRGOOD UNCOREPWRGOOD
0_0402_5%
Layout request for test point
AL35
PM_SYS_PWRGD_BUF 1 2 PM_DRAM_PWRGD_R V8 DBR#
Please place near JCPU RC58 130_0402_5% SM_DRAMPWROK
C AT28 C
BPM#[0] AR29
BPM#[1] AR30
BUF_CPU_RST# AR33 BPM#[2] AT30
RESET# BPM#[3] AP32
BPM#[4] AR31
BPM#[5] AT31
BPM#[6] AR32
+3VALW_PCH BPM#[7]
+3VALW_PCH
2 1 DRAMPWROK +1.5V_CPU
RC11 200_0402_5%
2 1 TYCO_2013620-2_IVY BRIDGE
1




10K_0402_5% 0.1U_0402_10V7K @
+3VS 2 RC13 1 CC33 RC14
UC1 200_0402_5%
5




74AHC1G09GW_TSSOP5
2




1 2 1
P




18,31 PM_PWROK
RC12 @ 0_0402_5% B 4 PM_SYS_PWRGD_BUF
2 O
18 DRAMPWROK A
G




1
3




RC25
39_0402_5%
@
1
RC181 @ 2 0_0402_5%
1 2




D QC2
9,34 SUSP SUSP 2 2N7002_SOT23
G @
S
3




B B




FAN Control Circuit

Buffered Reset to CPU
+5VS JFAN @
1A +FAN2 1
2 1
+3VS @ 3 2
2 3




1
C15
C13 4
10U_0805_6.3V6M 1000P_0402_50V7K 5 GND




2
1 GND
1 0.1U_0402_10V7K U1
CC36 1 8 ACES_85204-0300N
+1.05VS_VCCP 2 EN GND 7
PLT_RST# 20,26,27,28,31,32 VIN GND
+FAN2 3 6 R24 10K_0402_5%
2