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A B C D E
1 1
Compal Confidential
2 2
QALEA/QALEB Schematics Document
AMD APU Trinity FS1r2 + FCH Hudson-M3 + GPU Seymour XTX/Thames XT
2012-01-16
3
REV:0.4 3
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/04/18 Deciphered Date 2015/07/08 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Cover Page
Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-8124P 1 of
Monday, January 16, 2012 Sheet 50
A B C D E
A B C D E
Compal confidential
File Name : QALEA/QALEB
Themes XT M2/Seymour XTX M2
1
VRAM PCIE x 16 Gen2 1
64M16/128M16/256M16 Memory BUS(DDRIII) 204pin DDRIII-SO-DIMM X2
DDR3 x 8 AMD FS1r2 APU Dual Channel
Page 1724 BANK 0, 1, 2
Page 1011
1.5V DDRIII 1600 (1866)
DP Port0 Trinity
LVDS uPGA 722 pin
translator DP Port2 35mm x 35mm
RTD2132S HDMI Conn.
Page 27
Page 25 DP Port1
Page 59
4 * x1 PCI-E 2.0 x4 UMI Gen. 1
LVDS Conn. 2.5GT/s per lane
Page 26 GPP3 GPP1 GPP0 2Channel Speaker
CardReader LAN
RTL 8111F
2 4 in 1 Conn. IC AZALIA Audio Codec Internal MIC 2
RTS5229 Hudson M3 CX20671-21Z
Page 29
uFCBGA-656 Audio Jacks
PCI Express USB(BT) 24.5mm x 24.5mm 14*USB2.0/
Combo jack
Mini card Slot 1 PCI-E(WLAN) 4*USB3.0,10*USB2.0
WLAN
FCH CRT (VGA DAC)
CMOS Camera Page 26
Page 33
CRT CONN
Page 28
Page 1216
6*SATA serial BlueTooth CONN Page 32
USB PORT 3.0 x3 Page 34
SPI ROM LPC BUS USB PORT 2.0 x1 +Charger
4MB
Sub board WLAN Page 33
3
Page 35 Page 13
EC 3
ENE KB9012
Page 31 Finger Printer
Power Board 15" only G Sensor UPEK TCS5DA6C0
ST LIS34ALTR
Page 30
SATA0
ODD board SATA3.0 HDD CONN
LAN Track Point
Page 30
SATA1
Page 33 SATA ODD CONN
Int.KBD Page 30
Audio Jack+ Click Pad
Page 33
USB2.0 Page 33
FingerPrint Thermal Sensor
4 Fintek 5303 4
Page 32
Card reader Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/04/18 Deciphered Date 2015/07/08 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Block Diagrams
Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-8124P 2 of
Monday, January 16, 2012 Sheet 50
A B C D E
A B C D E
Voltage Rails
FCH Hudson-M2/3 Comal FCH Hudson-M2/3
Power Plane Description S0 S3 S5
SATA Port List PCIE Port List USB Port List
VIN Adapter power supply (19V) N/A N/A N/A
B+ AC or battery power rail for power circuit. N/A N/A N/A
USB1.1
SATA0 HDD PCIE0 LAN
+APU_CORE Core voltage for APU ON OFF OFF Port0 NC
SATA1 ODD PCIE1 WLAN
APU
+APU_CORE_NB Voltage for On-die VGA of APU ON OFF OFF
1
+1.5V 1.5V power rail for APU VDDIO and DDR ON ON OFF
Port1 NC 1
SATA2 NC PCIE2 NC
+0.75VS 0.75V switched power rail for DDR terminator ON OFF OFF USB2.0
+1.2VS 1.2V (VDDR, VDDP) switched power rail for APU ON OFF OFF
SATA3 NC PCIE3 Card Reader
+2.5VS 2.5V for APU VDDA ON OFF OFF
Port0 USB2.0 Port
SATA4 NC PCIE0 NC
+1.1VALW 1.1V switched power rail for FCH ON ON ON* Port1 NC
SATA5 NC PCIE1 NC
FCH
+1.1VS 1.1V switched power rail for FCH ON OFF OFF
+1.5VS 1.5V switched power rail ON OFF OFF
Port2 NC
PCIE2 NC
+VGA_CORE 0.95-1.2V switched power rail ON OFF OFF Port3 NC
+1.5VGS 1.5V switched power rail ON OFF OFF
PCIE3 NC
+1.8VGS 1.8V switched power rail ON OFF OFF
Port4 NC
+1.0VGS 1.0V switched power rail for VGA ON OFF OFF Port5 WLAN
+3VALW 3.3V always on power rail ON ON ON*
+3VS_WLAN 3.3V power rail for WLAN ON OFF OFF
Port6 CMOS
+3VS 3.3V switched power rail ON OFF OFF Port7 FP
+5VALW 5V always on power rail ON ON ON*
+5VS 5V switched power rail ON OFF OFF
Port8 BT
2 2
+VSB VSB always on power rail ON ON ON* Port9 NC
+RTCVCC RTC power ON ON ON
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Port10 USB 3.0
Port11 USB 3.0
Port12 USB 3.0
EC SM Bus1 address EC SM Bus2 address BOM Structure Port13 NC
Device Address HEX Device Address HEX
UMA@ : UMA only
DIS@ : DIS muxluss
Smart Battery 0001-011xb 15H F75303 (DDR,VRAM,CPUCORE)1001-101xb 9AH
PX40@ : PX4.0 Support
SB-TSI 1001-100xb 98H
PX50@ : PX5.0 Support
Seymour XTX 1000-0010b 82H CMOS@ : USB camera
LVDS translator
CONN@ : ME components
X76@, H2G@, S2G@ : VRAM
3 3
Tha@: Thames VGA
Sey@: Seymour VGA
BOM option and stencil
SDV:
CMOS@/DIS@/PX40@/SEY@ + X76@
FCH SMB0 (FCH_SMB0)
Device Address HEX PJ201,PJ401,PJ502,PJ503,PJ504,PJ601,PJ603,PJ604,
PJ701,PJ702,PJ703,PJ704,J1,J2301,J2401,J2402,J2403
DDR DIMM1 (FCH_SMB0) 1001-000xb 90 PJ402,PJ403,PJ501,PJ602,PJ801,PJ802,PJ803,PJ804,PJ805
DDR DIMM2 (FCH_SMB0) 1001-001xb 92
WLAN (FCH_SMB0)
Security ROM
Stencil Memo
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/04/18 Deciphered Date 2015/07/08 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Notes List
Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-8124P 3 of
Monday, January 16, 2012 Sheet 50
A B C D E
5 4 3 2 1
Without BACO option :
Power-Up/Down Sequence PE_GPIO0 : Low -> Reset dGPU ; High ->Normal operation
PE_GPIO1 : Low -> dGPU Power OFF ; High -> dGPU Power ON
All the ASIC supplies, except for VDDR3, must fully reach their respective
nominal voltages within 20 ms of the start of the ramp-up sequence, though a BACO option :
shorter ramp-up duration is preferred. There is no timing requirement on the PE_GPIO0 : High ->Normal operation (dGPU is not reset on BACO mode)
PE_GPIO1 : Low -> dGPU Power OFF ; High -> dGPU Power ON (always High)
ramp up of VDDR3 relative to other power rails.
D
The external pull-up resistors on the DDC/AUX signals (if applicable) should dGPU Power Pins Voltage PX 3.0 BACO Mode Max current
D
ramp up before or after both VDDC and VDD_CT have ramped up. PCIE_PVDD, PCIE_VDDR, TSVDD, VDDR4, VDD_CT, 1.8V OFF ON 1679mA
VDDC and VDD_CT should not ramp up simultaneously. For example, VDDC DPE_PVDD, DP[F:E]_VDD18, DP[D:A]_PVDD,
should reach 90% before VDD_CT starts to ramp up (or vice versa). DP[D:A]_VDD18, AVDD, VDD1DI, A2VDDQ, VDD2DI,
For power down, reversing the ramp-up sequence is recommended. DPLL_PVDD, MPV18, and SPV18
DP[F:E]_VDD10, DP[D:A]_VDD10, DPLL_VDDC, and 1.0V OFF ON 775mA
SPV10
PCIE_VDDC 1.0V OFF ON 1.1A
VDDR3(3.3VGS) VDDR3 3.3V OFF ON 60mA
BIF_VDDC (current consumption = [email protected], in Same as OFF ON 70mA
VDDC Same as
PCIE_VDDC(1.0V) BACO mode) PCIE_VDDC
VDDR1 1.5V OFF OFF 1.2A
VDDC/VDDCI TBD OFF OFF 28
C
VDDR1(1.5VGS) C
VDDC/VDDCI(1.12V)
VDD_CT(1.8V) PE_GPIO0(PXS_RST#) PE_EN BACO Switch
iGPU dGPU
PERSTb BIF_VDDC
PE_GPIO1(PXS_PWREN)
REFCLK PX_mode
B +3.3VALW MOS
+3.3VGS B
Straps Reset 1
+1.5V SI4800
+1.5VGS
+1.5V +1.0VGS
Straps Valid LDO 3
2
Global ASIC Reset
+B Regulator
+VGA_CORE
+5VLAW +1.8VGS
T4+16clock
Regulator
5 4
PWRGOOD
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/04/18 Deciphered Date 2015/07/08 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
dGPU Block Diagram
Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-8124P 4 of 50
Monday, January 16, 2012 Sheet
5 4 3 2 1
A B C D E
17 PCIE_CRX_GTX_P[0..15] PCIE_CTX_GRX_P[0..15] 17
17 PCIE_CRX_GTX_N[0..15] PCIE_CTX_GRX_N[0..15] 17
JCPU1A
PCI EXPRESS
PCIE_CRX_GTX_P0 AB8 AB2 PCIE_CTX_C_GRX_P0 C1 DIS@ 1 2 .1U_0402_16V7K PCIE_CTX_GRX_P0
PCIE_CRX_GTX_N0 AB7 P_GFX_RXP0 P_GFX_TXP0 AB1 PCIE_CTX_C_GRX_N0 C2 DIS@ 1 2 .1U_0402_16V7K PCIE_CTX_GRX_N0
PCIE_CRX_GTX_P1 AA9 P_GFX_RXN0 P_GFX_TXN0 AA3 PCIE_CTX_C_GRX_P1 C3 DIS@ 1 2 .1U_0402_16V7K PCIE_CTX_GRX_P1
PCIE_CRX_GTX_N1 AA8 P_GFX_RXP1 P_GFX_TXP1 AA2 PCIE_CTX_C_GRX_N1 C4 DIS@ 1 2 .1U_0402_16V7K PCIE_CTX_GRX_N1
PCIE_CRX_GTX_P2 AA5 P_GFX_RXN1 P_GFX_TXN1 Y5 PCIE_CTX_C_GRX_P2 C5 DIS@ 1 2 .1U_0402_16V7K PCIE_CTX_GRX_P2
1 PCIE_CRX_GTX_N2 AA6 P_GFX_RXP2 P_GFX_TXP2 Y4 PCIE_CTX_C_GRX_N2 C6 DIS@ 1 2 .1U_0402_16V7K PCIE_CTX_GRX_N2 1
PCIE_CRX_GTX_P3 Y8 P_GFX_RXN2 P_GFX_TXN2 Y2 PCIE_CTX_C_GRX_P3 C7 DIS@ 1 2 .1U_0402_16V7K PCIE_CTX_GRX_P3
PCIE_CRX_GTX_N3 Y7 P_GFX_RXP3 P_GFX_TXP3 Y1 PCIE_CTX_C_GRX_N3 C8 DIS@ 1 2 .1U_0402_16V7K PCIE_CTX_GRX_N3
PCIE_CRX_GTX_P4 W9 P_GFX_RXN3 P_GFX_TXN3 W3 PCIE_CTX_C_GRX_P4 C9 DIS@ 1 2 .1U_0402_16V7K PCIE_CTX_GRX_P4
PCIE_CRX_GTX_N4 W8 P_GFX_RXP4 P_GFX_TXP4 W2 PCIE_CTX_C_GRX_N4 C10 DIS@ 1 2 .1U_0402_16V7K PCIE_CTX_GRX_N4
PCIE_CRX_GTX_P5 W5 P_GFX_RXN4 P_GFX_TXN4 V5 PCIE_CTX_C_GRX_P5 C11 DIS@ 1 2 .1U_0402_16V7K PCIE_CTX_GRX_P5
PCIE_CRX_GTX_N5 W6 P_GFX_RXP5 P_GFX_TXP5 V4 PCIE_CTX_C_GRX_N5 C12 DIS@ 1 2 .1U_0402_16V7K PCIE_CTX_GRX_N5
PCIE_CRX_GTX_P6 V8 P_GFX_RXN5 P_GFX_TXN5 V2 PCIE_CTX_C_GRX_P6 C13 DIS@ 1 2 .1U_0402_16V7K PCIE_CTX_GRX_P6
PCIE_CRX_GTX_N6 V7 P_GFX_RXP6 P_GFX_TXP6 V1 PCIE_CTX_C_GRX_N6 C14 DIS@ 1 2 .1U_0402_16V7K PCIE_CTX_GRX_N6
GRAPHICS
PCIE_CRX_GTX_P7 U9 P_GFX_RXN6 P_GFX_TXN6 U3 PCIE_CTX_C_GRX_P7 C15 DIS@ 1 2 .1U_0402_16V7K PCIE_CTX_GRX_P7
PCIE_CRX_GTX_N7 U8 P_GFX_RXP7 P_GFX_TXP7 U2 PCIE_CTX_C_GRX_N7 C16 DIS@ 1 2 .1U_0402_16V7K PCIE_CTX_GRX_N7
PCIE_CRX_GTX_P8 U5 P_GFX_RXN7 P_GFX_TXN7 T5 PCIE_CTX_C_GRX_P8 C17 DIS@ 1 2 .1U_0402_16V7K PCIE_CTX_GRX_P8
PCIE_CRX_GTX_N8 U6 P_GFX_RXP8 P_GFX_TXP8 T4 PCIE_CTX_C_GRX_N8 C18 DIS@ 1 2 .1U_0402_16V7K PCIE_CTX_GRX_N8
PCIE_CRX_GTX_P9 T8 P_GFX_RXN8 P_GFX_TXN8 T2 PCIE_CTX_C_GRX_P9 C19 DIS@ 1 2 .1U_0402_16V7K PCIE_CTX_GRX_P9
PCIE_CRX_GTX_N9 T7 P_GFX_RXP9 P_GFX_TXP9 T1 PCIE_CTX_C_GRX_N9 C20 DIS@ 1 2 .1U_0402_16V7K PCIE_CTX_GRX_N9
PCIE_CRX_GTX_P10 R9 P_GFX_RXN9 P_GFX_TXN9 R3 PCIE_CTX_C_GRX_P10 C21 DIS@ 1 2 .1U_0402_16V7K PCIE_CTX_GRX_P10
PCIE_CRX_GTX_N10 R8 P_GFX_RXP10 P_GFX_TXP10 R2 PCIE_CTX_C_GRX_N10 C22 DIS@ 1 2 .1U_0402_16V7K PCIE_CTX_GRX_N10
PCIE_CRX_GTX_P11 R5 P_GFX_RXN10 P_GFX_TXN10 P5 PCIE_CTX_C_GRX_P11 C23 DIS@ 1 2 .1U_0402_16V7K PCIE_CTX_GRX_P11
PCIE_CRX_GTX_N11 R6 P_GFX_RXP11 P_GFX_TXP11 P4 PCIE_CTX_C_GRX_N11 C24 DIS@ 1 2 .1U_0402_16V7K PCIE_CTX_GRX_N11
PCIE_CRX_GTX_P12 P8 P_GFX_RXN11 P_GFX_TXN11 P2 PCIE_CTX_C_GRX_P12 C25 DIS@ 1 2 .1U_0402_16V7K PCIE_CTX_GRX_P12
PCIE_CRX_GTX_N12 P7 P_GFX_RXP12 P_GFX_TXP12 P1 PCIE_CTX_C_GRX_N12 C26 DIS@ 1 2 .1U_0402_16V7K PCIE_CTX_GRX_N12
PCIE_CRX_GTX_P13 N9 P_GFX_RXN12 P_GFX_TXN12 N3 PCIE_CTX_C_GRX_P13 C27 DIS@ 1 2 .1U_0402_16V7K PCIE_CTX_GRX_P13
PCIE_CRX_GTX_N13 N8 P_GFX_RXP13 P_GFX_TXP13 N2 PCIE_CTX_C_GRX_N13 C28 DIS@ 1 2 .1U_0402_16V7K PCIE_CTX_GRX_N13
PCIE_CRX_GTX_P14 N5 P_GFX_RXN13 P_GFX_TXN13 M5 PCIE_CTX_C_GRX_P14 C29 DIS@ 1 2 .1U_0402_16V7K PCIE_CTX_GRX_P14
PCIE_CRX_GTX_N14 N6 P_GFX_RXP14 P_GFX_TXP14 M4 PCIE_CTX_C_GRX_N14 C30 DIS@ 1 2 .1U_0402_16V7K PCIE_CTX_GRX_N14
PCIE_CRX_GTX_P15 M8 P_GFX_RXN14 P_GFX_TXN14 M2 PCIE_CTX_C_GRX_P15 C31 DIS@ 1 2 .1U_0402_16V7K PCIE_CTX_GRX_P15
PCIE_CRX_GTX_N15 M7 P_GFX_RXP15 P_GFX_TXP15 M1 PCIE_CTX_C_GRX_N15 C32 DIS@ 1 2 .1U_0402_16V7K PCIE_CTX_GRX_N15
P_GFX_RXN15 P_GFX_TXN15
AE5 AD5 PCIE_CTX_C_DRX_P0 C33 1 2 .1U_0402_16V7K
35 PCIE_CRX_DTX_P0 P_GPP_RXP0 P_GPP_TXP0 PCIE_CTX_DRX_P0 35
AE6 AD4 PCIE_CTX_C_DRX_N0 C34 1 2 .1U_0402_16V7K
LAN 35 PCIE_CRX_DTX_N0 AD8 P_GPP_RXN0 P_GPP_TXN0 AD2 PCIE_CTX_C_DRX_P1 C123 1 2 .1U_0402_16V7K
PCIE_CTX_DRX_N0 35
33 PCIE_CRX_DTX_P1 P_GPP_RXP1 P_GPP_TXP1 PCIE_CTX_DRX_P1 33
AD7 AD1 PCIE_CTX_C_DRX_N1 C124 1 2 .1U_0402_16V7K
2 WLAN 33 PCIE_CRX_DTX_N1
AC9 P_GPP_RXN1 P_GPP_TXN1 AC3
PCIE_CTX_DRX_N1 33 2
P_GPP_RXP2 P_GPP_TXP2
GPP
AC8 AC2
AC5 P_GPP_RXN2 P_GPP_TXN2 AB5 PCIE_CTX_C_DRX_P3 C35 1 2 .1U_0402_16V7K
35 PCIE_CRX_DTX_P3 AC6 P_GPP_RXP3 P_GPP_TXP3 AB4 1 2 .1U_0402_16V7K PCIE_CTX_DRX_P3 35
PCIE_CTX_C_DRX_N3 C36
Card Reader 35 PCIE_CRX_DTX_N3 P_GPP_RXN3 P_GPP_TXN3 PCIE_CTX_DRX_N3 35
AG8 AG2 UMI_TXP0_C C37 1 2 .1U_0402_16V7K
12 UMI_RXP0 P_UMI_RXP0 P_UMI_TXP0 UMI_TXP0 12
AG9 AG3 UMI_TXN0_C C38 1 2 .1U_0402_16V7K
12 UMI_RXN0 P_UMI_RXN0 P_UMI_TXN0 UMI_TXN0 12
AG6 AF4 UMI_TXP1_C C39 1 2 .1U_0402_16V7K
12 UMI_RXP1 AG5 P_UMI_RXP1 P_UMI_TXP1 AF5 1 2 UMI_TXP1 12
UMI_TXN1_C C40 .1U_0402_16V7K
12 UMI_RXN1 P_UMI_RXN1 P_UMI_TXN1 UMI_TXN1 12
AF7 AF1 UMI_TXP2_C C41 1 2 .1U_0402_16V7K
12 UMI_RXP2 P_UMI_RXP2 P_UMI_TXP2 UMI_TXP2 12
AF8 AF2 UMI_TXN2_C C42 1 2 .1U_0402_16V7K
12 UMI_RXN2 P_UMI_RXN2 P_UMI_TXN2 UMI_TXN2 12
AE8 AE2 UMI_TXP3_C C43 1 2 .1U_0402_16V7K
UMI
12 UMI_RXP3 P_UMI_RXP3 P_UMI_TXP3 UMI_TXP3 12
AE9 AE3 UMI_TXN3_C C44 1 2 .1U_0402_16V7K
12 UMI_RXN3 P_UMI_RXN3 P_UMI_TXN3 UMI_TXN3 12
+1.2VS 1 2 P_ZVDDP AG11 AH11 P_ZVSS 1 2
R1 196_0402_1% P_ZVDDP P_ZVSS R2 196_0402_1%
LOTES_ACA-ZIF-109-P12-A_FS1R2
CONN@
3 3
Power Sequence of APU
+1.5V
+2.5VS Group A
+1.5VS
+APU_CORE
Group B
4 +APU_CORE_NB 4
+1.2VS
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/04/18 Deciphered Date 2015/07/08 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
FS1r2 PCIE/UMI
Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.4
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
LA-8121P 5 of