Text preview for : Quanta_ZY9.PDF part of Quanta Quanta ZY9 Quanta Quanta_ZY9.PDF
Back to : Quanta_ZY9.PDF | Home
5 4 3 2 1
31ZY9MB0000
ZY9 MB ASSY(DC/GM/MXM)ASSY W/O CPU
31ZY9MB0010
ZY9 SYSTEM BLOCK DIAGRAM +1.05V
UP61111AQDD P36
CHARGER
ISL88731 P31
ZY9 MB ASSY(QC/GM/MXM)ASSY W/O CPU
X'TAL DDR PWR 3/5V SYS PWR
14.318MHz TPS5116 P37 ISL6237 P32
Fan Driver
D
CLOCK GENERATOR (PWM Type) THERMAL CPU CORE PWR D
P29 PROTECTION P42 ISL62882 P33
SELGO: SLG8SP585V
intel
P3
1.8VPWR VAXG
Auburndale (UMA+VGA) DISCHARGER P38 ISL62881 P34
Clarksfield (VGA)
DDR SYSTEM MEMORY
DDR III Dual Channel DDR3 POWER TREE +VTT
SO-DIMM 0 P39 UP61111AQDD P35
SO-DIMM 1 800/ 1066 MHz
P14, 15 rPGA 989 DISPLAY PORT
PCI-E
HDMI DISPLAY PORT
P19
P4.5.6.7 PCIE
X16 MXM 3.0 CRT
FDI DMI LVDS
P17 HDMI P19
X4 DMI interface
C C
FDI DMI CRT
Graphics Interfaces
LVDS & CRT P18
Switch
P18 LVDS P18
HDD (SATA) *2
intel
P22 SATA0
SATA
USB7
SATA3
eSATA Conn. eSATA Buffer SATA1
(TI SN75LVCP412) P28 ODD (SATA) PCI-E
PCI-Express PCIE-2 New Card
USB 10 P28 Ibex Peak_M X1 USB 7 P25
P22
SATA2
USB Port x 4 PCIE-4&6 Mini Card
USB 0,6, 11, 12 P28
USB 2.0
PCH RTC
X'TAL 32.768KHz WLAN / TV
B USB P9 B
USB 12 & 13 P21
Bluetooth Azalia IHDA
PCIE-1 PCIE-3 X'TAL
USB 4 P29
P8.9.10.11.12.13
25MHz
USB12 & 13
SPI LPC
CCD IEEE1394 & Broadcom
USB 9 P29 Giga-LAN
X'TAL
32.768KHz
Media Cardreader
JMB380-QGAZ0B (BCM5784)
FingerPrint Audio CODEC EC (WPC775C) P26 P20
USB 2 P29 (ALC889X) P23 SPI ROM
P9
P30
NVRAM
IEEE1394a Card Reader Transformer P20
connector Connector
P26 P26
SPI ROM
P30
RJ45 P20
A A
Front Stereo Amp Center Mono Amp Rear Audio Amp Sub-Amplifier
(G1453L/ 2W+2W) (G1442/ 2W) & Head phone (MAX9737) Touch Pad MMB SSID: 019F and 019E
P24 P23 AN12947A P23,P24 P24 P29 P27 SVID: 1025
Quanta Computer Inc.
Front Speaker Center Speaker Speaker S/PDIF SUBWOOFER Line in MIC Jack Int. D-MIC PROJECT : ZY9
K/B COON. CIR Size Document Number Rev
P24 P24 P24 P24 P24 P24 P24 P18, P24 P29 P30 3A
ZY9 Block Diagram
Date: Tuesday, August 18, 2009 Sheet 1 of 42
5 4 3 2 1
1 2 3 4 5 6 7 8
Table of Contents Power States
CONTROL
PAGE DESCRIPTION POWER PLANE VOLTAGE DESCRIPTION ACTIVE IN
SIGNAL
1 Schematic Block Diagram
2 Front Page VIN +10V~+19V MAIN POWER S0~S5
3 Clock Generator (SLG8SP585V)
+RTC_CELL +3V~+3.3V RTC S0~S5
4-7 CPU (Clarksfield)
A 8-13 PCH (Ibex Peak-M) +3VPCU +3.3V 8051 POWER ALWON S0~S5 A
14-15 DDRIII SO-DIMM
+5VPCU +5V CHARGE POWER ALWON S0~S5
16 BRAIDWOOD
17 MXM3.0 +15V +15V LARGE POWER +15V_ALWP S0~S5
18 CRT/LVDS Conn
3V_LAN_S5 +3.3V LAN POWER AUX_ON
19 HDMI / Display port
20 LAN (BCM5784M) +5VSUS +5V SUSD
21 MINI PCIE
+3VSUS +3.3V SUSD
22 SATA HDD/ODD
23-24 Audio CODEC(ALC889X) /Phone Jack +1.5VSUS +1.5V SODIMM POWER SUSON
25 NEW CARD
+0.75V_DDR_VTT +0.9V SODIMM POWER MAINON
26 Card Reader (JMB380) / 1394
27 MMB /LED +5V +5V MAIND
28 USB / E-SATA
+3V +3.3V MAIND
29 KB / FAN /TP /CCD /BT
B 30 EC /FLASH /CIR +1.8V +1.8V MAINON B
31 Charger (ISL88731)
+1.5V +1.5V PCH POWER MAIND
32 5V /3V (ISL6237)
33 CPU Core (ISL62882) +1.1V_VTT +1.05V~+1.1V CPU POWER MAINON
34 +VTT (UP6111AQDD)
+1.05V +1.05V PCH POWER MAINON
35 +1.05V (UP6111AQDD)
36 DDR 1.5V (TPS51116) +VCC_CORE 0V~+1.5V CPU CORE POWER VRON
37 Discharge /1.8V
LCDVCC +3.3V LCD Power LVDS_VDDEN
38 POWER TREE TABLE
39 PCH POWER PLANE MBAT+ +10V~+17V MAIN BATTERY
40 POWER Management
+5V_S5 +5V S5_ON
41 Thermal protection
42 change list +3V_S5 +3.3V S5D
C C
GND PLANE PAGE DESCRIPTION
LANGND 20
E775AGND 30
ADOGND 23.24
GND ALL
D D
Quanta Computer Inc.
PROJECT : ZY9
Size Document Number Rev
3A
Index & Power Status
Date: Tuesday, August 18, 2009 Sheet 2 of 42
1 2 3 4 5 6 7 8
5 4 3 2 1
+VDDIO_CLK
U21 +3V
+3V 150mA(20mil) +VDDIO_CLK
BKP1608HS181T_6_1.5A +1.05V L29 *BLM18AG601SN1D_6
+3V_CLK 1 15 80mA(20mil)
VDD_DOT VDD_SRC_I/O L30 BLM18AG601SN1D_6 C300 C305 C301 C308
5 VDD_27 VDD_CPU_I/O 18
D L28 C303 C293 C297 C299 C298 C285 C302 17 D
VDD_SRC CLK_BUF_DREFCLK_R .1u/16V_4 .1u/16V_4 10u/Y5V_8 10u/Y5V_8
24 VDD_CPU DOT_96 3
4.7U/10V_8
4.7U/10V_8
.1u/16V_4.1u/16V_4.1u/16V_4.1u/16V_4 .1u/16V_4 29 4 CLK_BUF_DREFCLK#_R
VDD_REF DOT_96#
27M 6 TP54
XTAL_OUT 27 7
XTAL_OUT 27M_SS TP56
XTAL_IN 28 XTAL_IN CLK_BUF_PCIE_3GPLL_R
SRC_1/SATA 10
11 CLK_BUF_PCIE_3GPLL#_R Place each 0.1uF cap as close as
R199 33_4 CPU_SEL SRC_1#/SATA# CLK_BUF_DREFSSCLK_R
10 CLK_ICH_14M 30 REF_0/CPU_SEL SRC_2 13 possible to each VDD IO pin. Place
14 CLK_BUF_DREFSSCLK#_R
Place the 33 ohm SRC_2# the 10uF caps on the VDD_IO plane.
CLK_SDATA 31 +3V
resistors close to the CK 505 SDA
CLK_SCLK 32 16 R206 10K_4
SCL *CPU_STOP#
2 VSS_DOT CPU_1 20 TP53
8 19 CLK_BUF_DREFCLK_R 3 4
VSS_27 CPU_1# TP55 CLK_BUF_DREFCLK 10
C 9 23 CLK_BUF_BCLK_R CLK_BUF_DREFCLK#_R 1 2 C
VSS_SATA CPU_0 CLK_BUF_DREFCLK# 10
Y3 12 22 CLK_BUF_BCLK#_R RN3 0_4P2R
XTAL_IN XTAL_OUT VSS_SRC CPU_0# CLK_BUF_PCIE_3GPLL_R
1 2 21 VSS_CPU 3 4 CLK_BUF_PCIE_3GPLL 10
26 25 CK_PWRGD_R CLK_BUF_PCIE_3GPLL#_R 1 2
VSS_REF CKPWRGD/PD# CLK_BUF_PCIE_3GPLL# 10
14.318MHZ 33 RN5 0_4P2R
C283 C284 GND CLK_BUF_DREFSSCLK_R 3 4 CLK_BUF_DREFSSCLK 10
33P 33P CLK_BUF_DREFSSCLK#_R 1 2 CLK_BUF_DREFSSCLK# 10
SLG8SP585V RN6 0_4P2R
CLK_BUF_BCLK_R 1 2 CLK_BUF_BCLK 10
CLK_BUF_BCLK#_R 3 4 CLK_BUF_BCLK# 10
RN4 0_4P2R
+1.05V +3V +3V
4/23 Chagne +3V to +1.05V R184
CLK Enable R197
B B
at B-test *10K_4 R198 R202 1K/F_4
2
*10K_4 *10K_4
CPU_SEL Q26 CK_PWRGD_R
3 1 CLK_SDATA CLK_SDATA 14,15
10,16,20,21,25 ICH_SMBDATA
3
Q25
R189 *2N7002W-7-F 2N7002E_200MA
10K_4 C264
*10p/50V/COG_4 R183 0_4 33 VR_PWRGD_CK505# 2 R200
100K/F_4
+3V
1
2
0 1 Q28
1 3 CLK_SCLK
A 10,16,20,21,25 ICH_SMBCLK
*2N7002W-7-F
CLK_SCLK 14,15
Quanta Computer Inc. A
CPU_SEL CPU0/1=133MHz CPU0/1=100MHz
(default) PROJECT : ZY9
R203 0_4 Size Document Number Rev
3A
Clock Generator
Date: Thursday, August 20, 2009 Sheet 3 of 42
5 4 3 2 1
5 4 3 2 1
AUBURNDALE/CLARKSFIELD PROCESSOR (DMI,PEG,FDI) AUBURNDALE/CLARKSFIELD PROCESSOR (CLK,MISC,JTAG)
U37A
Processor Compensation Signals
B26 R446 49.9/F_4 U37B
PEG_ICOMPI R467 20/F_4 H_COMP3
PEG_ICOMPO A26 AT23 COMP3
A24 B27 A16 CLK_CPU_BCLK_R R440 33_4 CLK_CPU_BCLK 11
8 DMI_TXN0 DMI_RX#[0] PEG_RCOMPO BCLK
MISC
C23 A25 R445 750/F_4 R464 20/F_4 H_COMP2 AT24 B16 CLK_CPU_BCLK#_R R439 33_4 CLK_CPU_BCLK# 11
8 DMI_TXN1 DMI_RX#[1] PEG_RBIAS COMP2 BCLK#
8 DMI_TXN2 B22 DMI_RX#[2] PCIE_MRX_GTX_N[0..15] 17
CLOCKS
A21 K35 PCIE_MRX_GTX_N0 R113 49.9/F_4 H_COMP1 G16 AR30 BCLK_ITP_P_R R485 33_4 BCLK_ITP_P 16
D 8 DMI_TXN3 DMI_RX#[3] PEG_RX#[0] COMP1 BCLK_ITP D
J34 PCIE_MRX_GTX_N1 AT30 BCLK_ITP_N_R R484 33_4 BCLK_ITP_N 16
PEG_RX#[1] PCIE_MRX_GTX_N2 R481 49.9/F_4 H_COMP0 BCLK_ITP#
8 DMI_TXP0 B24 DMI_RX[0] PEG_RX#[2] J33 AT26 COMP0
D23 G35 PCIE_MRX_GTX_N3 E16 CLK_PCIE_3GPLL_R R111 33_4 CLK_PCIE_3GPLL 10
8 DMI_TXP1 DMI_RX[1] PEG_RX#[3] PEG_CLK
DMI
DMI
B23 G32 PCIE_MRX_GTX_N4 D16 CLK_PCIE_3GPLL#_R R112 33_4 CLK_PCIE_3GPLL# 10
8 DMI_TXP2 DMI_RX[2] PEG_RX#[4] PEG_CLK#
A22 F34 PCIE_MRX_GTX_N5 R135 *1K_4 TP_SKT0CC# AH24
8 DMI_TXP3 DMI_RX[3] PEG_RX#[5] SKTOCC#
F31 PCIE_MRX_GTX_N6 A18 DPLL_REF_SSCLK_R
PEG_RX#[6] PCIE_MRX_GTX_N7 DPLL_REF_SSCLK DPLL_REF_SSCLK#_R
8 DMI_RXN0 D24 DMI_TX#[0] PEG_RX#[7] D35 DPLL_REF_SSCLK# A17 8/14 Reserve R213 by intel
G24 E33 PCIE_MRX_GTX_N8 H_CATERR# AK14 S3 at Ramp.
8 DMI_RXN1 DMI_TX#[1] PEG_RX#[8] CATERR#
THERMAL
F23 C33 PCIE_MRX_GTX_N9 R213 *100K_4
8 DMI_RXN2 DMI_TX#[2] PEG_RX#[9]
H23 D32 PCIE_MRX_GTX_N10 Layout Note: Place
8 DMI_RXN3 DMI_TX#[3] PEG_RX#[10]
B32 PCIE_MRX_GTX_N11 F6 CPU_DDR3_DRAMRST# 37
D25
PEG_RX#[11]
C31 PCIE_MRX_GTX_N12 R480 H_PECI_ISO AT15
SM_DRAMRST# these resistors
8 DMI_RXP0 DMI_TX[0] PEG_RX#[12] 11 H_PECI PECI
8 DMI_RXP1 F24 DMI_TX[1] PEG_RX#[13] B28 PCIE_MRX_GTX_N13 *SHORT_4
SM_RCOMP[0] AL1 SM_RCOMP_0 R155 100/F_4 near Processor
E23 B30 PCIE_MRX_GTX_N14 AM1 SM_RCOMP_1 R157 24.9/F_4
8 DMI_RXP2 DMI_TX[2] PEG_RX#[14] SM_RCOMP[1]
G23 A31 PCIE_MRX_GTX_N15 AN1 SM_RCOMP_2 R159 130/F_4 +1.1V_VTT
8 DMI_RXP3 DMI_TX[3] PEG_RX#[15] SM_RCOMP[2]
PCIE_MRX_GTX_P[0..15] 17 33 H_PROCHOT# R493 H_PROCHOT#_R AN26
PCIE_MRX_GTX_P0 *SHORT_4 PROCHOT# R477 10K_4
PEG_RX[0] J35 PM_EXT_TS#[0] AN15
DDR3
MISC
H34 PCIE_MRX_GTX_P1 AP15 R478 10K_4
PEG_RX[1] PCIE_MRX_GTX_P2