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8 7 6 5 4 3 2 1
Cover Sheet
Block Diagram
1
2
MS-6577 Version 2.0C
D
INTEL (R) Brookdale-G Chipset D
Clock CY28349 & ATA100 IDE Connector 3 Willamette/Northwood 478pin mPGA-B Processor Schematics
mPGA478-B INTEL CPU Sockets 4-5
CPU:
INTEL Brookdale-G GMCH -- North Bridge 6-8 Willamette/Northwood mPGA-478B Processor
INTEL ICH4 -- South Bridge 9 - 10
LPC I/O W83627HF-AW 11 System Brookdale-G Chipset:
AC'97 Codec and Audio Connector & Internal Speaker 12 INTEL GMCH (North Bridge) +
INTEL ICH4 (South Bridge)
C
FWH 13 C
DDR DIMMM1,2 14 On Board Chipset:
DDR Damping & DDR Termination 15 BIOS -- FWH
AGP 4X SLOT (1.5V) 16 LPC Super I/O -- W83627HF-AW
PCI SLOT 1 & 2 & 3 17 Clock Generator -- CY28349
IO Connector 18 AC'97 Codec -- RealTek AC202A/650
USB Connecto r 19 Onboard Lan Chipset -- RealTek RTL8101L
Front Panel & Connectors & FAN 20 Onboard 1394 -- NEC PD72874
B B
ACPI Controller (MS-5) 21 Expansion Slots:
L6719B CPU Power ( PWM )-VRM9.0 22 AGP2.0 SLOT * 1
Realtek RTL8101L LAN 23 PCI2.2 SLOT * 3
VGA Connector 24
Platform:
NEC 1394 25
Micro ATX
Jumper Setting & Manual Parts 26
GPIO Definition 27-28
A A
Power Delivery Map 29
MICRO-STAR
MSI
Title
COVER SHEET
Size Document Number Rev
2.0C
MS-6577
Date: Friday, August 30, 2002 Sheet 1 of 26
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
(478PINS)
( 100/133MHz)
Power
Supply VRM Willamette/Northwood CK408 Clock
( 100/133MHz)
CONN 9.0 Socket (mPGA478-B)
( 400/533MHz) S calable Bus S calable Bus/2
AGP 4 X (66MHz) AGP
AGP 4X
4X(1.5V) MCH: Memory
(1.5V)
AGP CONN
Controller HUB
( 5 93PINS/FCBGA) ( 200/266MHz)
DDR DIMM 1:2
VGA CONN
( 66MHz X 4 ) H UB Interface
( 14.318MHz)
C C
ICH4: I/O P CI (33MHz)
PCI Slots 1:3
( 3 60PINS/EBGA)
Controller HUB
IDE CONN 1&2
PCI Lan /
(48MHz) RealTek RJ-45
8101L Connector
( 3 3MHz)
(33MHz)
LPC Bus AC Link
USB Port 0:5
AC '97 Audio
FWH NEC PD72874
Codec Line Out
LPC SIO
MIC In
B Audio In B
Front 1394
Line In
PS2 Mouse & Parallel (1) Floppy Disk
CD-ROM
Keyboard Serial (1) Drive CONN Rear 1394
A A
MICRO-STAR
MSI
Title
BLOCK DIAGRAM
Size Document Number Rev
2.0C
MS-6577
Date: Friday, August 30, 2002 Sheet 2 of 26
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8 7 6 5 4 3 2 1
CLOCK GENERATOR BLOCK *Trace < 0.5"
Shut Source Termination Resistors Pull-Down Capacitors
U12 CPUCLK R227 49.9RST
FB20 80_0805 VCC3V 39 41 CPU0 R240 27.4RST CPUCLK CPUCLK# R233 49.9RST CPUCLK C173 X_10p
VCC3 CPU_VDD CPUCLK0 CPUCLK {4}
40 CPU0# R241 27.4RST CPUCLK# MCHCLK R234 49.9RST
CPUCLK0# CPUCLK# {4}
CB140 CB189 CB146 CB163 MCHCLK# R232 49.9RST CPUCLK# C174 X_10p
104P 104P 106P/0805 104P 36 38 CPU1 R242 27.4RST MCHCLK
CPU_GND CPUCLK1 MCHCLK {6}
37 CPU1# R243 27.4RST MCHCLK# MCHCLK C177 X_10p
CPUCLK1# MCHCLK# {6}
filtering from 10K~1M
46 Trace less 0.2" MCHCLK# C178 X_10p
MREF_VDD
D
* Put GND copper under Clock Gen. 45 49.9ohm for 50ohm M/B impedance D
CB165 CPUCLK2 44
connect to every GND pin 104P 43 CPUCLK2# R503 33 MCH_66
MREF_GND MCH_66 {6}
R504 33 ICH_66
* 40 mils Trace on Layer 4 R505 33 AGPCLK ICH_66 {10} CLOCK STRAPPING RESISTORS AGPCLK C291 X_10p
32 31
with GND copper around it 3V66_VDD 3V66_0 AGPCLK {16}
30 R506 33 DOT_CLK ICH_66 C292 X_10p
3V66_1 DOT_CLK {6}
CB145 28 MCH_66 C293 X_10p
104P 29 3V66_2 DOT_48 FS0 R263 10K VCC3V
27
3V66_GND 3V66_48/SEL66_48# FS3 R266 10K
* put close to every power pin 6 FS2 R520 33 FS2 R272 10K
FS2/PCI0 7 1394_PCLK {25}
9 FS3 FS4 R277 10K ICH_14 C172 10P
* Trace Width 7mils. PCI_VDD FS3/PCI1 8 SEL48_1 R273 X_33 FS1 R25 1.5K
SEL48_24#/PCI2 PCICLK3 {17}
CB144 7 8 R252 10K SIO_24 C180 X_10P
* Same Group spacing 15mils 104P 5 10 FS4 RN57 5 6 PCICLK0 BSEL0 {4,6}
PCI_GND FS4/PCI3 11 PCICLK0 {17}
8P4R-33
3 4 PCICLK1 ICH_48 C194 X_10P
* Different Group spacing 30mils PCI4 12 PCICLK1 {17}
18 1 2 PCICLK2 BSEL0 0 100 ; 1 133
PCI_VDD PCI5 14 PCICLK2 {17}
7 8 SIO_PCLK CODEC_14 C196 X_10P
* Differentical mode spacing 7mils CB148 PCI6 15 RN58 5 LAN_PCLK SIO_PCLK {11}
6 LAN_PCLK {23}
on itself 104P 13 PCI7 16 8P4R-33
3 4 FWH_PCLK FS4 FS3 FS2 FS1 FS0 FSB (MHz) DOT_CLK C251 X_10P
PCI_GND PCI8 17 FWH_PCLK {13}
1 2 ICH_PCLK
PCI9 ICH_PCLK {9}
1 1 1 0 1 100 MHz Ioh=6*Iref
FB22 X_80_0805 VDDA3V 24
VCC3 C181 48_VDD 22 FS0 R264 33 ICH_48 Voh=0.71V
FS0/48MHz ICH_48 {10} 1 1 1 1 1 133 MHz
CP12 X_COPPER 103P 23 FS1 R254 33 SIO_24
FS1/24_48MHz SIO_24 {11}
21
48_GND SEL48_1 R267 X_10K VCC3V
2
CB147 CB151 C195 REF_VDD MUL0 R238 33 ICH_14
48 ICH_14 {10}
104P 106P/0805 103P MUL0/REF0 1 MUL1 R265 33 CODEC_14 DOT_48 R276 10K
C CODEC_14 {12} C
47 MUL1/REF1
REF_GND 0 S e t Pin 27 48MHz
34 3 X1 C191 22P
C189 CORE_VDD X1
103P X1 14M-32pf-HC49S-D
33 4 X2 C188 22P
CORE_GND X2 R237 X_10K VCC3V
SMBCLK_ISO 26 35 R244 475RST Iref = 2.32mA MUL0 R230 10K MUL 1:0
{11,14,21} SMBCLK_ISO SCLK IREF
SMBDATA_IS 25
O 0 0 4X
{11,14,21} SMBDATA_IS O SDATA used only for EMI issue
20 MUL1 R255 10K VCC3V 0 1 5X
R295 10K 19 RESET# 42 PWR_DN# R239 1K VCC3V 1 0 6X
VCC3 VTT_GD# PWR_DN# 1 1 7X Trace less 0.2"
CY28349
R285 220 Q29
VCCP VCC3 VCC3 VCC3 VCC3
2N3904S
CB166 CB141 CB158 CB142 SMBCLK_ISO R245 4.7K VCC3
104P 104P 104P 104P SMBDATA_ISO R246 4.7K
PRIMARY IDE BLOCK SECONDARY IDE BLOCK
B B
PRIMAR1 SECON1
YJ220-CB-1 YJ220-CW-1 SDD[8..15] {10}
HD_RST# R189 33 1 2 HD_RST# R187 33 1 2
{21} HD_RST#
PDD7 3 4 PDD8 SDD7 3 4 SDD8
{10} PDD[0..7] {10} SDD[0..7]
PDD6 5 6 PDD9 SDD6 5 6 SDD9
PDD5 7 8 PDD10 SDD5 7 8 SDD10
PDD4 9 10 PDD11 SDD4 9 10 SDD11
PDD3 11 12 PDD12 SDD3 11 12 SDD12
PDD2 13 14 PDD13 SDD2 13 14 SDD13
PDD1 15 16 PDD14 SDD1 15 16 SDD14
PDD0 17 18 PDD15 SDD0 17 18 SDD15
19 19
PDD[8..15] {10}
{10} PD_DREQ 21 22 {10} SD_DREQ 21 22
23 24 23 24
{10} PD_IOW# {10} SD_IOW#
R518 33 25 26 R519 33 25 26
{10} PD_IOR# {10} SD_IOR#
27 28 27 28
{10} PD_IORDY {10} SD_IORDY
29 30 29 30
{10} PD_DACK# {10} SD_DACK#
31 32 31 32
{9} IRQ14 {9} IRQ15
33 34 33 34
{10} PD_A1 PD_DET {10} {10} SD_A1 SD_DET {10}
{10} PD_A0 35 36 PD_A2 {10} {10} SD_A0 35 36 SD_A2 {10}
37 38 37 38
{10} PD_CS#1 PD_CS#3 {10} {10} SD_CS#1 SD_CS#3 {10}
39 40 39 40
{20} PD_LED {20} SD_LED
C98 C97
X_473P X_473P
R97 C106 R114 R93 C107 R113
4.7K X_220P 10K 4.7K X_220P 10K
A VCC5 VCC3 VCC5 VCC3 A
MICRO-STAR
MSI
ATA100 IDE CONNECTORS *
*
*
Trace Width : 5mils
Trace Spacing : 7mils
Length(longest)-Length(shortest)<0.5"
Title
CLOCK GEN & ATA100 IDE
* Trace Length less than 5" Size Document Number Rev
2.0C
MS-6577
Date: Friday, August 30, 2002 Sheet 3 of 26
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CPU SIGNAL BLOCK
{6} HA#[3..31] CPU GTL REFERNCE VOLTAGE BLOCK
VCCP
VID[0..4] {11,22}
HA#31
HA#29
HA#24
HA#21
HA#19
HA#14
HA#11
HA#28
HA#25
HA#22
HA#18
HA#15
HA#12
HA#30
HA#27
HA#26
HA#23
HA#20
HA#17
HA#16
HA#13
HA#10
HA#9
HA#8
HA#5
HA#4
HA#7
HA#6
HA#3
AE3 VID2
AE1 VID4
AE4 VID1
AE5 VID0
AE2 VID3
R63
2/3*Vccp 49.9RST
AD26
AC26
AE25
GTLREF1
AB1
M1
M4
M3
M6
W2
W1
U4
R6
U3
U1
R3
R2
N5
N4
N2
N1
Y1
V3
V2
P6
P4
P3
K1
K4
K2
A5
A4
T5
T4
T2
T1
L2
L3
L6
U3A C47 CB56 C62 R62
220P 104P 105P 100RST
VCC_SENSE
VSS_SENSE
ITP_CLK1
ITP_CLK0
VID4#
VID3#
VID2#
VID1#
VID0#
DBR#
A35#
A34#
A33#
A32#
A31#
A30#
A29#
A28#
A27#
A26#
A25#
A24#
A23#
A22#
A21#
A20#
A19#
A18#
A17#
A16#
A15#
A14#
A13#
A12#
A11#
A10#
A9#
A8#
A7#
A6#
A5#
A4#
A3#
D D
HINV#0 E21
{6} HINV#[0..3] DBI0#
HINV#1 G25 AA21 GTLREF1
HINV#2 P26 DBI1# GTLREF3 AA6
HINV#3 DBI2# GTLREF2 F20
V21
DBI3# GTLREF1 F6
AC3 GTLREF0
IERR# BPM#5
V6 AB4
B6 MCERR# BPM5# AA5 BPM#4
{9} FERR# FERR# BPM4# Y6
Y4
{9} STPCLK# STPCLK# BPM3# AC4 Every pin put one 220pF cap near it.
AA3
W5 BINIT# BPM2# AB5 BPM#1
{9,13} HINIT# AB2 INIT# BPM1# AC6 BPM#0 Trace Width 10mils, Space 15mils.
RSP# BPM0#
HREQ#4 Keep the voltage dividers within 1.5 inches of the
H5 H3
{6} HDBSY# DBSY# REQ4# J3 HREQ#[0..4] {6}