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Stackup
R23 AMD Sabin UMA/Muxless SYSTEM DIAGRAM TOP
GND
IN1
A



DDR3
AMD DDR3 900MHz IN2
A




PCI-E x 8 ( 8 ~ 15 ) VCC
SODIMM1 Channel A Seymour-XT VRAM
Max. 4GB 128x16x4,64bit BOT
PG.12
AMD PG.19


DDR3
SODIMM2 Channel B Llano APU PG.14~18 +3V/+5V
Max. 4GB
PG.31
PG.13 35mm X 35mm PCI-E ( 0 ~ 3 )
HDMI PG.21 +1.1V/+1.1VS5
PG.32
B
FS1 socket 722 pin uPGA DP Port 0 ANX3110 LVDS B
LAN2 LAN1 LAN0
DP to LVDS LVDS PG.20 +1.2V/+2.5V
Card reader LAN WLAN TDP 35W Translator PG.11 PG.33
RTS5219-GR RTS8165EH BT COMBO PG.2~5
10/100 PG.24 10/100 PG.27 PG.30
+VCC_CORE
DP Port 1 UMI PG.34

+VDDNB_CORE
CRT CRT PG.35
PG.22
AMD FCH +1.5VSUS
USB2.0 Webcam BT +1.0V_VGA
Ports X 2PG.26 Softbreeze
PG.20 PG.26 +1.8V_VGA
C
USB 2.0 Hudson M2/M3 USB 2.0
PORT0,5 PORT2 PORT15
PG.36
C




PORT10 24.5mm X 24.5mm +VGACore
656pin FCBGA SATA0
SPI HDD PG.23 +1.5V_VGA
SPI ROM TDP 4.7W
+3V_VGA
LPC PG.6~10 SATA1 PG.37
KBC ODD
EnE KB3930QF D2 PG.23
PG.29 Charger
Azalia PG.38
KB TP ROM FAN Speaker Discharger
PG.25
AUDIO PG.39
D D

CODEC HP/MIC
PG.26
IDT92HD80B1
Analog MIC
PG.25 PG.25
Size Document Number Rev
Custom BLOCK DIAGRAM 1A

Date: Tuesday, May 03, 2011 Sheet 1 of 40
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5 4 3 2 1

U29F



02
note --HDMI P&N can not swap
AA8 PCI EXPRESS AA2 PEG_HDMI_TXDP2 C771 0.1U/10V_4 C_TX2_HDMI+
P_GFX_RXP0 P_GFX_TXP0 C_TX2_HDMI+ 21
AA9 AA3 PEG_HDMI_TXDN2 C772 0.1U/10V_4 C_TX2_HDMI-
P_GFX_RXN0 P_GFX_TXN0 C_TX2_HDMI- 21




HDMI
Y7 Y2 PEG_HDMI_TXDP1 C1053 0.1U/10V_4 C_TX1_HDMI+
P_GFX_RXP1 P_GFX_TXP1 C_TX1_HDMI+ 21
Y8 Y1 PEG_HDMI_TXDN1 C774 0.1U/10V_4 C_TX1_HDMI- P_GFX_TXP/N[3:0]
P_GFX_RXN1 P_GFX_TXN1 PEG_HDMI_TXDP0 C_TX0_HDMI+ C_TX1_HDMI- 21
W5 Y4 C775 0.1U/10V_4 correspond to DisplayPort 2.
P_GFX_RXP2 P_GFX_TXP2 C_TX0_HDMI+ 21
W6 Y5 PEG_HDMI_TXDN0 C776 0.1U/10V_4 C_TX0_HDMI-
P_GFX_RXN2 P_GFX_TXN2 C_TX0_HDMI- 21
W8 W2 PEG_HDMI_TXCP C777 0.1U/10V_4 C_TXC_HDMI+
P_GFX_RXP3 P_GFX_TXP3 PEG_HDMI_TXCN C_TXC_HDMI- C_TXC_HDMI+ 21
W9 W3 C778 0.1U/10V_4
P_GFX_RXN3 P_GFX_TXN3 C_TXC_HDMI- 21
V7 P_GFX_RXP4 P_GFX_TXP4 V2
V8 P_GFX_RXN4 P_GFX_TXN4 V1
U5 P_GFX_RXP5 P_GFX_TXP5 V4
U6 P_GFX_RXN5 P_GFX_TXN5 V5 swap for layout
D U8 U2 D
P_GFX_RXP6 P_GFX_TXP6 concern , AMD
U9 U3




GRAPHICS
P_GFX_RXN6 P_GFX_TXN6 recommend
T7 P_GFX_RXP7 P_GFX_TXP7 T2
T8 P_GFX_RXN7 P_GFX_TXN7 T1
14 PEG_RXN8 PEG_RXN8 R5 T4 PEG_TXP8_C PEG_TXN8_CC779 0.1U/10V_4 PEG_TXP8 PEG_TXP8 14
PEG_RXP8 P_GFX_RXP8 P_GFX_TXP8 PEG_TXN8_C PEG_TXP8_C C780 0.1U/10V_4 PEG_TXN8
14 PEG_RXP8 R6 P_GFX_RXN8 P_GFX_TXN8 T5 PEG_TXN8 14
14 PEG_RXP9 PEG_RXP9 R8 R2 PEG_TXP9_C PEG_TXN9_CC781 0.1U/10V_4 PEG_TXP9 PEG_TXP9 14
PEG_RXN9 P_GFX_RXP9 P_GFX_TXP9 PEG_TXN9_C PEG_TXP9_C C782 0.1U/10V_4 PEG_TXN9
P&N swap for 14 PEG_RXN9 R9 P_GFX_RXN9 P_GFX_TXN9 R3 PEG_TXN9 14
PEG_RXP10 P7 P2 PEG_TXP10_C C783 0.1U/10V_4 PEG_TXP10
layout concern , 14 PEG_RXP10 P_GFX_RXP10 P_GFX_TXP10 PEG_TXP10 14




PEG X 8
14 PEG_RXN10 PEG_RXN10 P8 P1 PEG_TXN10_C C784 0.1U/10V_4 PEG_TXN10 PEG_TXN10 14
AMD recommend PEG_RXN11 P_GFX_RXN10 P_GFX_TXN10 PEG_TXP11_C C785 0.1U/10V_4 PEG_TXP11
14 PEG_RXN11 N5 P_GFX_RXP11 P_GFX_TXP11 P4 PEG_TXP11 14
PEG_RXP11 N6 P5 PEG_TXN11_C C786 0.1U/10V_4 PEG_TXN11
14 PEG_RXP11 P_GFX_RXN11 P_GFX_TXN11 PEG_TXN11 14
14 PEG_RXP12 PEG_RXP12 N8 N2 PEG_TXP12_C C787 0.1U/10V_4 PEG_TXP12 PEG_TXP12 14
PEG_RXN12 P_GFX_RXP12 P_GFX_TXP12 PEG_TXN12_C C788 0.1U/10V_4 PEG_TXN12
14 PEG_RXN12 N9 P_GFX_RXN12 P_GFX_TXN12 N3 PEG_TXN12 14
PEG_RXP13 M7 M2 PEG_TXP13_C C789 0.1U/10V_4 PEG_TXP13
14 PEG_RXP13 P_GFX_RXP13 P_GFX_TXP13 PEG_TXP13 14
14 PEG_RXN13 PEG_RXN13 M8 M1 PEG_TXN13_C C790 0.1U/10V_4 PEG_TXN13 PEG_TXN13 14
PEG_RXP14 P_GFX_RXN13 P_GFX_TXN13 PEG_TXP14_C C791 0.1U/10V_4 PEG_TXP14
14 PEG_RXP14 L5 P_GFX_RXP14 P_GFX_TXP14 M4 PEG_TXP14 14
PEG_RXN14 L6 M5 PEG_TXN14_C C792 0.1U/10V_4 PEG_TXN14
14 PEG_RXN14 P_GFX_RXN14 P_GFX_TXN14 PEG_TXN14 14
PEG_RXP15 L8 L2 PEG_TXP15_C C793 0.1U/10V_4 PEG_TXP15
14 PEG_RXP15 P_GFX_RXP15 P_GFX_TXP15 PEG_TXP15 14
14 PEG_RXN15 PEG_RXN15 L9 L3 PEG_TXN15_C C794 0.1U/10V_4 PEG_TXN15 PEG_TXN15 14
P_GFX_RXN15 P_GFX_TXN15
PCIE_RXP0_WLAN AC5 AD4 PCIE_TXP0_C C903 0.1U/10V_4
30 PCIE_RXP0_WLAN P_GPP_RXP0 P_GPP_TXP0 PCIE_TXP0_WALN 30
TO WLAN PCIE_RXN0_WLAN AC6 AD5 PCIE_TXN0_C C904 0.1U/10V_4 PCIE_TXN0_WLAN 30 TO WLAN
30 PCIE_RXN0_WLAN P_GPP_RXN0 P_GPP_TXN0
PCIE_RXP1_LAN AC8 AC2 PCIE_TXP1_C C905 0.1U/10V_4 PCIE_TXP1_LAN 27
27 PCIE_RXP1_LAN P_GPP_RXP1 P_GPP_TXP1
TO PCIE-LAN PCIE_RXN1_LAN AC9 AC3 PCIE_TXN1_C C906 0.1U/10V_4 TO PCIE-LAN
27 PCIE_RXN1_LAN P_GPP_RXN1 P_GPP_TXN1 PCIE_TXN1_LAN 27
PCIE_RXP2_CARD AB7 AB2 PCIE_TXP2_C C907 0.1U/10V_4 PCIE_TXP2_CARD 24
24 PCIE_RXP2_CARD P_GPP_RXP2 P_GPP_TXP2




GPP
TO PCIE CARD READER PCIE_RXN2_CARD AB8 AB1 PCIE_TXN2_C C908 0.1U/10V_4 PCIE_TXN2_CARD 24 TO PCIE CARD READER
24 PCIE_RXN2_CARD P_GPP_RXN2 P_GPP_TXN2
AA5 P_GPP_RXP3 P_GPP_TXP3 AB4
AA6 P_GPP_RXN3 P_GPP_TXN3 AB5
C AF8 AF1 UMI_TXP0_C C795 0.1U/10V_4 UMI_TXP0 C
7 UMI_RXP0 P_UMI_RXP0 P_UMI_TXP0 UMI_TXP0 7
7 UMI_RXN0 AF7 AF2 UMI_TXN0_C C796 0.1U/10V_4 UMI_TXN0 UMI_TXN0 7
P_UMI_RXN0 P_UMI_TXN0 UMI_TXP1_C C797 0.1U/10V_4 UMI_TXP1
7 UMI_RXP1 AE6 P_UMI_RXP1 P_UMI_TXP1 AF5 UMI_TXP1 7
UMI_TXN1_C C798 0.1U/10V_4 UMI_TXN1




UMI-LINK
7 UMI_RXN1 AE5 P_UMI_RXN1 P_UMI_TXN1 AF4 UMI_TXN1 7
7 UMI_RXP2 AE9 AE3 UMI_TXP2_C C799 0.1U/10V_4 UMI_TXP2 UMI_TXP2 7
P_UMI_RXP2 P_UMI_TXP2 UMI_TXN2_C C800 0.1U/10V_4 UMI_TXN2
7 UMI_RXN2 AE8 P_UMI_RXN2 P_UMI_TXN2 AE2 UMI_TXN2 7
AD8 AD1 UMI_TXP3_C C801 0.1U/10V_4 UMI_TXP3
7 UMI_RXP3 P_UMI_RXP3 P_UMI_TXP3 UMI_TXP3 7
7 UMI_RXN3 AD7 AD2 UMI_TXN3_C C802 0.1U/10V_4 UMI_TXN3 UMI_TXN3 7
P_UMI_RXN3 P_UMI_TXN3
R508 196/F_6 P_ZVDDP K5 K4 P_ZVSS R509 196/F_6
+1.2V P_ZVDDP P_ZVSS


Llano APU
+3V

HDT+ Connector for Debug only PV change to short-pad
VID Override Circuit
BOOT VOLTAGE
+1.5V
R873
*0_4/s SVC SVD VFIX_+VDD VFIX_+VDD
=VCC/GND =OPEN

R510 R511 0 0 1.1 1.1
*300/J_4 *300/J_4

U30 0 1 1.0 1.2
B APU_RST# 1 6 APU_RST_L_BUF B
4,7 APU_RST# A1 Y1
2 GND VCC 5 1 0 0.9 1.0
Note:
APU_PWRGD 3 4 APU_PWROK_BUF
4,7 APU_PWRGD A2 Y2 To override VID,Remove Rd, Re, Rf, install Rc
1 1 0.8 0.8
set VID via SVC & SVD option RES.
*74LVC2G07
+1.5VSUS SI +1.5V




R512 R513
J1 1K/F_4 1K/F_4 R515 R516 R514
+1.5VSUS *1K/J_4 *1K/J_4 *2.2K/J_4
20
APU_TEST18 19
close to HDT 4 APU_TEST18 18
Rd
+1.5VSUS APU_TEST19 SVC R517 0_4 CPU_SVC
debug HEADER 4 APU_TEST19 17 4 SVC CPU_SVC 34,35
APU_RST_L_BUF Re
APU_TDI R529 *1K/F_4 CPU_LDT_RST_HTPA# 16 SVD R520 0_4 CPU_SVD
TP37 15 4 SVD CPU_SVD 34,35
APU_TCK R530 *1K/F_4 APU_DBREQ# Rf
4 APU_DBREQ# 14
APU_TMS R531 *1K/F_4 APU_DBRDY APU_PWRGD R523 0_4 CPU_PWRGD_SVID_REG CPU_PWRGD_SVID_REG 34,35
4 APU_DBRDY 13 4,7 APU_PWRGD
APU_TRST# R532 *1K/F_4 APU_TCK
4 APU_TCK 12
APU_DBREQ# R533 *300/J_4 APU_TMS APU_PWRGD have pull up 300ohm
4 APU_TMS 11
APU_TDI
4 APU_TDI
APU_TRST# 10 to +1.5V on page 4 R526 R527 R528
4 APU_TRST# APU_TDO 9 *220/J_4 *220/J_4 *220/J_4
4 APU_TDO 8
APU_PWROK_BUF for normal operation Ra Rb Rc
7
A 6 open Ra , Rb,Rc A
5
4
3
2
1
*HDT CONN
88511-2001-20p-l Quanta Computer Inc.
DEL AMD HDT debug port
PROJECT : R23
Size Document Number Rev
1A
Llano PCIE/UMI/GPP
Date: Wednesday, May 04, 2011 Sheet 2 of 40
5 4 3 2 1
5 4 3 2 1




U29A M_A_DQ[0..63] 12
U29B
03
M_B_DQ[0..63] 13
12 M_A_A[15:0] M_A_A0 MEMORY CHANNEL A M_A_DQ0 13 M_B_A[15:0]
U20 MA_ADD0 MA_DATA0 E13 MEMORY CHANNEL B
M_A_A1 R20 J13 M_A_DQ1 M_B_A0 T27 A14 M_B_DQ0
M_A_A2 MA_ADD1 MA_DATA1 M_A_DQ2 M_B_A1 MB_ADD0 MB_DATA0 M_B_DQ1
R21 MA_ADD2 MA_DATA2 H15 P24 MB_ADD1 MB_DATA1 B14
M_A_A3 P22 J15 M_A_DQ3 M_B_A2 P25 D16 M_B_DQ2
M_A_A4 MA_ADD3 MA_DATA3 M_A_DQ4 M_B_A3 MB_ADD2 MB_DATA2 M_B_DQ3
P21 MA_ADD4 MA_DATA4 H13 N27 MB_ADD3 MB_DATA3 E16
D M_A_A5 N24 F13 M_A_DQ5 M_B_A4 N26 B13 M_B_DQ4 D
M_A_A6 MA_ADD5 MA_DATA5 M_A_DQ6 M_B_A5 MB_ADD4 MB_DATA4 M_B_DQ5
N23 MA_ADD6 MA_DATA6 F15 M28 MB_ADD5 MB_DATA5 C13
M_A_A7 N20 E15 M_A_DQ7 M_B_A6 M27 B16 M_B_DQ6
M_A_A8 MA_ADD7 MA_DATA7 M_B_A7 MB_ADD6 MB_DATA6 M_B_DQ7
N21 MA_ADD8 M24 MB_ADD7 MB_DATA7 A16
M_A_A9 M21 H17 M_A_DQ8 M_B_A8 M25
M_A_A10 MA_ADD9 MA_DATA8 M_A_DQ9 M_B_A9 MB_ADD8 M_B_DQ8
U23 MA_ADD10 MA_DATA9 F17 L26 MB_ADD9 MB_DATA8 C17
M_A_A11 M22 E19 M_A_DQ10 M_B_A10 U26 B18 M_B_DQ9
M_A_A12 MA_ADD11 MA_DATA10 M_A_DQ11 M_B_A11 MB_ADD10 MB_DATA9 M_B_DQ10
L24 MA_ADD12 MA_DATA11 J19 L27 MB_ADD11 MB_DATA10 B20
M_A_A13 AA25 G16 M_A_DQ12 M_B_A12 K27 A20 M_B_DQ11
M_A_A14 MA_ADD13 MA_DATA12 M_A_DQ13 M_B_A13 MB_ADD12 MB_DATA11 M_B_DQ12
L21 MA_ADD14 MA_DATA13 H16 W 26 MB_ADD13 MB_DATA12 E17
M_A_A15 L20 H19 M_A_DQ14 M_B_A14 K25 B17 M_B_DQ13
12 M_A_BS#[2..0] MA_ADD15 MA_DATA14 MB_ADD14 MB_DATA13
F19 M_A_DQ15 M_B_A15 K24 B19 M_B_DQ14
M_A_BS#0 MA_DATA15 13 M_B_BS#[2..0] MB_ADD15 MB_DATA14 M_B_DQ15
U24 MA_BANK0 MB_DATA15 C19
M_A_BS#1 U21 H20 M_A_DQ16 M_B_BS#0 U27
M_A_BS#2 MA_BANK1 MA_DATA16 M_A_DQ17 M_B_BS#1 MB_BANK0 M_B_DQ16
12 M_A_DM[7..0] L23 MA_BANK2 MA_DATA17 F21 T28 MB_BANK1 MB_DATA16 C21
J23 M_A_DQ18 M_B_BS#2 K28 B22 M_B_DQ17
MA_DATA18 13 M_B_DM[7..0] MB_BANK2 MB_DATA17
M_A_DM0 E14 H23 M_A_DQ19 C23 M_B_DQ18
M_A_DM1 MA_DM0 MA_DATA19 M_A_DQ20 M_B_DM0 MB_DATA18 M_B_DQ19
J17 MA_DM1 MA_DATA20 G20 D14 MB_DM0 MB_DATA19 A24
M_A