Text preview for : Compal_LA-5631P.pdf part of Compal Compal LA-5631P Compal Compal_LA-5631P.pdf
Back to : Compal_LA-5631P.pdf | Home
A B C D E
1 1
Compal Confidential
2 2
NCL20 ULV M/B Schematics Document
Intel Penryn Processor with Cantiga SFF + DDRIII + ICH9M SFF
3
2009-10-08 3
REV:0.4
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/27 Deciphered Date 2010/01/21 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL20 M/B LA-5631P Schematic
Date: Tuesday, November 10, 2009 Sheet 1 of 41
A B C D E
A B C D E
Compal confidential CK505
File Name : LA-5631P Thermal Sensor
Mobile Penym EMC1402-1-ACZL Clock Generator
page4 ICS9LPRS387
LV/ULV Dual Core
LS5631P I/O Board uFCPGA-956 CPU - SFF page 19
1 1
page 4,5,6,7
LS5632P C/R Board
H_A#(3..35) FSB
H_D#(0..63)
667/800/1066MHz 1.05V
LS5633P LED Board HDMI Conn. LCD CONN. CRT CONN.
page25 page 17 page 18
LS5634P SW Board Intel Cantiga GS45 DDR3 800MHz 1.5V DDR3
LVDS FCBGA 1363 - SFF SO-DIMM X2
Level shift
Dual Channel page 14,15
LS5635P TP/B Board
TMDS page 8,9,10,11,12,13
LS5636P ODD/B Board
2
DMI X4 USB conn x2 Bluetooth CMOS 2
conn Camera 1.3M
page 28 page 28 page23
IO board
PCI-Express
Intel ICH9-M 3.3V 48MHz USB
WBMMAP-569 - SFF 3.3V 24.576MHz/48Mhz
S-ATA
HD Audio
MINI Card x1 MINI Card x1 LAN ATHEROS Card Reader
page 19,20,21,22 RTS5159-GR
USB conn x1
3G WLAN AR8131L
page23
page 27 page 24 HDA Codec
port 0 ALC269X-GR
LPC BUS page 32
SIM CONN. RJ45 LAN HDD IO board
3 connector connector 3
page 23
page 25
ENE KB926 D2
port 1 page 29
CDROM SPEAKER Audio Jack
page 33 page 33
connector
RTC CKT. page 23
page 24
Power On/Off CKT. Touch Pad Int.KBD
page 30 page 30
page 32
DC/DC Interface CKT. IO/B Conn. BIOS
4
page 29 4
page 35 page 30
TP/B Conn.
page 31
Power Circuit DC/DC Security Classification Compal Secret Data Compal Electronics, Inc.
page 36~~42 2009/02/27 2009/02/20 Title
Speaker Conn. Issued Date Deciphered Date
Block Diagram
page 31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B NCL20 M/B LA-5631P Schematic 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, October 20, 2009 Sheet 2 of 41
A B C D E
A B C D E
SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Voltage Rails
Full ON HIGH HIGH HIGH HIGH ON ON ON ON
Power Plane Description S1 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
VIN Adapter power supply (19V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
B+ AC or battery power rail for power circuit. N/A N/A N/A
1
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1
+CPU_CORE Core voltage for CPU ON OFF OFF
+1.05VS 1.05V switched power rail ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
ON OFF OFF
+1.5V 1.5V power rail for DDR ON ON OFF Board ID / SKU ID Table for AD channel
+1.5VS 1.5V switched power rail ON OFF OFF Vcc 3.3V +/- 5%
+0.75V 0.75V switched power rail for DDR terminator ON OFF OFF Ra/Rc/Re 100K +/- 5%
Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
0 0 0 V 0 V 0 V
+3VALW 3.3V always on power rail ON ON ON* 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+3V_LAN 3.3V power rail for LAN ON ON ON 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+3VS 3.3V switched power rail ON OFF OFF 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+5VALW 5V always on power rail ON ON ON* 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
+5VS 5V switched power rail ON OFF OFF 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
+VSB VSB always on power rail ON ON ON* 7 NC 2.500 V 3.300 V 3.300 V
2 2
+RTCVCC RTC power ON ON ON
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
BOARD ID Table BTO Option Table
External PCI Devices Board ID PCB Revision BTO Item BOM Structure
Device IDSEL# REQ#/GNT# Interrupts
0 0.1
1
2
3
4
5
6
7 PCIE table
PCIE port1 3G Card
EC SM Bus1 address EC SM Bus2 address USB table
PCIE port2 Wireless Card
3
Port0 MB USB Conn1. 3
Device Address Device Address UHCI1
Smart Battery ADI ADT7421
Port1 MB USB Conn2. PCIE port3 GLAN
0001 011X b 1001 100X b
Port2 sub board
EHCI1 UHCI2 PCIE port4
Port3 WLAN
Port4 Card Reader PCIE port5
UHCI3
Port5 3G
PCIE port6
Port6 BT
UHCI4
Port7 CMOS Camera SATA table
EHCI2 Port8
ICH9M SMBUS Address UHCI5
Port9 SATA port0 HDD
Port10
UHCI6 SATA port1 ODD
Device HEX Address Port11
SATA port2
DDR SO-DIMM 0 A0 10100000
DDR SO-DIMM 1 A4 10100100 SATA port3
CLOCK GENERATOR D2 11010010
(ICS9LPRS387, SLG8SP556V) SATA port4
4 4
SATA port5
ZZZ1
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/02/27 Deciphered Date 2010/01/21 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
PCB-MB AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NCL20 M/B LA-5631P Schematic
DA80000GO00 Date: Tuesday, October 20, 2009 Sheet 3 of 41
A B C D E
5 4 3 2 1
+5VS +5VS
C638
1 2 @
1
1
0_0603_5%
R111 10U_0805_10V4Z D53 @
1SS355_SOD323-2
U19
Add it 090909. 1 VEN 8
2
GND D54
D 2 VIN 7 D
2
+VCCP +VCC_FAN1 GND
Place close to U1. 3 VO GND 6 1 2 @
EN_FAN1 1 2 4 VSET 5
(29) EN_FAN1 GND
0_0402_5% 1 BAS16_SOT23-3
(8) H_A#[3..16]
U1A R1007 C949 G990P11U SOP @
H_A#3 P2 M4 @ 0.1U_0402_16V4Z C639
A[3]# ADS# H_ADS# (8)
H_A#4 V4 J5 @ SA00002GW00 1 2
A[4]# BNR# H_BNR# (8) 2
H_A#5 W1 L5 10U_0805_10V4Z
A[5]# BPRI# H_BPRI# (8)
2
2
56_0402_5%
H_A#6 T4 C640
A[6]# +3VS
ADDR GROUP 0
H_A#7 AA1 N5 R10 1000P_0402_50V7K
A[7]# DEFER# H_DEFER# (8)
H_A#8 AB4 F38 51_0402_1% 1 2
A[8]# DRDY# H_DRDY# (8)
H_A#9 T2 J1 @
A[9]# DBSY# H_DBSY# (8)
1
R9
H_A#10 AC5 9/20
1
1
A[10]#
CONTROL
H_A#11 AD2 M2 R1586
A[11]# BR0# H_BR0# (8)
H_A#12 AD4 10K_0402_5%
A[12]#
H_A#13 AA5 B40 Change to NU 072709. 40mil
H_A#14 A[13]# IERR# JP32
AE5 D8 H_INIT# (18)
2
H_A#15 A[14]# INIT# +VCC_FAN1
AB2 A[15]# 1 1
H_A#16 AC1 N1 2
A[16]# LOCK# H_LOCK# (8) (29) FAN_SPEED1 2
Y4 FAN_PWM 3 5
(8) H_ADSTB#0 ADSTB[0]# (29) FAN_PWM 3 G1
G5 H_RESET# 1 4 6
RESET# H_RESET# (8) 4 G2
R1 K2 C641
(8) H_REQ#0 REQ[0]# RS[0]# H_RS#0 (8)
R5 H4 1000P_0402_50V7K E-T_3801-E04N-01R
(8) H_REQ#1 REQ[1]# RS[1]# H_RS#1 (8)
(8) H_REQ#2 U1 REQ[2]# RS[2]# K4 H_RS#2 (8) 2 CONN@ SP020907300
(8) H_REQ#3 P4 REQ[3]# TRDY# L1 H_TRDY# (8)
(8) H_REQ#4 W5 REQ[4]#
(8) H_A#[17..35] H2 H_HIT# (8) Change footprint 073109.
H_A#17 HIT#
AN1 A[17]# HITM# F2 H_HITM# (8)
H_A#18 AK4
C H_A#19 A[18]# C
AG1 A[19]# BPM[0]# AY8
ADDR GROUP 1
H_A#20 AT4 BA7
H_A#21 A[20]# BPM[1]#
AK2 A[21]# BPM[2]# BA5
H_A#22 AT2 AY2
A[22]# BPM[3]#
H_A#23 AH2 AV10 Del XDP_BPM#5 net.071309.
XDP/ITP SIGNALS
H_A#24 A[23]# PRDY#
AF4 A[24]# PREQ# AV2
H_A#25 AJ5 AV4 XDP_TCK
H_A#26 A[25]# TCK XDP_TDI +VCCP
AH4 A[26]# TDI AW7
H_A#27 AM4 AU1 XDP_TDO
H_A#28 A[27]# TDO XDP_TMS
AP4 A[28]# TMS AW5
H_A#29 AR5 AV8 XDP_TRST# XDP_TDI R1 1 2 51_0402_1%
H_A#30 A[29]# TRST# XDP_DBRESET#
AJ1 A[30]# DBR# J7 XDP_DBRESET# (19)
H_A#31 AL1 XDP_TMS R2 1 2 51_0402_1%
H_A#32 A[31]# R558 1 @
AM2 A[32]# 2 0_0402_5% H_PROCHOT# (40)
H_A#33 AU5 THERMAL XDP_TDO R3 1 2 51_0402_1%
H_A#34 A[33]# +VCCP
AP2 A[34]#
H_A#35 AR1 D38 R22 1 2 68_0402_5%
A[35]# PROCHOT# H_THERMDA_R R23
(8) H_ADSTB#1 AN5 ADSTB[1]# THERMDA BB34 1 2 0_0402_5% H_THERMDA
BD34 H_THERMDC_R R24 1 2 0_0402_5% H_THERMDC
THERMDC
(18) H_A20M# C7 A20M#
D4 B10 H_THERMTRIP# XDP_TRST# R6 1 2 51_0402_1%
(18) H_FERR# FERR# THERMTRIP# H_THERMTRIP# (8,18)
ICH
ICH
(18) H_IGNNE# F10 IGNNE#
H_THERMDA, H_THERMDC routing together, XDP_TCK R7 1 2 51_0402_1%
(18) H_STPCLK# F8 STPCLK#
(18) H_INTR C9 H CLK Trace width / Spacing = 10 / 10 mil This shall place near CPU
LINT0
(18) H_NMI C5 A35 CLK_CPU_BCLK (16) Change from 54.9 ohm to 51ohm 072709.
LINT1 BCLK[0]
(18) H_SMI# E5 SMI# BCLK[1] C35 CLK_CPU_BCLK# (16)
V2 RSVD01
B B
Y2 RSVD02
AG5 RSVD03
RESERVED
AL5 add it 073109.
RSVD04 XDP_DBRESET#
J9 RSVD05
F4 RSVD06
H8 XDP_TDO
RSVD07
XDP_TRST#
+3VS
XDP_TDI C1034
0.1U_0402_16V4Z
PENRYN SFF_UFCBGA956 1 2
XDP_TMS
XDP_TCK U7
H_THERMDA
@ @ @
3
2
3
2
3
2
1 VDD SMCLK 8 EC_SMB_CK2 (29)
D9 D10 D